1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Common Clock Framework support for Exynos3250 SoC. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 #include <linux/syscore_ops.h> 18 19 #include <dt-bindings/clock/exynos3250.h> 20 21 #include "clk.h" 22 #include "clk-pll.h" 23 24 #define SRC_LEFTBUS 0x4200 25 #define DIV_LEFTBUS 0x4500 26 #define GATE_IP_LEFTBUS 0x4800 27 #define SRC_RIGHTBUS 0x8200 28 #define DIV_RIGHTBUS 0x8500 29 #define GATE_IP_RIGHTBUS 0x8800 30 #define GATE_IP_PERIR 0x8960 31 #define MPLL_LOCK 0xc010 32 #define MPLL_CON0 0xc110 33 #define VPLL_LOCK 0xc020 34 #define VPLL_CON0 0xc120 35 #define UPLL_LOCK 0xc030 36 #define UPLL_CON0 0xc130 37 #define SRC_TOP0 0xc210 38 #define SRC_TOP1 0xc214 39 #define SRC_CAM 0xc220 40 #define SRC_MFC 0xc228 41 #define SRC_G3D 0xc22c 42 #define SRC_LCD 0xc234 43 #define SRC_ISP 0xc238 44 #define SRC_FSYS 0xc240 45 #define SRC_PERIL0 0xc250 46 #define SRC_PERIL1 0xc254 47 #define SRC_MASK_TOP 0xc310 48 #define SRC_MASK_CAM 0xc320 49 #define SRC_MASK_LCD 0xc334 50 #define SRC_MASK_ISP 0xc338 51 #define SRC_MASK_FSYS 0xc340 52 #define SRC_MASK_PERIL0 0xc350 53 #define SRC_MASK_PERIL1 0xc354 54 #define DIV_TOP 0xc510 55 #define DIV_CAM 0xc520 56 #define DIV_MFC 0xc528 57 #define DIV_G3D 0xc52c 58 #define DIV_LCD 0xc534 59 #define DIV_ISP 0xc538 60 #define DIV_FSYS0 0xc540 61 #define DIV_FSYS1 0xc544 62 #define DIV_FSYS2 0xc548 63 #define DIV_PERIL0 0xc550 64 #define DIV_PERIL1 0xc554 65 #define DIV_PERIL3 0xc55c 66 #define DIV_PERIL4 0xc560 67 #define DIV_PERIL5 0xc564 68 #define DIV_CAM1 0xc568 69 #define CLKDIV2_RATIO 0xc580 70 #define GATE_SCLK_CAM 0xc820 71 #define GATE_SCLK_MFC 0xc828 72 #define GATE_SCLK_G3D 0xc82c 73 #define GATE_SCLK_LCD 0xc834 74 #define GATE_SCLK_ISP_TOP 0xc838 75 #define GATE_SCLK_FSYS 0xc840 76 #define GATE_SCLK_PERIL 0xc850 77 #define GATE_IP_CAM 0xc920 78 #define GATE_IP_MFC 0xc928 79 #define GATE_IP_G3D 0xc92c 80 #define GATE_IP_LCD 0xc934 81 #define GATE_IP_ISP 0xc938 82 #define GATE_IP_FSYS 0xc940 83 #define GATE_IP_PERIL 0xc950 84 #define GATE_BLOCK 0xc970 85 #define APLL_LOCK 0x14000 86 #define APLL_CON0 0x14100 87 #define SRC_CPU 0x14200 88 #define DIV_CPU0 0x14500 89 #define DIV_CPU1 0x14504 90 #define PWR_CTRL1 0x15020 91 #define PWR_CTRL2 0x15024 92 93 /* Below definitions are used for PWR_CTRL settings */ 94 #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) 95 #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16) 96 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) 97 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) 98 #define PWR_CTRL1_USE_CORE3_WFE (1 << 7) 99 #define PWR_CTRL1_USE_CORE2_WFE (1 << 6) 100 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5) 101 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4) 102 #define PWR_CTRL1_USE_CORE3_WFI (1 << 3) 103 #define PWR_CTRL1_USE_CORE2_WFI (1 << 2) 104 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 105 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 106 107 /* list of PLLs to be registered */ 108 enum exynos3250_plls { 109 apll, mpll, vpll, upll, 110 nr_plls 111 }; 112 113 static void __iomem *reg_base; 114 115 /* 116 * Support for CMU save/restore across system suspends 117 */ 118 #ifdef CONFIG_PM_SLEEP 119 static struct samsung_clk_reg_dump *exynos3250_clk_regs; 120 121 static unsigned long exynos3250_cmu_clk_regs[] __initdata = { 122 SRC_LEFTBUS, 123 DIV_LEFTBUS, 124 GATE_IP_LEFTBUS, 125 SRC_RIGHTBUS, 126 DIV_RIGHTBUS, 127 GATE_IP_RIGHTBUS, 128 GATE_IP_PERIR, 129 MPLL_LOCK, 130 MPLL_CON0, 131 VPLL_LOCK, 132 VPLL_CON0, 133 UPLL_LOCK, 134 UPLL_CON0, 135 SRC_TOP0, 136 SRC_TOP1, 137 SRC_CAM, 138 SRC_MFC, 139 SRC_G3D, 140 SRC_LCD, 141 SRC_ISP, 142 SRC_FSYS, 143 SRC_PERIL0, 144 SRC_PERIL1, 145 SRC_MASK_TOP, 146 SRC_MASK_CAM, 147 SRC_MASK_LCD, 148 SRC_MASK_ISP, 149 SRC_MASK_FSYS, 150 SRC_MASK_PERIL0, 151 SRC_MASK_PERIL1, 152 DIV_TOP, 153 DIV_CAM, 154 DIV_MFC, 155 DIV_G3D, 156 DIV_LCD, 157 DIV_ISP, 158 DIV_FSYS0, 159 DIV_FSYS1, 160 DIV_FSYS2, 161 DIV_PERIL0, 162 DIV_PERIL1, 163 DIV_PERIL3, 164 DIV_PERIL4, 165 DIV_PERIL5, 166 DIV_CAM1, 167 CLKDIV2_RATIO, 168 GATE_SCLK_CAM, 169 GATE_SCLK_MFC, 170 GATE_SCLK_G3D, 171 GATE_SCLK_LCD, 172 GATE_SCLK_ISP_TOP, 173 GATE_SCLK_FSYS, 174 GATE_SCLK_PERIL, 175 GATE_IP_CAM, 176 GATE_IP_MFC, 177 GATE_IP_G3D, 178 GATE_IP_LCD, 179 GATE_IP_ISP, 180 GATE_IP_FSYS, 181 GATE_IP_PERIL, 182 GATE_BLOCK, 183 APLL_LOCK, 184 SRC_CPU, 185 DIV_CPU0, 186 DIV_CPU1, 187 PWR_CTRL1, 188 PWR_CTRL2, 189 }; 190 191 static int exynos3250_clk_suspend(void) 192 { 193 samsung_clk_save(reg_base, exynos3250_clk_regs, 194 ARRAY_SIZE(exynos3250_cmu_clk_regs)); 195 return 0; 196 } 197 198 static void exynos3250_clk_resume(void) 199 { 200 samsung_clk_restore(reg_base, exynos3250_clk_regs, 201 ARRAY_SIZE(exynos3250_cmu_clk_regs)); 202 } 203 204 static struct syscore_ops exynos3250_clk_syscore_ops = { 205 .suspend = exynos3250_clk_suspend, 206 .resume = exynos3250_clk_resume, 207 }; 208 209 static void exynos3250_clk_sleep_init(void) 210 { 211 exynos3250_clk_regs = 212 samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs, 213 ARRAY_SIZE(exynos3250_cmu_clk_regs)); 214 if (!exynos3250_clk_regs) { 215 pr_warn("%s: Failed to allocate sleep save data\n", __func__); 216 goto err; 217 } 218 219 register_syscore_ops(&exynos3250_clk_syscore_ops); 220 return; 221 err: 222 kfree(exynos3250_clk_regs); 223 } 224 #else 225 static inline void exynos3250_clk_sleep_init(void) { } 226 #endif 227 228 /* list of all parent clock list */ 229 PNAME(mout_vpllsrc_p) = { "fin_pll", }; 230 231 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 232 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; 233 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; 234 PNAME(mout_upll_p) = { "fin_pll", "fout_upll", }; 235 236 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", }; 237 PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", }; 238 PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", }; 239 PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", }; 240 241 PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", }; 242 PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", }; 243 244 PNAME(mout_gdl_p) = { "mout_mpll_user_l", }; 245 PNAME(mout_gdr_p) = { "mout_mpll_user_r", }; 246 247 PNAME(mout_aclk_400_mcuisp_sub_p) 248 = { "fin_pll", "div_aclk_400_mcuisp", }; 249 PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", }; 250 PNAME(mout_aclk_266_1_p) = { "mout_epll_user", }; 251 PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", }; 252 PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", }; 253 254 PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", }; 255 PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" }; 256 PNAME(group_sclk_p) = { "xxti", "xusbxti", 257 "none", "none", 258 "none", "none", "div_mpll_pre", 259 "mout_epll_user", "mout_vpll", }; 260 PNAME(group_sclk_audio_p) = { "audiocdclk", "none", 261 "none", "none", 262 "xxti", "xusbxti", 263 "div_mpll_pre", "mout_epll_user", 264 "mout_vpll", }; 265 PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti", 266 "none", "none", "none", 267 "none", "div_mpll_pre", 268 "mout_epll_user", "mout_vpll", 269 "div_cam_blk_320", }; 270 PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti", 271 "m_bitclkhsdiv4_2l", "none", 272 "none", "none", "div_mpll_pre", 273 "mout_epll_user", "mout_vpll", 274 "none", "none", "none", 275 "div_lcd_blk_145", }; 276 277 PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" }; 278 PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" }; 279 280 static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = { 281 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0), 282 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0), 283 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0), 284 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0), 285 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0), 286 287 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */ 288 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), 289 }; 290 291 static struct samsung_mux_clock mux_clks[] __initdata = { 292 /* 293 * NOTE: Following table is sorted by register address in ascending 294 * order and then bitfield shift in descending order, as it is done 295 * in the User's Manual. When adding new entries, please make sure 296 * that the order is preserved, to avoid merge conflicts and make 297 * further work with defined data easier. 298 */ 299 300 /* SRC_LEFTBUS */ 301 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p, 302 SRC_LEFTBUS, 4, 1), 303 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1), 304 305 /* SRC_RIGHTBUS */ 306 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p, 307 SRC_RIGHTBUS, 4, 1), 308 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1), 309 310 /* SRC_TOP0 */ 311 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1), 312 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1), 313 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1), 314 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1), 315 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1), 316 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1), 317 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1), 318 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 319 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1), 320 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1), 321 322 /* SRC_TOP1 */ 323 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1), 324 MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p, 325 SRC_TOP1, 24, 1), 326 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1), 327 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1), 328 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1), 329 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), 330 331 /* SRC_CAM */ 332 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4), 333 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4), 334 335 /* SRC_MFC */ 336 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 337 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1), 338 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1), 339 340 /* SRC_G3D */ 341 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1), 342 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1), 343 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1), 344 345 /* SRC_LCD */ 346 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4), 347 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4), 348 349 /* SRC_ISP */ 350 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4), 351 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4), 352 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4), 353 354 /* SRC_FSYS */ 355 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), 356 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3), 357 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3), 358 359 /* SRC_PERIL0 */ 360 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), 361 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), 362 363 /* SRC_PERIL1 */ 364 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4), 365 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4), 366 MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4), 367 368 /* SRC_CPU */ 369 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p, 370 SRC_CPU, 24, 1), 371 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1), 372 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1), 373 MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 374 }; 375 376 static struct samsung_div_clock div_clks[] __initdata = { 377 /* 378 * NOTE: Following table is sorted by register address in ascending 379 * order and then bitfield shift in descending order, as it is done 380 * in the User's Manual. When adding new entries, please make sure 381 * that the order is preserved, to avoid merge conflicts and make 382 * further work with defined data easier. 383 */ 384 385 /* DIV_LEFTBUS */ 386 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), 387 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4), 388 389 /* DIV_RIGHTBUS */ 390 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), 391 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4), 392 393 /* DIV_TOP */ 394 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2), 395 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp", 396 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3), 397 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3), 398 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3), 399 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3), 400 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4), 401 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3), 402 403 /* DIV_CAM */ 404 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), 405 DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4), 406 407 /* DIV_MFC */ 408 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4), 409 410 /* DIV_G3D */ 411 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4), 412 413 /* DIV_LCD */ 414 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4, 415 CLK_SET_RATE_PARENT, 0), 416 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4), 417 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4), 418 419 /* DIV_ISP */ 420 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4), 421 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp", 422 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0), 423 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4), 424 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp", 425 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0), 426 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4), 427 428 /* DIV_FSYS0 */ 429 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8, 430 CLK_SET_RATE_PARENT, 0), 431 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4), 432 433 /* DIV_FSYS1 */ 434 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8, 435 CLK_SET_RATE_PARENT, 0), 436 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 437 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8, 438 CLK_SET_RATE_PARENT, 0), 439 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 440 441 /* DIV_PERIL0 */ 442 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 443 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 444 445 /* DIV_PERIL1 */ 446 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8, 447 CLK_SET_RATE_PARENT, 0), 448 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), 449 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8, 450 CLK_SET_RATE_PARENT, 0), 451 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), 452 453 /* DIV_PERIL4 */ 454 DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8), 455 DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4), 456 457 /* DIV_PERIL5 */ 458 DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6), 459 460 /* DIV_CPU0 */ 461 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3), 462 DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3), 463 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3), 464 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3), 465 DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3), 466 DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3), 467 468 /* DIV_CPU1 */ 469 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3), 470 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), 471 }; 472 473 static struct samsung_gate_clock gate_clks[] __initdata = { 474 /* 475 * NOTE: Following table is sorted by register address in ascending 476 * order and then bitfield shift in descending order, as it is done 477 * in the User's Manual. When adding new entries, please make sure 478 * that the order is preserved, to avoid merge conflicts and make 479 * further work with defined data easier. 480 */ 481 482 /* GATE_IP_LEFTBUS */ 483 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6, 484 CLK_IGNORE_UNUSED, 0), 485 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4, 486 CLK_IGNORE_UNUSED, 0), 487 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1, 488 CLK_IGNORE_UNUSED, 0), 489 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0, 490 CLK_IGNORE_UNUSED, 0), 491 492 /* GATE_IP_RIGHTBUS */ 493 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100", 494 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0), 495 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100", 496 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0), 497 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100", 498 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0), 499 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2, 500 CLK_IGNORE_UNUSED, 0), 501 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1, 502 CLK_IGNORE_UNUSED, 0), 503 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0, 504 CLK_IGNORE_UNUSED, 0), 505 506 /* GATE_IP_PERIR */ 507 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22, 508 CLK_IGNORE_UNUSED, 0), 509 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21, 510 CLK_IGNORE_UNUSED, 0), 511 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100", 512 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0), 513 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100", 514 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0), 515 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18, 516 CLK_IGNORE_UNUSED, 0), 517 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100", 518 GATE_IP_PERIR, 17, 0, 0), 519 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0), 520 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0), 521 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0), 522 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0), 523 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12, 524 CLK_IGNORE_UNUSED, 0), 525 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10, 526 CLK_IGNORE_UNUSED, 0), 527 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9, 528 CLK_IGNORE_UNUSED, 0), 529 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8, 530 CLK_IGNORE_UNUSED, 0), 531 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7, 532 CLK_IGNORE_UNUSED, 0), 533 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6, 534 CLK_IGNORE_UNUSED, 0), 535 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5, 536 CLK_IGNORE_UNUSED, 0), 537 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4, 538 CLK_IGNORE_UNUSED, 0), 539 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3, 540 CLK_IGNORE_UNUSED, 0), 541 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2, 542 CLK_IGNORE_UNUSED, 0), 543 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1, 544 CLK_IGNORE_UNUSED, 0), 545 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0, 546 CLK_IGNORE_UNUSED, 0), 547 548 /* GATE_SCLK_CAM */ 549 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk", 550 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0), 551 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk", 552 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0), 553 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk", 554 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0), 555 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk", 556 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0), 557 558 /* GATE_SCLK_MFC */ 559 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc", 560 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0), 561 562 /* GATE_SCLK_G3D */ 563 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", 564 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0), 565 566 /* GATE_SCLK_LCD */ 567 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0", 568 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0), 569 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre", 570 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0), 571 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", 572 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0), 573 574 /* GATE_SCLK_ISP_TOP */ 575 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", 576 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0), 577 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp", 578 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0), 579 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp", 580 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0), 581 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp", 582 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0), 583 584 /* GATE_SCLK_FSYS */ 585 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0), 586 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre", 587 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 588 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", 589 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), 590 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", 591 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 592 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", 593 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 594 595 /* GATE_SCLK_PERIL */ 596 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s", 597 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0), 598 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm", 599 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0), 600 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre", 601 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), 602 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", 603 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), 604 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", 605 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), 606 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", 607 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0), 608 609 /* GATE_IP_CAM */ 610 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19, 611 CLK_IGNORE_UNUSED, 0), 612 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320", 613 GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0), 614 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320", 615 GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0), 616 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320", 617 GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0), 618 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320", 619 GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0), 620 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320", 621 GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0), 622 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320", 623 GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0), 624 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320", 625 GATE_IP_CAM, 11, 0, 0), 626 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320", 627 GATE_IP_CAM, 9, 0, 0), 628 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320", 629 GATE_IP_CAM, 8, 0, 0), 630 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320", 631 GATE_IP_CAM, 7, 0, 0), 632 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0), 633 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320", 634 GATE_IP_CAM, 2, 0, 0), 635 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0), 636 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0), 637 638 /* GATE_IP_MFC */ 639 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5, 640 CLK_IGNORE_UNUSED, 0), 641 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3, 642 CLK_IGNORE_UNUSED, 0), 643 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0), 644 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0), 645 646 /* GATE_IP_G3D */ 647 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0), 648 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2, 649 CLK_IGNORE_UNUSED, 0), 650 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1, 651 CLK_IGNORE_UNUSED, 0), 652 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0), 653 654 /* GATE_IP_LCD */ 655 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7, 656 CLK_IGNORE_UNUSED, 0), 657 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6, 658 CLK_IGNORE_UNUSED, 0), 659 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5, 660 CLK_IGNORE_UNUSED, 0), 661 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0), 662 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0), 663 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0), 664 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0), 665 666 /* GATE_IP_ISP */ 667 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0), 668 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub", 669 GATE_IP_ISP, 3, 0, 0), 670 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub", 671 GATE_IP_ISP, 2, 0, 0), 672 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub", 673 GATE_IP_ISP, 1, 0, 0), 674 675 /* GATE_IP_FSYS */ 676 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0), 677 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17, 678 CLK_IGNORE_UNUSED, 0), 679 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), 680 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), 681 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), 682 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), 683 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), 684 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), 685 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0), 686 687 /* GATE_IP_PERIL */ 688 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0), 689 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0), 690 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0), 691 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0), 692 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0), 693 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0), 694 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0), 695 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0), 696 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0), 697 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0), 698 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), 699 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), 700 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), 701 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), 702 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), 703 }; 704 705 /* APLL & MPLL & BPLL & UPLL */ 706 static struct samsung_pll_rate_table exynos3250_pll_rates[] = { 707 PLL_35XX_RATE(1200000000, 400, 4, 1), 708 PLL_35XX_RATE(1100000000, 275, 3, 1), 709 PLL_35XX_RATE(1066000000, 533, 6, 1), 710 PLL_35XX_RATE(1000000000, 250, 3, 1), 711 PLL_35XX_RATE( 960000000, 320, 4, 1), 712 PLL_35XX_RATE( 900000000, 300, 4, 1), 713 PLL_35XX_RATE( 850000000, 425, 6, 1), 714 PLL_35XX_RATE( 800000000, 200, 3, 1), 715 PLL_35XX_RATE( 700000000, 175, 3, 1), 716 PLL_35XX_RATE( 667000000, 667, 12, 1), 717 PLL_35XX_RATE( 600000000, 400, 4, 2), 718 PLL_35XX_RATE( 533000000, 533, 6, 2), 719 PLL_35XX_RATE( 520000000, 260, 3, 2), 720 PLL_35XX_RATE( 500000000, 250, 3, 2), 721 PLL_35XX_RATE( 400000000, 200, 3, 2), 722 PLL_35XX_RATE( 200000000, 200, 3, 3), 723 PLL_35XX_RATE( 100000000, 200, 3, 4), 724 { /* sentinel */ } 725 }; 726 727 /* VPLL */ 728 static struct samsung_pll_rate_table exynos3250_vpll_rates[] = { 729 PLL_36XX_RATE(600000000, 100, 2, 1, 0), 730 PLL_36XX_RATE(533000000, 266, 3, 2, 32768), 731 PLL_36XX_RATE(519230987, 173, 2, 2, 5046), 732 PLL_36XX_RATE(500000000, 250, 3, 2, 0), 733 PLL_36XX_RATE(445500000, 148, 2, 2, 32768), 734 PLL_36XX_RATE(445055007, 148, 2, 2, 23047), 735 PLL_36XX_RATE(400000000, 200, 3, 2, 0), 736 PLL_36XX_RATE(371250000, 123, 2, 2, 49152), 737 PLL_36XX_RATE(370878997, 185, 3, 2, 28803), 738 PLL_36XX_RATE(340000000, 170, 3, 2, 0), 739 PLL_36XX_RATE(335000015, 111, 2, 2, 43691), 740 PLL_36XX_RATE(333000000, 111, 2, 2, 0), 741 PLL_36XX_RATE(330000000, 110, 2, 2, 0), 742 PLL_36XX_RATE(320000015, 106, 2, 2, 43691), 743 PLL_36XX_RATE(300000000, 100, 2, 2, 0), 744 PLL_36XX_RATE(275000000, 275, 3, 3, 0), 745 PLL_36XX_RATE(222750000, 148, 2, 3, 32768), 746 PLL_36XX_RATE(222528007, 148, 2, 3, 23069), 747 PLL_36XX_RATE(160000000, 160, 3, 3, 0), 748 PLL_36XX_RATE(148500000, 99, 2, 3, 0), 749 PLL_36XX_RATE(148352005, 98, 2, 3, 59070), 750 PLL_36XX_RATE(108000000, 144, 2, 4, 0), 751 PLL_36XX_RATE( 74250000, 99, 2, 4, 0), 752 PLL_36XX_RATE( 74176002, 98, 3, 4, 59070), 753 PLL_36XX_RATE( 54054000, 216, 3, 5, 14156), 754 PLL_36XX_RATE( 54000000, 144, 2, 5, 0), 755 { /* sentinel */ } 756 }; 757 758 static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = { 759 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 760 APLL_LOCK, APLL_CON0, NULL), 761 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 762 MPLL_LOCK, MPLL_CON0, NULL), 763 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", 764 VPLL_LOCK, VPLL_CON0, NULL), 765 [upll] = PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll", 766 UPLL_LOCK, UPLL_CON0, NULL), 767 }; 768 769 static void __init exynos3_core_down_clock(void) 770 { 771 unsigned int tmp; 772 773 /* 774 * Enable arm clock down (in idle) and set arm divider 775 * ratios in WFI/WFE state. 776 */ 777 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) | 778 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | 779 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | 780 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); 781 __raw_writel(tmp, reg_base + PWR_CTRL1); 782 783 /* 784 * Disable the clock up feature on Exynos4x12, in case it was 785 * enabled by bootloader. 786 */ 787 __raw_writel(0x0, reg_base + PWR_CTRL2); 788 } 789 790 static void __init exynos3250_cmu_init(struct device_node *np) 791 { 792 struct samsung_clk_provider *ctx; 793 794 reg_base = of_iomap(np, 0); 795 if (!reg_base) 796 panic("%s: failed to map registers\n", __func__); 797 798 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 799 if (!ctx) 800 panic("%s: unable to allocate context.\n", __func__); 801 802 samsung_clk_register_fixed_factor(ctx, fixed_factor_clks, 803 ARRAY_SIZE(fixed_factor_clks)); 804 805 exynos3250_plls[apll].rate_table = exynos3250_pll_rates; 806 exynos3250_plls[mpll].rate_table = exynos3250_pll_rates; 807 exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates; 808 exynos3250_plls[upll].rate_table = exynos3250_pll_rates; 809 810 samsung_clk_register_pll(ctx, exynos3250_plls, 811 ARRAY_SIZE(exynos3250_plls), reg_base); 812 813 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks)); 814 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks)); 815 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks)); 816 817 exynos3_core_down_clock(); 818 819 exynos3250_clk_sleep_init(); 820 821 samsung_clk_of_add_provider(np, ctx); 822 } 823 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); 824