1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2021 Linaro Ltd.
4  * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com>
5  * Author: Sam Protsenko <semen.protsenko@linaro.org>
6  * Author: Dávid Virág <virag.david003@gmail.com>
7  *
8  * This file contains shared functions used by some arm64 Exynos SoCs,
9  * such as Exynos7885 or Exynos850 to register and init CMUs.
10  */
11 #include <linux/clk.h>
12 #include <linux/of_address.h>
13 
14 #include "clk-exynos-arm64.h"
15 
16 /* Gate register bits */
17 #define GATE_MANUAL		BIT(20)
18 #define GATE_ENABLE_HWACG	BIT(28)
19 
20 /* Gate register offsets range */
21 #define GATE_OFF_START		0x2000
22 #define GATE_OFF_END		0x2fff
23 
24 /**
25  * exynos_arm64_init_clocks - Set clocks initial configuration
26  * @np:			CMU device tree node with "reg" property (CMU addr)
27  * @reg_offs:		Register offsets array for clocks to init
28  * @reg_offs_len:	Number of register offsets in reg_offs array
29  *
30  * Set manual control mode for all gate clocks.
31  */
32 static void __init exynos_arm64_init_clocks(struct device_node *np,
33 		const unsigned long *reg_offs, size_t reg_offs_len)
34 {
35 	void __iomem *reg_base;
36 	size_t i;
37 
38 	reg_base = of_iomap(np, 0);
39 	if (!reg_base)
40 		panic("%s: failed to map registers\n", __func__);
41 
42 	for (i = 0; i < reg_offs_len; ++i) {
43 		void __iomem *reg = reg_base + reg_offs[i];
44 		u32 val;
45 
46 		/* Modify only gate clock registers */
47 		if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
48 			continue;
49 
50 		val = readl(reg);
51 		val |= GATE_MANUAL;
52 		val &= ~GATE_ENABLE_HWACG;
53 		writel(val, reg);
54 	}
55 
56 	iounmap(reg_base);
57 }
58 
59 /**
60  * exynos_arm64_register_cmu - Register specified Exynos CMU domain
61  * @dev:	Device object; may be NULL if this function is not being
62  *		called from platform driver probe function
63  * @np:		CMU device tree node
64  * @cmu:	CMU data
65  *
66  * Register specified CMU domain, which includes next steps:
67  *
68  * 1. Enable parent clock of @cmu CMU
69  * 2. Set initial registers configuration for @cmu CMU clocks
70  * 3. Register @cmu CMU clocks using Samsung clock framework API
71  */
72 void __init exynos_arm64_register_cmu(struct device *dev,
73 		struct device_node *np, const struct samsung_cmu_info *cmu)
74 {
75 	/* Keep CMU parent clock running (needed for CMU registers access) */
76 	if (cmu->clk_name) {
77 		struct clk *parent_clk;
78 
79 		if (dev)
80 			parent_clk = clk_get(dev, cmu->clk_name);
81 		else
82 			parent_clk = of_clk_get_by_name(np, cmu->clk_name);
83 
84 		if (IS_ERR(parent_clk)) {
85 			pr_err("%s: could not find bus clock %s; err = %ld\n",
86 			       __func__, cmu->clk_name, PTR_ERR(parent_clk));
87 		} else {
88 			clk_prepare_enable(parent_clk);
89 		}
90 	}
91 
92 	exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
93 	samsung_cmu_register_one(np, cmu);
94 }
95