1*cfe238e4SDavid Virag // SPDX-License-Identifier: GPL-2.0-only 2*cfe238e4SDavid Virag /* 3*cfe238e4SDavid Virag * Copyright (C) 2021 Linaro Ltd. 4*cfe238e4SDavid Virag * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com> 5*cfe238e4SDavid Virag * Author: Sam Protsenko <semen.protsenko@linaro.org> 6*cfe238e4SDavid Virag * Author: Dávid Virág <virag.david003@gmail.com> 7*cfe238e4SDavid Virag * 8*cfe238e4SDavid Virag * This file contains shared functions used by some arm64 Exynos SoCs, 9*cfe238e4SDavid Virag * such as Exynos7885 or Exynos850 to register and init CMUs. 10*cfe238e4SDavid Virag */ 11*cfe238e4SDavid Virag #include <linux/clk.h> 12*cfe238e4SDavid Virag #include <linux/of_address.h> 13*cfe238e4SDavid Virag 14*cfe238e4SDavid Virag #include "clk-exynos-arm64.h" 15*cfe238e4SDavid Virag 16*cfe238e4SDavid Virag /* Gate register bits */ 17*cfe238e4SDavid Virag #define GATE_MANUAL BIT(20) 18*cfe238e4SDavid Virag #define GATE_ENABLE_HWACG BIT(28) 19*cfe238e4SDavid Virag 20*cfe238e4SDavid Virag /* Gate register offsets range */ 21*cfe238e4SDavid Virag #define GATE_OFF_START 0x2000 22*cfe238e4SDavid Virag #define GATE_OFF_END 0x2fff 23*cfe238e4SDavid Virag 24*cfe238e4SDavid Virag /** 25*cfe238e4SDavid Virag * exynos_arm64_init_clocks - Set clocks initial configuration 26*cfe238e4SDavid Virag * @np: CMU device tree node with "reg" property (CMU addr) 27*cfe238e4SDavid Virag * @reg_offs: Register offsets array for clocks to init 28*cfe238e4SDavid Virag * @reg_offs_len: Number of register offsets in reg_offs array 29*cfe238e4SDavid Virag * 30*cfe238e4SDavid Virag * Set manual control mode for all gate clocks. 31*cfe238e4SDavid Virag */ 32*cfe238e4SDavid Virag static void __init exynos_arm64_init_clocks(struct device_node *np, 33*cfe238e4SDavid Virag const unsigned long *reg_offs, size_t reg_offs_len) 34*cfe238e4SDavid Virag { 35*cfe238e4SDavid Virag void __iomem *reg_base; 36*cfe238e4SDavid Virag size_t i; 37*cfe238e4SDavid Virag 38*cfe238e4SDavid Virag reg_base = of_iomap(np, 0); 39*cfe238e4SDavid Virag if (!reg_base) 40*cfe238e4SDavid Virag panic("%s: failed to map registers\n", __func__); 41*cfe238e4SDavid Virag 42*cfe238e4SDavid Virag for (i = 0; i < reg_offs_len; ++i) { 43*cfe238e4SDavid Virag void __iomem *reg = reg_base + reg_offs[i]; 44*cfe238e4SDavid Virag u32 val; 45*cfe238e4SDavid Virag 46*cfe238e4SDavid Virag /* Modify only gate clock registers */ 47*cfe238e4SDavid Virag if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END) 48*cfe238e4SDavid Virag continue; 49*cfe238e4SDavid Virag 50*cfe238e4SDavid Virag val = readl(reg); 51*cfe238e4SDavid Virag val |= GATE_MANUAL; 52*cfe238e4SDavid Virag val &= ~GATE_ENABLE_HWACG; 53*cfe238e4SDavid Virag writel(val, reg); 54*cfe238e4SDavid Virag } 55*cfe238e4SDavid Virag 56*cfe238e4SDavid Virag iounmap(reg_base); 57*cfe238e4SDavid Virag } 58*cfe238e4SDavid Virag 59*cfe238e4SDavid Virag /** 60*cfe238e4SDavid Virag * exynos_arm64_register_cmu - Register specified Exynos CMU domain 61*cfe238e4SDavid Virag * @dev: Device object; may be NULL if this function is not being 62*cfe238e4SDavid Virag * called from platform driver probe function 63*cfe238e4SDavid Virag * @np: CMU device tree node 64*cfe238e4SDavid Virag * @cmu: CMU data 65*cfe238e4SDavid Virag * 66*cfe238e4SDavid Virag * Register specified CMU domain, which includes next steps: 67*cfe238e4SDavid Virag * 68*cfe238e4SDavid Virag * 1. Enable parent clock of @cmu CMU 69*cfe238e4SDavid Virag * 2. Set initial registers configuration for @cmu CMU clocks 70*cfe238e4SDavid Virag * 3. Register @cmu CMU clocks using Samsung clock framework API 71*cfe238e4SDavid Virag */ 72*cfe238e4SDavid Virag void __init exynos_arm64_register_cmu(struct device *dev, 73*cfe238e4SDavid Virag struct device_node *np, const struct samsung_cmu_info *cmu) 74*cfe238e4SDavid Virag { 75*cfe238e4SDavid Virag /* Keep CMU parent clock running (needed for CMU registers access) */ 76*cfe238e4SDavid Virag if (cmu->clk_name) { 77*cfe238e4SDavid Virag struct clk *parent_clk; 78*cfe238e4SDavid Virag 79*cfe238e4SDavid Virag if (dev) 80*cfe238e4SDavid Virag parent_clk = clk_get(dev, cmu->clk_name); 81*cfe238e4SDavid Virag else 82*cfe238e4SDavid Virag parent_clk = of_clk_get_by_name(np, cmu->clk_name); 83*cfe238e4SDavid Virag 84*cfe238e4SDavid Virag if (IS_ERR(parent_clk)) { 85*cfe238e4SDavid Virag pr_err("%s: could not find bus clock %s; err = %ld\n", 86*cfe238e4SDavid Virag __func__, cmu->clk_name, PTR_ERR(parent_clk)); 87*cfe238e4SDavid Virag } else { 88*cfe238e4SDavid Virag clk_prepare_enable(parent_clk); 89*cfe238e4SDavid Virag } 90*cfe238e4SDavid Virag } 91*cfe238e4SDavid Virag 92*cfe238e4SDavid Virag exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs); 93*cfe238e4SDavid Virag samsung_cmu_register_one(np, cmu); 94*cfe238e4SDavid Virag } 95