1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Common Clock Framework support for all PLL's in Samsung platforms 9 */ 10 11 #ifndef __SAMSUNG_CLK_CPU_H 12 #define __SAMSUNG_CLK_CPU_H 13 14 #include "clk.h" 15 16 /** 17 * struct exynos_cpuclk_data: config data to setup cpu clocks. 18 * @prate: frequency of the primary parent clock (in KHz). 19 * @div0: value to be programmed in the div_cpu0 register. 20 * @div1: value to be programmed in the div_cpu1 register. 21 * 22 * This structure holds the divider configuration data for dividers in the CPU 23 * clock domain. The parent frequency at which these divider values are valid is 24 * specified in @prate. The @prate is the frequency of the primary parent clock. 25 * For CPU clock domains that do not have a DIV1 register, the @div1 member 26 * value is not used. 27 */ 28 struct exynos_cpuclk_cfg_data { 29 unsigned long prate; 30 unsigned long div0; 31 unsigned long div1; 32 }; 33 34 /** 35 * struct exynos_cpuclk: information about clock supplied to a CPU core. 36 * @hw: handle between CCF and CPU clock. 37 * @alt_parent: alternate parent clock to use when switching the speed 38 * of the primary parent clock. 39 * @ctrl_base: base address of the clock controller. 40 * @lock: cpu clock domain register access lock. 41 * @cfg: cpu clock rate configuration data. 42 * @num_cfgs: number of array elements in @cfg array. 43 * @clk_nb: clock notifier registered for changes in clock speed of the 44 * primary parent clock. 45 * @flags: configuration flags for the CPU clock. 46 * 47 * This structure holds information required for programming the CPU clock for 48 * various clock speeds. 49 */ 50 struct exynos_cpuclk { 51 struct clk_hw hw; 52 struct clk *alt_parent; 53 void __iomem *ctrl_base; 54 spinlock_t *lock; 55 const struct exynos_cpuclk_cfg_data *cfg; 56 const unsigned long num_cfgs; 57 struct notifier_block clk_nb; 58 unsigned long flags; 59 60 /* The CPU clock registers have DIV1 configuration register */ 61 #define CLK_CPU_HAS_DIV1 (1 << 0) 62 /* When ALT parent is active, debug clocks need safe divider values */ 63 #define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) 64 /* The CPU clock registers have Exynos5433-compatible layout */ 65 #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2) 66 }; 67 68 extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 69 unsigned int lookup_id, const char *name, 70 const char *parent, const char *alt_parent, 71 unsigned long offset, 72 const struct exynos_cpuclk_cfg_data *cfg, 73 unsigned long num_cfgs, unsigned long flags); 74 75 #endif /* __SAMSUNG_CLK_CPU_H */ 76