1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
4  * Author: Shawn Lin <shawn.lin@rock-chips.com>
5  *         Andy Yan <andy.yan@rock-chips.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/syscore_ops.h>
13 #include <dt-bindings/clock/rv1108-cru.h>
14 #include "clk.h"
15 
16 #define RV1108_GRF_SOC_STATUS0	0x480
17 
18 enum rv1108_plls {
19 	apll, dpll, gpll,
20 };
21 
22 static struct rockchip_pll_rate_table rv1108_pll_rates[] = {
23 	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
24 	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
25 	RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
26 	RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
27 	RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
28 	RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
29 	RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
30 	RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
31 	RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
32 	RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
33 	RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
34 	RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
35 	RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
36 	RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
37 	RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
38 	RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
39 	RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
40 	RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
41 	RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
42 	RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
43 	RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
44 	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
45 	RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
46 	RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
47 	RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
48 	RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
49 	RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
50 	RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
51 	RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
52 	RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
53 	RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
54 	RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
55 	RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
56 	RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
57 	RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
58 	RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
59 	RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
60 	RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
61 	RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
62 	RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
63 	RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
64 	RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
65 	RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
66 	{ /* sentinel */ },
67 };
68 
69 #define RV1108_DIV_CORE_MASK		0xf
70 #define RV1108_DIV_CORE_SHIFT		4
71 
72 #define RV1108_CLKSEL0(_core_peri_div)	\
73 	{				\
74 		.reg = RV1108_CLKSEL_CON(1),	\
75 		.val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\
76 				RV1108_DIV_CORE_SHIFT)	\
77 	}
78 
79 #define RV1108_CPUCLK_RATE(_prate, _core_peri_div)			\
80 	{								\
81 		.prate = _prate,					\
82 		.divs = {						\
83 			RV1108_CLKSEL0(_core_peri_div),		\
84 		},							\
85 	}
86 
87 static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
88 	RV1108_CPUCLK_RATE(1608000000, 7),
89 	RV1108_CPUCLK_RATE(1512000000, 7),
90 	RV1108_CPUCLK_RATE(1488000000, 5),
91 	RV1108_CPUCLK_RATE(1416000000, 5),
92 	RV1108_CPUCLK_RATE(1392000000, 5),
93 	RV1108_CPUCLK_RATE(1296000000, 5),
94 	RV1108_CPUCLK_RATE(1200000000, 5),
95 	RV1108_CPUCLK_RATE(1104000000, 5),
96 	RV1108_CPUCLK_RATE(1008000000, 5),
97 	RV1108_CPUCLK_RATE(912000000, 5),
98 	RV1108_CPUCLK_RATE(816000000, 3),
99 	RV1108_CPUCLK_RATE(696000000, 3),
100 	RV1108_CPUCLK_RATE(600000000, 3),
101 	RV1108_CPUCLK_RATE(500000000, 3),
102 	RV1108_CPUCLK_RATE(408000000, 1),
103 	RV1108_CPUCLK_RATE(312000000, 1),
104 	RV1108_CPUCLK_RATE(216000000, 1),
105 	RV1108_CPUCLK_RATE(96000000, 1),
106 };
107 
108 static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
109 	.core_reg[0] = RV1108_CLKSEL_CON(0),
110 	.div_core_shift[0] = 0,
111 	.div_core_mask[0] = 0x1f,
112 	.num_cores = 1,
113 	.mux_core_alt = 1,
114 	.mux_core_main = 0,
115 	.mux_core_shift = 8,
116 	.mux_core_mask = 0x3,
117 };
118 
119 PNAME(mux_pll_p)		= { "xin24m", "xin24m"};
120 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr", "apll_ddr" };
121 PNAME(mux_armclk_p)		= { "apll_core", "gpll_core", "dpll_core" };
122 PNAME(mux_usb480m_pre_p)	= { "usbphy", "xin24m" };
123 PNAME(mux_hdmiphy_phy_p)	= { "hdmiphy", "xin24m" };
124 PNAME(mux_dclk_hdmiphy_pre_p)	= { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
125 PNAME(mux_pll_src_4plls_p)	= { "dpll", "gpll", "hdmiphy", "usb480m" };
126 PNAME(mux_pll_src_2plls_p)	= { "dpll", "gpll" };
127 PNAME(mux_pll_src_apll_gpll_p)	= { "apll", "gpll" };
128 PNAME(mux_aclk_peri_src_p)	= { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
129 PNAME(mux_aclk_bus_src_p)	= { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" };
130 PNAME(mux_mmc_src_p)		= { "dpll", "gpll", "xin24m", "usb480m" };
131 PNAME(mux_pll_src_dpll_gpll_usb480m_p)	= { "dpll", "gpll", "usb480m" };
132 PNAME(mux_uart0_p)		= { "uart0_src", "uart0_frac", "xin24m" };
133 PNAME(mux_uart1_p)		= { "uart1_src", "uart1_frac", "xin24m" };
134 PNAME(mux_uart2_p)		= { "uart2_src", "uart2_frac", "xin24m" };
135 PNAME(mux_sclk_mac_p)		= { "sclk_mac_pre", "ext_gmac" };
136 PNAME(mux_i2s0_pre_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
137 PNAME(mux_i2s_out_p)		= { "i2s0_pre", "xin12m" };
138 PNAME(mux_i2s1_p)		= { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
139 PNAME(mux_i2s2_p)		= { "i2s2_src", "i2s2_frac", "dummy", "xin12m" };
140 PNAME(mux_wifi_src_p)		= { "gpll", "xin24m" };
141 PNAME(mux_cifout_src_p)	= { "hdmiphy", "gpll" };
142 PNAME(mux_cifout_p)		= { "sclk_cifout_src", "xin24m" };
143 PNAME(mux_sclk_cif0_src_p)	= { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" };
144 PNAME(mux_sclk_cif1_src_p)	= { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" };
145 PNAME(mux_sclk_cif2_src_p)	= { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" };
146 PNAME(mux_sclk_cif3_src_p)	= { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" };
147 PNAME(mux_dsp_src_p)		= { "dpll", "gpll", "apll", "usb480m" };
148 PNAME(mux_dclk_hdmiphy_p)	= { "hdmiphy", "xin24m" };
149 PNAME(mux_dclk_vop_p)		= { "dclk_hdmiphy", "dclk_vop_src" };
150 PNAME(mux_hdmi_cec_src_p)		= { "dpll", "gpll", "xin24m" };
151 PNAME(mux_cvbs_src_p)		= { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" };
152 
153 static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
154 	[apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
155 		     RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates),
156 	[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
157 		     RV1108_PLL_CON(11), 8, 1, 0, NULL),
158 	[gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
159 		     RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates),
160 };
161 
162 #define MFLAGS CLK_MUX_HIWORD_MASK
163 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
164 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
165 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
166 
167 static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata =
168 	MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
169 			RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
170 
171 static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata =
172 	MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
173 			RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
174 
175 static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata =
176 	MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
177 			RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
178 
179 static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata =
180 	MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT,
181 			RV1108_CLKSEL_CON(5), 12, 2, MFLAGS);
182 
183 static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata =
184 	MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
185 			RV1108_CLKSEL_CON(6), 12, 2, MFLAGS);
186 
187 static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata =
188 	MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
189 			RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
190 
191 static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
192 	MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
193 			RV1108_MISC_CON, 13, 1, MFLAGS),
194 	MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
195 			RV1108_MISC_CON, 15, 1, MFLAGS),
196 	/*
197 	 * Clock-Architecture Diagram 2
198 	 */
199 
200 	/* PD_CORE */
201 	GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
202 			RV1108_CLKGATE_CON(0), 1, GFLAGS),
203 	GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
204 			RV1108_CLKGATE_CON(0), 0, GFLAGS),
205 	GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
206 			RV1108_CLKGATE_CON(0), 2, GFLAGS),
207 	COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED,
208 			RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
209 			RV1108_CLKGATE_CON(0), 5, GFLAGS),
210 	COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED,
211 			RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
212 			RV1108_CLKGATE_CON(0), 4, GFLAGS),
213 	GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
214 			RV1108_CLKGATE_CON(11), 0, GFLAGS),
215 	GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
216 			RV1108_CLKGATE_CON(11), 1, GFLAGS),
217 
218 	/* PD_RKVENC */
219 	COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0,
220 			RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
221 			RV1108_CLKGATE_CON(8), 8, GFLAGS),
222 	FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4,
223 			RV1108_CLKGATE_CON(8), 10, GFLAGS),
224 	COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0,
225 			RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS,
226 			RV1108_CLKGATE_CON(8), 9, GFLAGS),
227 	GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
228 			RV1108_CLKGATE_CON(19), 8, GFLAGS),
229 	GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
230 			RV1108_CLKGATE_CON(19), 9, GFLAGS),
231 	GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
232 			RV1108_CLKGATE_CON(19), 11, GFLAGS),
233 	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
234 			RV1108_CLKGATE_CON(19), 10, GFLAGS),
235 
236 	/* PD_RKVDEC */
237 	COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0,
238 			RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
239 			RV1108_CLKGATE_CON(8), 2, GFLAGS),
240 	FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4,
241 			RV1108_CLKGATE_CON(8), 10, GFLAGS),
242 	COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0,
243 			RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
244 			RV1108_CLKGATE_CON(8), 1, GFLAGS),
245 
246 	COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
247 			RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
248 			RV1108_CLKGATE_CON(8), 0, GFLAGS),
249 	COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
250 			RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
251 			RV1108_CLKGATE_CON(8), 3, GFLAGS),
252 	GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
253 			RV1108_CLKGATE_CON(19), 0, GFLAGS),
254 	GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
255 			RV1108_CLKGATE_CON(19), 1, GFLAGS),
256 	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
257 			RV1108_CLKGATE_CON(19), 2, GFLAGS),
258 	GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
259 			RV1108_CLKGATE_CON(19), 3, GFLAGS),
260 	GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,
261 			RV1108_CLKGATE_CON(19), 4, GFLAGS),
262 	GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,
263 			RV1108_CLKGATE_CON(19), 5, GFLAGS),
264 	GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
265 			RV1108_CLKGATE_CON(19), 6, GFLAGS),
266 
267 	/* PD_PMU_wrapper */
268 	COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
269 			RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
270 			RV1108_CLKGATE_CON(8), 12, GFLAGS),
271 	GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
272 			RV1108_CLKGATE_CON(10), 0, GFLAGS),
273 	GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
274 			RV1108_CLKGATE_CON(10), 1, GFLAGS),
275 	GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0,
276 			RV1108_CLKGATE_CON(10), 2, GFLAGS),
277 	GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
278 			RV1108_CLKGATE_CON(10), 3, GFLAGS),
279 	GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
280 			RV1108_CLKGATE_CON(10), 4, GFLAGS),
281 	GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0,
282 			RV1108_CLKGATE_CON(10), 5, GFLAGS),
283 	GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0,
284 			RV1108_CLKGATE_CON(10), 6, GFLAGS),
285 	COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0,
286 			RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
287 			RV1108_CLKGATE_CON(8), 15, GFLAGS),
288 	COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0,
289 			RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
290 			RV1108_CLKGATE_CON(8), 14, GFLAGS),
291 	GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
292 			RV1108_CLKGATE_CON(8), 13, GFLAGS),
293 
294 	/*
295 	 * Clock-Architecture Diagram 3
296 	 */
297 	COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0,
298 			RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS,
299 			RV1108_CLKGATE_CON(9), 8, GFLAGS),
300 	COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0,
301 			RV1108_CLKSEL_CON(40), 8, 1, MFLAGS,
302 			RV1108_CLKGATE_CON(9), 11, GFLAGS),
303 	COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0,
304 			RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS),
305 	COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0,
306 			RV1108_CLKSEL_CON(41), 0, 5, DFLAGS,
307 			RV1108_CLKGATE_CON(9), 12, GFLAGS),
308 
309 	GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
310 			RV1108_CLKGATE_CON(14), 6, GFLAGS),
311 	GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
312 			RV1108_CLKGATE_CON(14), 14, GFLAGS),
313 
314 	GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0,
315 			RV1108_CLKGATE_CON(18), 10, GFLAGS),
316 	GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
317 			RV1108_CLKGATE_CON(18), 10, GFLAGS),
318 	COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0,
319 			RV1108_CLKSEL_CON(31), 0, 2, MFLAGS,
320 			RV1108_CLKGATE_CON(7), 9, GFLAGS),
321 	GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0,
322 			RV1108_CLKGATE_CON(17), 6, GFLAGS),
323 	GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0,
324 			RV1108_CLKGATE_CON(17), 7, GFLAGS),
325 	COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0,
326 			RV1108_CLKSEL_CON(31), 2, 2, MFLAGS,
327 			RV1108_CLKGATE_CON(7), 10, GFLAGS),
328 	GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0,
329 			RV1108_CLKGATE_CON(17), 8, GFLAGS),
330 	GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0,
331 			RV1108_CLKGATE_CON(17), 9, GFLAGS),
332 	COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0,
333 			RV1108_CLKSEL_CON(31), 4, 2, MFLAGS,
334 			RV1108_CLKGATE_CON(7), 11, GFLAGS),
335 	GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0,
336 			RV1108_CLKGATE_CON(17), 10, GFLAGS),
337 	GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0,
338 			RV1108_CLKGATE_CON(17), 11, GFLAGS),
339 	COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0,
340 			RV1108_CLKSEL_CON(31), 6, 2, MFLAGS,
341 			RV1108_CLKGATE_CON(7), 12, GFLAGS),
342 	GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED,
343 			RV1108_CLKGATE_CON(7), 8, GFLAGS),
344 
345 	/* PD_DSP_wrapper */
346 	COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0,
347 			RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS,
348 			RV1108_CLKGATE_CON(9), 0, GFLAGS),
349 	GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
350 			RV1108_CLKGATE_CON(16), 0, GFLAGS),
351 	GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
352 			RV1108_CLKGATE_CON(16), 1, GFLAGS),
353 	GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
354 			RV1108_CLKGATE_CON(16), 2, GFLAGS),
355 	GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
356 			RV1108_CLKGATE_CON(16), 3, GFLAGS),
357 	GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED,
358 			RV1108_CLKGATE_CON(16), 13, GFLAGS),
359 	COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0,
360 			RV1108_CLKSEL_CON(44), 0, 5, DFLAGS,
361 			RV1108_CLKGATE_CON(9), 1, GFLAGS),
362 	COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0,
363 			RV1108_CLKSEL_CON(44), 8, 5, DFLAGS,
364 			RV1108_CLKGATE_CON(9), 2, GFLAGS),
365 	COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0,
366 			RV1108_CLKSEL_CON(45), 0, 5, DFLAGS,
367 			RV1108_CLKGATE_CON(9), 3, GFLAGS),
368 	COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0,
369 			RV1108_CLKSEL_CON(45), 8, 5, DFLAGS,
370 			RV1108_CLKGATE_CON(9), 4, GFLAGS),
371 	GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED,
372 			RV1108_CLKGATE_CON(16), 4, GFLAGS),
373 	GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
374 			RV1108_CLKGATE_CON(16), 5, GFLAGS),
375 	GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
376 			RV1108_CLKGATE_CON(16), 6, GFLAGS),
377 	GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED,
378 			RV1108_CLKGATE_CON(16), 7, GFLAGS),
379 	GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED,
380 			RV1108_CLKGATE_CON(16), 14, GFLAGS),
381 	COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0,
382 			RV1108_CLKSEL_CON(43), 0, 5, DFLAGS,
383 			RV1108_CLKGATE_CON(9), 5, GFLAGS),
384 	COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0,
385 			RV1108_CLKSEL_CON(43), 8, 5, DFLAGS,
386 			RV1108_CLKGATE_CON(9), 6, GFLAGS),
387 	GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
388 			RV1108_CLKGATE_CON(16), 8, GFLAGS),
389 	GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
390 			RV1108_CLKGATE_CON(16), 9, GFLAGS),
391 	GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
392 			RV1108_CLKGATE_CON(16), 10, GFLAGS),
393 	GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
394 			RV1108_CLKGATE_CON(16), 11, GFLAGS),
395 	GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
396 			RV1108_CLKGATE_CON(16), 12, GFLAGS),
397 	GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
398 			RV1108_CLKGATE_CON(16), 15, GFLAGS),
399 	GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
400 			RV1108_CLKGATE_CON(11), 8, GFLAGS),
401 
402 	/*
403 	 * Clock-Architecture Diagram 4
404 	 */
405 	COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
406 			RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
407 			RV1108_CLKGATE_CON(6), 0, GFLAGS),
408 	GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0,
409 			RV1108_CLKGATE_CON(17), 0, GFLAGS),
410 	COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
411 			RV1108_CLKSEL_CON(29), 0, 5, DFLAGS,
412 			RV1108_CLKGATE_CON(7), 2, GFLAGS),
413 	GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
414 			RV1108_CLKGATE_CON(17), 2, GFLAGS),
415 	COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
416 			RV1108_CLKSEL_CON(29), 8, 5, DFLAGS,
417 			RV1108_CLKGATE_CON(7), 3, GFLAGS),
418 	GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
419 			RV1108_CLKGATE_CON(17), 3, GFLAGS),
420 	COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
421 			RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
422 			RV1108_CLKGATE_CON(6), 1, GFLAGS),
423 	GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0,
424 			RV1108_CLKGATE_CON(17), 1, GFLAGS),
425 
426 	INVERTER(0, "pclk_vip", "ext_vip",
427 			RV1108_CLKSEL_CON(31), 8, IFLAGS),
428 	GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED,
429 			RV1108_CLKGATE_CON(7), 6, GFLAGS),
430 	GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED,
431 			RV1108_CLKGATE_CON(18), 10, GFLAGS),
432 	GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED,
433 			RV1108_CLKGATE_CON(6), 5, GFLAGS),
434 	GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
435 			RV1108_CLKGATE_CON(6), 4, GFLAGS),
436 	COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0,
437 			RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS),
438 	COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0,
439 			RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS),
440 	MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT,
441 			RV1108_CLKSEL_CON(32), 15, 1, MFLAGS),
442 	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
443 			RV1108_CLKSEL_CON(32), 7, 1, MFLAGS),
444 	GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0,
445 			RV1108_CLKGATE_CON(18), 0, GFLAGS),
446 	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
447 			RV1108_CLKGATE_CON(18), 1, GFLAGS),
448 	GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0,
449 			RV1108_CLKGATE_CON(18), 2, GFLAGS),
450 	GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
451 			RV1108_CLKGATE_CON(18), 3, GFLAGS),
452 
453 	GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0,
454 			RV1108_CLKGATE_CON(18), 4, GFLAGS),
455 	GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
456 			RV1108_CLKGATE_CON(18), 5, GFLAGS),
457 	COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0,
458 			RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS,
459 			RV1108_CLKGATE_CON(6), 6, GFLAGS),
460 
461 	COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0,
462 			RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS,
463 			RV1108_CLKGATE_CON(6), 7, GFLAGS),
464 	FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2),
465 
466 	GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0,
467 			RV1108_CLKGATE_CON(6), 8, GFLAGS),
468 
469 	COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0,
470 			RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS,
471 			RV1108_CLKGATE_CON(6), 9, GFLAGS),
472 	GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0,
473 			RV1108_CLKGATE_CON(18), 8, GFLAGS),
474 	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0,
475 			RV1108_CLKGATE_CON(18), 9, GFLAGS),
476 
477 	GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0,
478 			RV1108_CLKGATE_CON(18), 12, GFLAGS),
479 	GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
480 			RV1108_CLKGATE_CON(18), 11, GFLAGS),
481 	COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0,
482 			RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
483 			RV1108_CLKGATE_CON(6), 3, GFLAGS),
484 
485 	GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED,
486 			RV1108_CLKGATE_CON(9), 10, GFLAGS),
487 	GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
488 			RV1108_CLKGATE_CON(14), 9, GFLAGS),
489 	GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
490 			RV1108_CLKGATE_CON(14), 11, GFLAGS),
491 	GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
492 			RV1108_CLKGATE_CON(14), 12, GFLAGS),
493 
494 	/*
495 	 * Clock-Architecture Diagram 5
496 	 */
497 
498 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
499 
500 
501 	COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0,
502 			RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
503 			RV1108_CLKGATE_CON(2), 0, GFLAGS),
504 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
505 			RV1108_CLKSEL_CON(8), 0,
506 			RV1108_CLKGATE_CON(2), 1, GFLAGS,
507 			&rv1108_i2s0_fracmux),
508 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
509 			RV1108_CLKGATE_CON(2), 2, GFLAGS),
510 	COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
511 			RV1108_CLKSEL_CON(5), 15, 1, MFLAGS,
512 			RV1108_CLKGATE_CON(2), 3, GFLAGS),
513 
514 	COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0,
515 			RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
516 			RV1108_CLKGATE_CON(2), 4, GFLAGS),
517 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
518 			RK2928_CLKSEL_CON(9), 0,
519 			RK2928_CLKGATE_CON(2), 5, GFLAGS,
520 			&rv1108_i2s1_fracmux),
521 	GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
522 			RV1108_CLKGATE_CON(2), 6, GFLAGS),
523 
524 	COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0,
525 			RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
526 			RV1108_CLKGATE_CON(3), 8, GFLAGS),
527 	COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
528 			RV1108_CLKSEL_CON(10), 0,
529 			RV1108_CLKGATE_CON(2), 9, GFLAGS,
530 			&rv1108_i2s2_fracmux),
531 	GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
532 			RV1108_CLKGATE_CON(2), 10, GFLAGS),
533 
534 	/* PD_BUS */
535 	GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
536 			RV1108_CLKGATE_CON(1), 0, GFLAGS),
537 	GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
538 			RV1108_CLKGATE_CON(1), 1, GFLAGS),
539 	GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
540 			RV1108_CLKGATE_CON(1), 2, GFLAGS),
541 	COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
542 			RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
543 	COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0,
544 			RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
545 			RV1108_CLKGATE_CON(1), 4, GFLAGS),
546 	COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0,
547 			RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
548 			RV1108_CLKGATE_CON(1), 5, GFLAGS),
549 	GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
550 			RV1108_CLKGATE_CON(1), 6, GFLAGS),
551 	GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
552 			RV1108_CLKGATE_CON(1), 7, GFLAGS),
553 	GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
554 			RV1108_CLKGATE_CON(1), 8, GFLAGS),
555 	GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
556 			RV1108_CLKGATE_CON(1), 9, GFLAGS),
557 	GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED,
558 			RV1108_CLKGATE_CON(1), 10, GFLAGS),
559 	GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
560 			RV1108_CLKGATE_CON(13), 4, GFLAGS),
561 
562 	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0,
563 			RV1108_CLKGATE_CON(12), 7, GFLAGS),
564 	GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0,
565 			RV1108_CLKGATE_CON(12), 8, GFLAGS),
566 	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0,
567 			RV1108_CLKGATE_CON(12), 9, GFLAGS),
568 
569 	GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0,
570 			RV1108_CLKGATE_CON(12), 10, GFLAGS),
571 	GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0,
572 			RV1108_CLKGATE_CON(12), 11, GFLAGS),
573 	COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
574 			RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS,
575 			RV1108_CLKGATE_CON(2), 12, GFLAGS),
576 
577 	COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0,
578 			RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS,
579 			RV1108_CLKGATE_CON(3), 0, GFLAGS),
580 	GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0,
581 			RV1108_CLKGATE_CON(13), 5, GFLAGS),
582 
583 	COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
584 			RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
585 			RV1108_CLKGATE_CON(3), 1, GFLAGS),
586 	COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
587 			RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
588 			RV1108_CLKGATE_CON(3), 3, GFLAGS),
589 	COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
590 			RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
591 			RV1108_CLKGATE_CON(3), 5, GFLAGS),
592 
593 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
594 			RV1108_CLKSEL_CON(16), 0,
595 			RV1108_CLKGATE_CON(3), 2, GFLAGS,
596 			&rv1108_uart0_fracmux),
597 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
598 			RV1108_CLKSEL_CON(17), 0,
599 			RV1108_CLKGATE_CON(3), 4, GFLAGS,
600 			&rv1108_uart1_fracmux),
601 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
602 			RV1108_CLKSEL_CON(18), 0,
603 			RV1108_CLKGATE_CON(3), 6, GFLAGS,
604 			&rv1108_uart2_fracmux),
605 	GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
606 			RV1108_CLKGATE_CON(13), 10, GFLAGS),
607 	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
608 			RV1108_CLKGATE_CON(13), 11, GFLAGS),
609 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
610 			RV1108_CLKGATE_CON(13), 12, GFLAGS),
611 
612 	COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0,
613 			RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS,
614 			RV1108_CLKGATE_CON(3), 7, GFLAGS),
615 	COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0,
616 			RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
617 			RV1108_CLKGATE_CON(3), 8, GFLAGS),
618 	COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0,
619 			RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS,
620 			RV1108_CLKGATE_CON(3), 9, GFLAGS),
621 	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0,
622 			RV1108_CLKGATE_CON(13), 0, GFLAGS),
623 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0,
624 			RV1108_CLKGATE_CON(13), 1, GFLAGS),
625 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0,
626 			RV1108_CLKGATE_CON(13), 2, GFLAGS),
627 	COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0,
628 			RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
629 			RV1108_CLKGATE_CON(3), 10, GFLAGS),
630 	GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0,
631 			RV1108_CLKGATE_CON(13), 6, GFLAGS),
632 	GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
633 			RV1108_CLKGATE_CON(13), 3, GFLAGS),
634 	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0,
635 			RV1108_CLKGATE_CON(13), 7, GFLAGS),
636 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0,
637 			RV1108_CLKGATE_CON(13), 8, GFLAGS),
638 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0,
639 			RV1108_CLKGATE_CON(13), 9, GFLAGS),
640 
641 	GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
642 			RV1108_CLKGATE_CON(14), 0, GFLAGS),
643 	GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0,
644 			RV1108_CLKGATE_CON(12), 12, GFLAGS),
645 	GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0,
646 			RV1108_CLKGATE_CON(12), 13, GFLAGS),
647 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0,
648 			RV1108_CLKGATE_CON(13), 13, GFLAGS),
649 	COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
650 			RV1108_CLKSEL_CON(21), 0, 10, DFLAGS,
651 			RV1108_CLKGATE_CON(3), 11, GFLAGS),
652 	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0,
653 			RV1108_CLKGATE_CON(13), 14, GFLAGS),
654 	COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
655 			RV1108_CLKSEL_CON(22), 0, 10, DFLAGS,
656 			RV1108_CLKGATE_CON(3), 12, GFLAGS),
657 
658 	GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
659 	     RV1108_CLKGATE_CON(12), 2, GFLAGS),
660 	GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED,
661 			RV1108_CLKGATE_CON(12), 3, GFLAGS),
662 	GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED,
663 			RV1108_CLKGATE_CON(12), 1, GFLAGS),
664 
665 	/* PD_DDR */
666 	GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
667 			RV1108_CLKGATE_CON(0), 8, GFLAGS),
668 	GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
669 			RV1108_CLKGATE_CON(0), 9, GFLAGS),
670 	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
671 			RV1108_CLKGATE_CON(0), 10, GFLAGS),
672 	COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
673 			RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
674 			DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
675 	FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2),
676 	GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED,
677 			RV1108_CLKGATE_CON(10), 9, GFLAGS),
678 	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
679 			RV1108_CLKGATE_CON(12), 4, GFLAGS),
680 	GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
681 			RV1108_CLKGATE_CON(12), 5, GFLAGS),
682 	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
683 			RV1108_CLKGATE_CON(12), 6, GFLAGS),
684 	GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
685 			RV1108_CLKGATE_CON(0), 11, GFLAGS),
686 	GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
687 			RV1108_CLKGATE_CON(14), 2, GFLAGS),
688 	GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
689 			RV1108_CLKGATE_CON(14), 4, GFLAGS),
690 
691 	/*
692 	 * Clock-Architecture Diagram 6
693 	 */
694 
695 	/* PD_PERI */
696 	COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
697 			RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
698 			RV1108_CLKGATE_CON(4), 5, GFLAGS),
699 	GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
700 			RV1108_CLKGATE_CON(15), 13, GFLAGS),
701 	COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
702 			RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
703 			RV1108_CLKGATE_CON(4), 4, GFLAGS),
704 	GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
705 			RV1108_CLKGATE_CON(15), 12, GFLAGS),
706 
707 	GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
708 			RV1108_CLKGATE_CON(4), 1, GFLAGS),
709 	GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
710 			RV1108_CLKGATE_CON(4), 2, GFLAGS),
711 	COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0,
712 			RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS,
713 			RV1108_CLKGATE_CON(15), 11, GFLAGS),
714 
715 	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
716 			RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
717 			RV1108_CLKGATE_CON(5), 0, GFLAGS),
718 
719 	COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
720 			RV1108_CLKSEL_CON(25), 10, 2, MFLAGS,
721 			RV1108_CLKGATE_CON(5), 2, GFLAGS),
722 	DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
723 			RV1108_CLKSEL_CON(26), 0, 8, DFLAGS),
724 
725 	COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
726 			RV1108_CLKSEL_CON(25), 12, 2, MFLAGS,
727 			RV1108_CLKGATE_CON(5), 1, GFLAGS),
728 	DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
729 			RK2928_CLKSEL_CON(26), 8, 8, DFLAGS),
730 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS),
731 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS),
732 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
733 
734 	COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
735 			RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS,
736 			RV1108_CLKGATE_CON(5), 3, GFLAGS),
737 	GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
738 
739 	GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS),
740 	GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS),
741 	GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS),
742 	GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS),
743 	GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS),
744 
745 	COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
746 			RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
747 			RV1108_CLKGATE_CON(5), 4, GFLAGS),
748 	GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
749 
750 	COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0,
751 			RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS,
752 			RV1108_CLKGATE_CON(4), 10, GFLAGS),
753 	MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT,
754 			RV1108_CLKSEL_CON(24), 8, 1, MFLAGS),
755 	GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
756 	GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
757 	GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
758 	GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
759 	GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),
760 
761 	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
762 	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
763 
764 	MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RV1108_SDIO_CON0,  1),
765 	MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RV1108_SDIO_CON1,  1),
766 
767 	MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RV1108_EMMC_CON0,  1),
768 	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RV1108_EMMC_CON1,  1),
769 };
770 
771 static const char *const rv1108_critical_clocks[] __initconst = {
772 	"aclk_core",
773 	"aclk_bus",
774 	"hclk_bus",
775 	"pclk_bus",
776 	"aclk_periph",
777 	"hclk_periph",
778 	"pclk_periph",
779 	"nclk_ddrupctl",
780 	"pclk_ddrmon",
781 	"pclk_acodecphy",
782 	"pclk_pmu",
783 };
784 
785 static void __init rv1108_clk_init(struct device_node *np)
786 {
787 	struct rockchip_clk_provider *ctx;
788 	void __iomem *reg_base;
789 
790 	reg_base = of_iomap(np, 0);
791 	if (!reg_base) {
792 		pr_err("%s: could not map cru region\n", __func__);
793 		return;
794 	}
795 
796 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
797 	if (IS_ERR(ctx)) {
798 		pr_err("%s: rockchip clk init failed\n", __func__);
799 		iounmap(reg_base);
800 		return;
801 	}
802 
803 	rockchip_clk_register_plls(ctx, rv1108_pll_clks,
804 				   ARRAY_SIZE(rv1108_pll_clks),
805 				   RV1108_GRF_SOC_STATUS0);
806 	rockchip_clk_register_branches(ctx, rv1108_clk_branches,
807 				  ARRAY_SIZE(rv1108_clk_branches));
808 	rockchip_clk_protect_critical(rv1108_critical_clocks,
809 				      ARRAY_SIZE(rv1108_critical_clocks));
810 
811 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
812 			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
813 			&rv1108_cpuclk_data, rv1108_cpuclk_rates,
814 			ARRAY_SIZE(rv1108_cpuclk_rates));
815 
816 	rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0),
817 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
818 
819 	rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL);
820 
821 	rockchip_clk_of_add_provider(np, ctx);
822 }
823 CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init);
824