1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Shawn Lin <shawn.lin@rock-chips.com> 4 * Andy Yan <andy.yan@rock-chips.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk-provider.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/syscore_ops.h> 21 #include <dt-bindings/clock/rv1108-cru.h> 22 #include "clk.h" 23 24 #define RV1108_GRF_SOC_STATUS0 0x480 25 26 enum rv1108_plls { 27 apll, dpll, gpll, 28 }; 29 30 static struct rockchip_pll_rate_table rv1108_pll_rates[] = { 31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 49 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 52 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 53 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 54 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 55 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 56 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 57 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 58 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 59 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 60 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 61 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 62 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 63 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 64 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 65 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 66 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 67 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 68 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 69 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 70 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 71 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 72 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 73 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 74 { /* sentinel */ }, 75 }; 76 77 #define RV1108_DIV_CORE_MASK 0xf 78 #define RV1108_DIV_CORE_SHIFT 4 79 80 #define RV1108_CLKSEL0(_core_peri_div) \ 81 { \ 82 .reg = RV1108_CLKSEL_CON(1), \ 83 .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\ 84 RV1108_DIV_CORE_SHIFT) \ 85 } 86 87 #define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \ 88 { \ 89 .prate = _prate, \ 90 .divs = { \ 91 RV1108_CLKSEL0(_core_peri_div), \ 92 }, \ 93 } 94 95 static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = { 96 RV1108_CPUCLK_RATE(816000000, 4), 97 RV1108_CPUCLK_RATE(600000000, 4), 98 RV1108_CPUCLK_RATE(312000000, 4), 99 }; 100 101 static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { 102 .core_reg = RV1108_CLKSEL_CON(0), 103 .div_core_shift = 0, 104 .div_core_mask = 0x1f, 105 .mux_core_alt = 1, 106 .mux_core_main = 0, 107 .mux_core_shift = 8, 108 .mux_core_mask = 0x1, 109 }; 110 111 PNAME(mux_pll_p) = { "xin24m", "xin24m"}; 112 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; 113 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; 114 PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" }; 115 PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" }; 116 PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" }; 117 PNAME(mux_pll_src_4plls_p) = { "dpll", "hdmiphy", "gpll", "usb480m" }; 118 PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" }; 119 PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" }; 120 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" }; 121 PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_dpll", "aclk_peri_src_gpll" }; 122 PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" }; 123 PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" }; 124 PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" }; 125 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 126 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 127 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 128 PNAME(mux_sclk_macphy_p) = { "sclk_macphy_pre", "ext_gmac" }; 129 PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; 130 PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" }; 131 PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "xin12m" }; 132 PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; 133 134 static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = { 135 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), 136 RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates), 137 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), 138 RV1108_PLL_CON(11), 8, 31, 0, NULL), 139 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), 140 RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates), 141 }; 142 143 #define MFLAGS CLK_MUX_HIWORD_MASK 144 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 145 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 146 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 147 148 static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata = 149 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 150 RV1108_CLKSEL_CON(13), 8, 2, MFLAGS); 151 152 static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata = 153 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 154 RV1108_CLKSEL_CON(14), 8, 2, MFLAGS); 155 156 static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata = 157 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 158 RV1108_CLKSEL_CON(15), 8, 2, MFLAGS); 159 160 static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata = 161 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, 162 RV1108_CLKSEL_CON(5), 12, 2, MFLAGS); 163 164 static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata = 165 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, 166 RV1108_CLKSEL_CON(6), 12, 2, MFLAGS); 167 168 static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata = 169 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, 170 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS); 171 172 static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { 173 MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, 174 RV1108_MISC_CON, 13, 2, MFLAGS), 175 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, 176 RV1108_MISC_CON, 15, 2, MFLAGS), 177 /* 178 * Clock-Architecture Diagram 2 179 */ 180 181 /* PD_CORE */ 182 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, 183 RV1108_CLKGATE_CON(0), 1, GFLAGS), 184 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 185 RV1108_CLKGATE_CON(0), 0, GFLAGS), 186 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 187 RV1108_CLKGATE_CON(0), 2, GFLAGS), 188 COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED, 189 RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 190 RV1108_CLKGATE_CON(0), 5, GFLAGS), 191 COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED, 192 RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 193 RV1108_CLKGATE_CON(0), 4, GFLAGS), 194 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED, 195 RV1108_CLKGATE_CON(11), 0, GFLAGS), 196 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED, 197 RV1108_CLKGATE_CON(11), 1, GFLAGS), 198 199 /* PD_RKVENC */ 200 201 /* PD_RKVDEC */ 202 203 /* PD_PMU_wrapper */ 204 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED, 205 RV1108_CLKSEL_CON(38), 0, 5, DFLAGS, 206 RV1108_CLKGATE_CON(8), 12, GFLAGS), 207 GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 208 RV1108_CLKGATE_CON(10), 0, GFLAGS), 209 GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, 210 RV1108_CLKGATE_CON(10), 1, GFLAGS), 211 GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 212 RV1108_CLKGATE_CON(10), 2, GFLAGS), 213 GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, 214 RV1108_CLKGATE_CON(10), 3, GFLAGS), 215 GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED, 216 RV1108_CLKGATE_CON(10), 4, GFLAGS), 217 GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, 218 RV1108_CLKGATE_CON(10), 5, GFLAGS), 219 GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, 220 RV1108_CLKGATE_CON(10), 6, GFLAGS), 221 COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 222 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, 223 RV1108_CLKGATE_CON(8), 15, GFLAGS), 224 COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 225 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, 226 RV1108_CLKGATE_CON(8), 14, GFLAGS), 227 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, 228 RV1108_CLKGATE_CON(8), 13, GFLAGS), 229 230 /* 231 * Clock-Architecture Diagram 4 232 */ 233 COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 234 RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 235 RV1108_CLKGATE_CON(6), 0, GFLAGS), 236 GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED, 237 RV1108_CLKGATE_CON(17), 0, GFLAGS), 238 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0, 239 RV1108_CLKSEL_CON(29), 0, 5, DFLAGS, 240 RV1108_CLKGATE_CON(7), 2, GFLAGS), 241 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0, 242 RV1108_CLKSEL_CON(29), 8, 5, DFLAGS, 243 RV1108_CLKGATE_CON(7), 3, GFLAGS), 244 245 INVERTER(0, "pclk_vip", "ext_vip", 246 RV1108_CLKSEL_CON(31), 8, IFLAGS), 247 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED, 248 RV1108_CLKGATE_CON(7), 6, GFLAGS), 249 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED, 250 RV1108_CLKGATE_CON(18), 10, GFLAGS), 251 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED, 252 RV1108_CLKGATE_CON(6), 5, GFLAGS), 253 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED, 254 RV1108_CLKGATE_CON(6), 4, GFLAGS), 255 COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0, 256 RV1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS), 257 258 /* 259 * Clock-Architecture Diagram 5 260 */ 261 262 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 263 264 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, 265 RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, 266 RV1108_CLKGATE_CON(2), 0, GFLAGS), 267 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 268 RV1108_CLKSEL_CON(8), 0, 269 RV1108_CLKGATE_CON(2), 1, GFLAGS, 270 &rv1108_i2s0_fracmux), 271 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, 272 RV1108_CLKGATE_CON(2), 2, GFLAGS), 273 COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0, 274 RV1108_CLKSEL_CON(5), 15, 1, MFLAGS, 275 RV1108_CLKGATE_CON(2), 3, GFLAGS), 276 277 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, 278 RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, 279 RV1108_CLKGATE_CON(2), 4, GFLAGS), 280 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 281 RK2928_CLKSEL_CON(9), 0, 282 RK2928_CLKGATE_CON(2), 5, GFLAGS, 283 &rv1108_i2s1_fracmux), 284 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 285 RV1108_CLKGATE_CON(2), 6, GFLAGS), 286 287 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, 288 RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, 289 RV1108_CLKGATE_CON(3), 8, GFLAGS), 290 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, 291 RV1108_CLKSEL_CON(10), 0, 292 RV1108_CLKGATE_CON(2), 9, GFLAGS, 293 &rv1108_i2s2_fracmux), 294 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, 295 RV1108_CLKGATE_CON(2), 10, GFLAGS), 296 297 /* PD_BUS */ 298 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED, 299 RV1108_CLKGATE_CON(1), 0, GFLAGS), 300 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED, 301 RV1108_CLKGATE_CON(1), 1, GFLAGS), 302 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED, 303 RV1108_CLKGATE_CON(1), 2, GFLAGS), 304 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0, 305 RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), 306 COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0, 307 RV1108_CLKSEL_CON(3), 0, 5, DFLAGS, 308 RV1108_CLKGATE_CON(1), 4, GFLAGS), 309 COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0, 310 RV1108_CLKSEL_CON(3), 8, 5, DFLAGS, 311 RV1108_CLKGATE_CON(1), 5, GFLAGS), 312 GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED, 313 RV1108_CLKGATE_CON(1), 6, GFLAGS), 314 GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED, 315 RV1108_CLKGATE_CON(1), 7, GFLAGS), 316 GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED, 317 RV1108_CLKGATE_CON(1), 8, GFLAGS), 318 GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED, 319 RV1108_CLKGATE_CON(1), 9, GFLAGS), 320 GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED, 321 RV1108_CLKGATE_CON(1), 10, GFLAGS), 322 GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, 323 RV1108_CLKGATE_CON(13), 4, GFLAGS), 324 325 COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 326 RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 327 RV1108_CLKGATE_CON(3), 1, GFLAGS), 328 COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 329 RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 330 RV1108_CLKGATE_CON(3), 3, GFLAGS), 331 COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 332 RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, 333 RV1108_CLKGATE_CON(3), 5, GFLAGS), 334 335 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 336 RV1108_CLKSEL_CON(16), 0, 337 RV1108_CLKGATE_CON(3), 2, GFLAGS, 338 &rv1108_uart0_fracmux), 339 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 340 RV1108_CLKSEL_CON(17), 0, 341 RV1108_CLKGATE_CON(3), 4, GFLAGS, 342 &rv1108_uart1_fracmux), 343 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 344 RV1108_CLKSEL_CON(18), 0, 345 RV1108_CLKGATE_CON(3), 6, GFLAGS, 346 &rv1108_uart2_fracmux), 347 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED, 348 RV1108_CLKGATE_CON(13), 10, GFLAGS), 349 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 350 RV1108_CLKGATE_CON(13), 11, GFLAGS), 351 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 352 RV1108_CLKGATE_CON(13), 12, GFLAGS), 353 354 COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 355 RV1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS, 356 RV1108_CLKGATE_CON(3), 7, GFLAGS), 357 COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 358 RV1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS, 359 RV1108_CLKGATE_CON(3), 8, GFLAGS), 360 COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 361 RV1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS, 362 RV1108_CLKGATE_CON(3), 9, GFLAGS), 363 GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 364 RV1108_CLKGATE_CON(13), 0, GFLAGS), 365 GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 366 RV1108_CLKGATE_CON(13), 1, GFLAGS), 367 GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED, 368 RV1108_CLKGATE_CON(13), 2, GFLAGS), 369 COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 370 RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, 371 RV1108_CLKGATE_CON(3), 10, GFLAGS), 372 GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 373 RV1108_CLKGATE_CON(13), 6, GFLAGS), 374 GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED, 375 RV1108_CLKGATE_CON(13), 3, GFLAGS), 376 GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 377 RV1108_CLKGATE_CON(13), 7, GFLAGS), 378 GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 379 RV1108_CLKGATE_CON(13), 8, GFLAGS), 380 GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED, 381 RV1108_CLKGATE_CON(13), 9, GFLAGS), 382 383 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, 384 RV1108_CLKGATE_CON(14), 0, GFLAGS), 385 386 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0, 387 RV1108_CLKGATE_CON(12), 2, GFLAGS), 388 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, 389 RV1108_CLKGATE_CON(12), 3, GFLAGS), 390 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, 391 RV1108_CLKGATE_CON(12), 1, GFLAGS), 392 393 /* PD_DDR */ 394 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, 395 RV1108_CLKGATE_CON(0), 8, GFLAGS), 396 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 397 RV1108_CLKGATE_CON(0), 9, GFLAGS), 398 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 399 RV1108_CLKGATE_CON(0), 10, GFLAGS), 400 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 401 RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, 402 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 403 RV1108_CLKGATE_CON(10), 9, GFLAGS), 404 GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED, 405 RV1108_CLKGATE_CON(12), 4, GFLAGS), 406 GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED, 407 RV1108_CLKGATE_CON(12), 5, GFLAGS), 408 GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED, 409 RV1108_CLKGATE_CON(12), 6, GFLAGS), 410 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED, 411 RV1108_CLKGATE_CON(0), 11, GFLAGS), 412 413 /* 414 * Clock-Architecture Diagram 6 415 */ 416 417 /* PD_PERI */ 418 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0, 419 RV1108_CLKSEL_CON(23), 10, 5, DFLAGS, 420 RV1108_CLKGATE_CON(4), 5, GFLAGS), 421 GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, 422 RV1108_CLKGATE_CON(15), 13, GFLAGS), 423 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0, 424 RV1108_CLKSEL_CON(23), 5, 5, DFLAGS, 425 RV1108_CLKGATE_CON(4), 4, GFLAGS), 426 GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, 427 RV1108_CLKGATE_CON(15), 12, GFLAGS), 428 429 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED, 430 RV1108_CLKGATE_CON(4), 1, GFLAGS), 431 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED, 432 RV1108_CLKGATE_CON(4), 2, GFLAGS), 433 COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED, 434 RV1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS, 435 RV1108_CLKGATE_CON(15), 11, GFLAGS), 436 437 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, 438 RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, 439 RV1108_CLKGATE_CON(5), 0, GFLAGS), 440 441 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 442 RV1108_CLKSEL_CON(25), 10, 2, MFLAGS, 443 RV1108_CLKGATE_CON(5), 2, GFLAGS), 444 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 445 RV1108_CLKSEL_CON(26), 0, 8, DFLAGS), 446 447 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, 448 RV1108_CLKSEL_CON(25), 12, 2, MFLAGS, 449 RV1108_CLKGATE_CON(5), 1, GFLAGS), 450 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, 451 RK2928_CLKSEL_CON(26), 8, 8, DFLAGS), 452 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS), 453 GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS), 454 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS), 455 456 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, 457 RV1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS, 458 RV1108_CLKGATE_CON(5), 3, GFLAGS), 459 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS), 460 461 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0, 462 RV1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS, 463 RV1108_CLKGATE_CON(5), 4, GFLAGS), 464 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS), 465 466 COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0, 467 RV1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS, 468 RV1108_CLKGATE_CON(4), 10, GFLAGS), 469 MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT, 470 RV1108_CLKSEL_CON(24), 8, 2, MFLAGS), 471 GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS), 472 GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS), 473 GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS), 474 475 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1), 476 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1), 477 478 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1), 479 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1), 480 481 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1), 482 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1), 483 }; 484 485 static const char *const rv1108_critical_clocks[] __initconst = { 486 "aclk_core", 487 "aclk_bus_src_gpll", 488 "aclk_periph", 489 "hclk_periph", 490 "pclk_periph", 491 }; 492 493 static void __init rv1108_clk_init(struct device_node *np) 494 { 495 struct rockchip_clk_provider *ctx; 496 void __iomem *reg_base; 497 498 reg_base = of_iomap(np, 0); 499 if (!reg_base) { 500 pr_err("%s: could not map cru region\n", __func__); 501 return; 502 } 503 504 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 505 if (IS_ERR(ctx)) { 506 pr_err("%s: rockchip clk init failed\n", __func__); 507 iounmap(reg_base); 508 return; 509 } 510 511 rockchip_clk_register_plls(ctx, rv1108_pll_clks, 512 ARRAY_SIZE(rv1108_pll_clks), 513 RV1108_GRF_SOC_STATUS0); 514 rockchip_clk_register_branches(ctx, rv1108_clk_branches, 515 ARRAY_SIZE(rv1108_clk_branches)); 516 rockchip_clk_protect_critical(rv1108_critical_clocks, 517 ARRAY_SIZE(rv1108_critical_clocks)); 518 519 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 520 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 521 &rv1108_cpuclk_data, rv1108_cpuclk_rates, 522 ARRAY_SIZE(rv1108_cpuclk_rates)); 523 524 rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0), 525 ROCKCHIP_SOFTRST_HIWORD_MASK); 526 527 rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL); 528 529 rockchip_clk_of_add_provider(np, ctx); 530 } 531 CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init); 532