1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Shawn Lin <shawn.lin@rock-chips.com> 4 * Andy Yan <andy.yan@rock-chips.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk-provider.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/syscore_ops.h> 21 #include <dt-bindings/clock/rv1108-cru.h> 22 #include "clk.h" 23 24 #define RV1108_GRF_SOC_STATUS0 0x480 25 26 enum rv1108_plls { 27 apll, dpll, gpll, 28 }; 29 30 static struct rockchip_pll_rate_table rv1108_pll_rates[] = { 31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 49 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 52 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 53 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 54 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 55 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 56 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 57 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 58 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 59 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 60 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 61 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 62 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 63 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 64 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 65 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 66 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 67 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 68 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 69 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 70 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 71 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 72 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 73 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 74 { /* sentinel */ }, 75 }; 76 77 #define RV1108_DIV_CORE_MASK 0xf 78 #define RV1108_DIV_CORE_SHIFT 4 79 80 #define RV1108_CLKSEL0(_core_peri_div) \ 81 { \ 82 .reg = RV1108_CLKSEL_CON(1), \ 83 .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\ 84 RV1108_DIV_CORE_SHIFT) \ 85 } 86 87 #define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \ 88 { \ 89 .prate = _prate, \ 90 .divs = { \ 91 RV1108_CLKSEL0(_core_peri_div), \ 92 }, \ 93 } 94 95 static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = { 96 RV1108_CPUCLK_RATE(1608000000, 7), 97 RV1108_CPUCLK_RATE(1512000000, 7), 98 RV1108_CPUCLK_RATE(1488000000, 5), 99 RV1108_CPUCLK_RATE(1416000000, 5), 100 RV1108_CPUCLK_RATE(1392000000, 5), 101 RV1108_CPUCLK_RATE(1296000000, 5), 102 RV1108_CPUCLK_RATE(1200000000, 5), 103 RV1108_CPUCLK_RATE(1104000000, 5), 104 RV1108_CPUCLK_RATE(1008000000, 5), 105 RV1108_CPUCLK_RATE(912000000, 5), 106 RV1108_CPUCLK_RATE(816000000, 3), 107 RV1108_CPUCLK_RATE(696000000, 3), 108 RV1108_CPUCLK_RATE(600000000, 3), 109 RV1108_CPUCLK_RATE(500000000, 3), 110 RV1108_CPUCLK_RATE(408000000, 1), 111 RV1108_CPUCLK_RATE(312000000, 1), 112 RV1108_CPUCLK_RATE(216000000, 1), 113 RV1108_CPUCLK_RATE(96000000, 1), 114 }; 115 116 static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { 117 .core_reg = RV1108_CLKSEL_CON(0), 118 .div_core_shift = 0, 119 .div_core_mask = 0x1f, 120 .mux_core_alt = 1, 121 .mux_core_main = 0, 122 .mux_core_shift = 8, 123 .mux_core_mask = 0x3, 124 }; 125 126 PNAME(mux_pll_p) = { "xin24m", "xin24m"}; 127 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; 128 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; 129 PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" }; 130 PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" }; 131 PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" }; 132 PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" }; 133 PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" }; 134 PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" }; 135 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" }; 136 PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" }; 137 PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" }; 138 PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" }; 139 PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" }; 140 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 141 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 142 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 143 PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" }; 144 PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; 145 PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" }; 146 PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" }; 147 PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" }; 148 PNAME(mux_wifi_src_p) = { "gpll", "xin24m" }; 149 PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" }; 150 PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" }; 151 PNAME(mux_sclk_cif0_src_p) = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" }; 152 PNAME(mux_sclk_cif1_src_p) = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" }; 153 PNAME(mux_sclk_cif2_src_p) = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" }; 154 PNAME(mux_sclk_cif3_src_p) = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" }; 155 PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" }; 156 PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" }; 157 PNAME(mux_dclk_vop_p) = { "dclk_hdmiphy", "dclk_vop_src" }; 158 PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" }; 159 PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" }; 160 161 static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = { 162 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), 163 RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates), 164 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), 165 RV1108_PLL_CON(11), 8, 1, 0, NULL), 166 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), 167 RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates), 168 }; 169 170 #define MFLAGS CLK_MUX_HIWORD_MASK 171 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 172 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 173 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 174 175 static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata = 176 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 177 RV1108_CLKSEL_CON(13), 8, 2, MFLAGS); 178 179 static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata = 180 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 181 RV1108_CLKSEL_CON(14), 8, 2, MFLAGS); 182 183 static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata = 184 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 185 RV1108_CLKSEL_CON(15), 8, 2, MFLAGS); 186 187 static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata = 188 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, 189 RV1108_CLKSEL_CON(5), 12, 2, MFLAGS); 190 191 static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata = 192 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, 193 RV1108_CLKSEL_CON(6), 12, 2, MFLAGS); 194 195 static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata = 196 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, 197 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS); 198 199 static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { 200 MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, 201 RV1108_MISC_CON, 13, 1, MFLAGS), 202 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, 203 RV1108_MISC_CON, 15, 1, MFLAGS), 204 /* 205 * Clock-Architecture Diagram 2 206 */ 207 208 /* PD_CORE */ 209 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, 210 RV1108_CLKGATE_CON(0), 1, GFLAGS), 211 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 212 RV1108_CLKGATE_CON(0), 0, GFLAGS), 213 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 214 RV1108_CLKGATE_CON(0), 2, GFLAGS), 215 COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED, 216 RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 217 RV1108_CLKGATE_CON(0), 5, GFLAGS), 218 COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED, 219 RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 220 RV1108_CLKGATE_CON(0), 4, GFLAGS), 221 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED, 222 RV1108_CLKGATE_CON(11), 0, GFLAGS), 223 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED, 224 RV1108_CLKGATE_CON(11), 1, GFLAGS), 225 226 /* PD_RKVENC */ 227 COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0, 228 RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS, 229 RV1108_CLKGATE_CON(8), 8, GFLAGS), 230 FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4, 231 RV1108_CLKGATE_CON(8), 10, GFLAGS), 232 COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0, 233 RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS, 234 RV1108_CLKGATE_CON(8), 9, GFLAGS), 235 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, 236 RV1108_CLKGATE_CON(19), 8, GFLAGS), 237 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, 238 RV1108_CLKGATE_CON(19), 9, GFLAGS), 239 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED, 240 RV1108_CLKGATE_CON(19), 11, GFLAGS), 241 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED, 242 RV1108_CLKGATE_CON(19), 10, GFLAGS), 243 244 /* PD_RKVDEC */ 245 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0, 246 RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS, 247 RV1108_CLKGATE_CON(8), 2, GFLAGS), 248 FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4, 249 RV1108_CLKGATE_CON(8), 10, GFLAGS), 250 COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0, 251 RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS, 252 RV1108_CLKGATE_CON(8), 1, GFLAGS), 253 254 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, 255 RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 256 RV1108_CLKGATE_CON(8), 0, GFLAGS), 257 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, 258 RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS, 259 RV1108_CLKGATE_CON(8), 3, GFLAGS), 260 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, 261 RV1108_CLKGATE_CON(19), 0, GFLAGS), 262 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, 263 RV1108_CLKGATE_CON(19), 1, GFLAGS), 264 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, 265 RV1108_CLKGATE_CON(19), 2, GFLAGS), 266 GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0, 267 RV1108_CLKGATE_CON(19), 3, GFLAGS), 268 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, 269 RV1108_CLKGATE_CON(19), 4, GFLAGS), 270 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, 271 RV1108_CLKGATE_CON(19), 5, GFLAGS), 272 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, 273 RV1108_CLKGATE_CON(19), 6, GFLAGS), 274 275 /* PD_PMU_wrapper */ 276 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED, 277 RV1108_CLKSEL_CON(38), 0, 5, DFLAGS, 278 RV1108_CLKGATE_CON(8), 12, GFLAGS), 279 GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 280 RV1108_CLKGATE_CON(10), 0, GFLAGS), 281 GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, 282 RV1108_CLKGATE_CON(10), 1, GFLAGS), 283 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0, 284 RV1108_CLKGATE_CON(10), 2, GFLAGS), 285 GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, 286 RV1108_CLKGATE_CON(10), 3, GFLAGS), 287 GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 288 RV1108_CLKGATE_CON(10), 4, GFLAGS), 289 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0, 290 RV1108_CLKGATE_CON(10), 5, GFLAGS), 291 GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0, 292 RV1108_CLKGATE_CON(10), 6, GFLAGS), 293 COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0, 294 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, 295 RV1108_CLKGATE_CON(8), 15, GFLAGS), 296 COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0, 297 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, 298 RV1108_CLKGATE_CON(8), 14, GFLAGS), 299 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, 300 RV1108_CLKGATE_CON(8), 13, GFLAGS), 301 302 /* 303 * Clock-Architecture Diagram 3 304 */ 305 COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0, 306 RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS, 307 RV1108_CLKGATE_CON(9), 8, GFLAGS), 308 COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0, 309 RV1108_CLKSEL_CON(40), 8, 1, MFLAGS, 310 RV1108_CLKGATE_CON(9), 11, GFLAGS), 311 COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0, 312 RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS), 313 COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0, 314 RV1108_CLKSEL_CON(41), 0, 5, DFLAGS, 315 RV1108_CLKGATE_CON(9), 12, GFLAGS), 316 317 GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 318 RV1108_CLKGATE_CON(14), 6, GFLAGS), 319 GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED, 320 RV1108_CLKGATE_CON(14), 14, GFLAGS), 321 322 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0, 323 RV1108_CLKGATE_CON(18), 10, GFLAGS), 324 GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0, 325 RV1108_CLKGATE_CON(18), 10, GFLAGS), 326 COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0, 327 RV1108_CLKSEL_CON(31), 0, 2, MFLAGS, 328 RV1108_CLKGATE_CON(7), 9, GFLAGS), 329 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0, 330 RV1108_CLKGATE_CON(17), 6, GFLAGS), 331 GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0, 332 RV1108_CLKGATE_CON(17), 7, GFLAGS), 333 COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0, 334 RV1108_CLKSEL_CON(31), 2, 2, MFLAGS, 335 RV1108_CLKGATE_CON(7), 10, GFLAGS), 336 GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0, 337 RV1108_CLKGATE_CON(17), 8, GFLAGS), 338 GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0, 339 RV1108_CLKGATE_CON(17), 9, GFLAGS), 340 COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0, 341 RV1108_CLKSEL_CON(31), 4, 2, MFLAGS, 342 RV1108_CLKGATE_CON(7), 11, GFLAGS), 343 GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0, 344 RV1108_CLKGATE_CON(17), 10, GFLAGS), 345 GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0, 346 RV1108_CLKGATE_CON(17), 11, GFLAGS), 347 COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0, 348 RV1108_CLKSEL_CON(31), 6, 2, MFLAGS, 349 RV1108_CLKGATE_CON(7), 12, GFLAGS), 350 GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED, 351 RV1108_CLKGATE_CON(7), 8, GFLAGS), 352 353 /* PD_DSP_wrapper */ 354 COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0, 355 RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS, 356 RV1108_CLKGATE_CON(9), 0, GFLAGS), 357 GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 358 RV1108_CLKGATE_CON(16), 0, GFLAGS), 359 GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 360 RV1108_CLKGATE_CON(16), 1, GFLAGS), 361 GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 362 RV1108_CLKGATE_CON(16), 2, GFLAGS), 363 GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 364 RV1108_CLKGATE_CON(16), 3, GFLAGS), 365 GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED, 366 RV1108_CLKGATE_CON(16), 13, GFLAGS), 367 COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0, 368 RV1108_CLKSEL_CON(44), 0, 5, DFLAGS, 369 RV1108_CLKGATE_CON(9), 1, GFLAGS), 370 COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0, 371 RV1108_CLKSEL_CON(44), 8, 5, DFLAGS, 372 RV1108_CLKGATE_CON(9), 2, GFLAGS), 373 COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0, 374 RV1108_CLKSEL_CON(45), 0, 5, DFLAGS, 375 RV1108_CLKGATE_CON(9), 3, GFLAGS), 376 COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0, 377 RV1108_CLKSEL_CON(45), 8, 5, DFLAGS, 378 RV1108_CLKGATE_CON(9), 4, GFLAGS), 379 GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED, 380 RV1108_CLKGATE_CON(16), 4, GFLAGS), 381 GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED, 382 RV1108_CLKGATE_CON(16), 5, GFLAGS), 383 GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED, 384 RV1108_CLKGATE_CON(16), 6, GFLAGS), 385 GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED, 386 RV1108_CLKGATE_CON(16), 7, GFLAGS), 387 GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED, 388 RV1108_CLKGATE_CON(16), 14, GFLAGS), 389 COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0, 390 RV1108_CLKSEL_CON(43), 0, 5, DFLAGS, 391 RV1108_CLKGATE_CON(9), 5, GFLAGS), 392 COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0, 393 RV1108_CLKSEL_CON(43), 8, 5, DFLAGS, 394 RV1108_CLKGATE_CON(9), 6, GFLAGS), 395 GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 396 RV1108_CLKGATE_CON(16), 8, GFLAGS), 397 GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 398 RV1108_CLKGATE_CON(16), 9, GFLAGS), 399 GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 400 RV1108_CLKGATE_CON(16), 10, GFLAGS), 401 GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 402 RV1108_CLKGATE_CON(16), 11, GFLAGS), 403 GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 404 RV1108_CLKGATE_CON(16), 12, GFLAGS), 405 GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED, 406 RV1108_CLKGATE_CON(16), 15, GFLAGS), 407 GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED, 408 RV1108_CLKGATE_CON(11), 8, GFLAGS), 409 410 /* 411 * Clock-Architecture Diagram 4 412 */ 413 COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 414 RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 415 RV1108_CLKGATE_CON(6), 0, GFLAGS), 416 GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0, 417 RV1108_CLKGATE_CON(17), 0, GFLAGS), 418 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0, 419 RV1108_CLKSEL_CON(29), 0, 5, DFLAGS, 420 RV1108_CLKGATE_CON(7), 2, GFLAGS), 421 GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0, 422 RV1108_CLKGATE_CON(17), 2, GFLAGS), 423 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0, 424 RV1108_CLKSEL_CON(29), 8, 5, DFLAGS, 425 RV1108_CLKGATE_CON(7), 3, GFLAGS), 426 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0, 427 RV1108_CLKGATE_CON(17), 3, GFLAGS), 428 COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 429 RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS, 430 RV1108_CLKGATE_CON(6), 1, GFLAGS), 431 GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0, 432 RV1108_CLKGATE_CON(17), 1, GFLAGS), 433 434 INVERTER(0, "pclk_vip", "ext_vip", 435 RV1108_CLKSEL_CON(31), 8, IFLAGS), 436 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED, 437 RV1108_CLKGATE_CON(7), 6, GFLAGS), 438 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED, 439 RV1108_CLKGATE_CON(18), 10, GFLAGS), 440 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED, 441 RV1108_CLKGATE_CON(6), 5, GFLAGS), 442 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED, 443 RV1108_CLKGATE_CON(6), 4, GFLAGS), 444 COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0, 445 RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS), 446 COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0, 447 RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS), 448 MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT, 449 RV1108_CLKSEL_CON(32), 15, 1, MFLAGS), 450 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT, 451 RV1108_CLKSEL_CON(32), 7, 1, MFLAGS), 452 GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0, 453 RV1108_CLKGATE_CON(18), 0, GFLAGS), 454 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, 455 RV1108_CLKGATE_CON(18), 1, GFLAGS), 456 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0, 457 RV1108_CLKGATE_CON(18), 2, GFLAGS), 458 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, 459 RV1108_CLKGATE_CON(18), 3, GFLAGS), 460 461 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0, 462 RV1108_CLKGATE_CON(18), 4, GFLAGS), 463 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, 464 RV1108_CLKGATE_CON(18), 5, GFLAGS), 465 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0, 466 RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS, 467 RV1108_CLKGATE_CON(6), 6, GFLAGS), 468 469 COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0, 470 RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS, 471 RV1108_CLKGATE_CON(6), 7, GFLAGS), 472 FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2), 473 474 GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0, 475 RV1108_CLKGATE_CON(6), 8, GFLAGS), 476 477 COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0, 478 RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS, 479 RV1108_CLKGATE_CON(6), 9, GFLAGS), 480 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0, 481 RV1108_CLKGATE_CON(18), 8, GFLAGS), 482 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0, 483 RV1108_CLKGATE_CON(18), 9, GFLAGS), 484 485 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0, 486 RV1108_CLKGATE_CON(18), 12, GFLAGS), 487 GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0, 488 RV1108_CLKGATE_CON(18), 11, GFLAGS), 489 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0, 490 RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, 491 RV1108_CLKGATE_CON(6), 3, GFLAGS), 492 493 GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED, 494 RV1108_CLKGATE_CON(9), 10, GFLAGS), 495 GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 496 RV1108_CLKGATE_CON(14), 9, GFLAGS), 497 GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 498 RV1108_CLKGATE_CON(14), 11, GFLAGS), 499 GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 500 RV1108_CLKGATE_CON(14), 12, GFLAGS), 501 502 /* 503 * Clock-Architecture Diagram 5 504 */ 505 506 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 507 508 509 COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0, 510 RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, 511 RV1108_CLKGATE_CON(2), 0, GFLAGS), 512 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, 513 RV1108_CLKSEL_CON(8), 0, 514 RV1108_CLKGATE_CON(2), 1, GFLAGS, 515 &rv1108_i2s0_fracmux), 516 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, 517 RV1108_CLKGATE_CON(2), 2, GFLAGS), 518 COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0, 519 RV1108_CLKSEL_CON(5), 15, 1, MFLAGS, 520 RV1108_CLKGATE_CON(2), 3, GFLAGS), 521 522 COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0, 523 RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, 524 RV1108_CLKGATE_CON(2), 4, GFLAGS), 525 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 526 RK2928_CLKSEL_CON(9), 0, 527 RK2928_CLKGATE_CON(2), 5, GFLAGS, 528 &rv1108_i2s1_fracmux), 529 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 530 RV1108_CLKGATE_CON(2), 6, GFLAGS), 531 532 COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0, 533 RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, 534 RV1108_CLKGATE_CON(3), 8, GFLAGS), 535 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, 536 RV1108_CLKSEL_CON(10), 0, 537 RV1108_CLKGATE_CON(2), 9, GFLAGS, 538 &rv1108_i2s2_fracmux), 539 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, 540 RV1108_CLKGATE_CON(2), 10, GFLAGS), 541 542 /* PD_BUS */ 543 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED, 544 RV1108_CLKGATE_CON(1), 0, GFLAGS), 545 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED, 546 RV1108_CLKGATE_CON(1), 1, GFLAGS), 547 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED, 548 RV1108_CLKGATE_CON(1), 2, GFLAGS), 549 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0, 550 RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), 551 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0, 552 RV1108_CLKSEL_CON(3), 0, 5, DFLAGS, 553 RV1108_CLKGATE_CON(1), 4, GFLAGS), 554 COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0, 555 RV1108_CLKSEL_CON(3), 8, 5, DFLAGS, 556 RV1108_CLKGATE_CON(1), 5, GFLAGS), 557 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0, 558 RV1108_CLKGATE_CON(1), 6, GFLAGS), 559 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 560 RV1108_CLKGATE_CON(1), 7, GFLAGS), 561 GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 562 RV1108_CLKGATE_CON(1), 8, GFLAGS), 563 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0, 564 RV1108_CLKGATE_CON(1), 9, GFLAGS), 565 GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED, 566 RV1108_CLKGATE_CON(1), 10, GFLAGS), 567 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, 568 RV1108_CLKGATE_CON(13), 4, GFLAGS), 569 570 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, 571 RV1108_CLKGATE_CON(12), 7, GFLAGS), 572 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0, 573 RV1108_CLKGATE_CON(12), 8, GFLAGS), 574 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, 575 RV1108_CLKGATE_CON(12), 9, GFLAGS), 576 577 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, 578 RV1108_CLKGATE_CON(12), 10, GFLAGS), 579 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, 580 RV1108_CLKGATE_CON(12), 11, GFLAGS), 581 COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0, 582 RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS, 583 RV1108_CLKGATE_CON(2), 12, GFLAGS), 584 585 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0, 586 RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS, 587 RV1108_CLKGATE_CON(3), 0, GFLAGS), 588 GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0, 589 RV1108_CLKGATE_CON(13), 5, GFLAGS), 590 591 COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 592 RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 593 RV1108_CLKGATE_CON(3), 1, GFLAGS), 594 COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 595 RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 596 RV1108_CLKGATE_CON(3), 3, GFLAGS), 597 COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 598 RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, 599 RV1108_CLKGATE_CON(3), 5, GFLAGS), 600 601 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 602 RV1108_CLKSEL_CON(16), 0, 603 RV1108_CLKGATE_CON(3), 2, GFLAGS, 604 &rv1108_uart0_fracmux), 605 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 606 RV1108_CLKSEL_CON(17), 0, 607 RV1108_CLKGATE_CON(3), 4, GFLAGS, 608 &rv1108_uart1_fracmux), 609 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 610 RV1108_CLKSEL_CON(18), 0, 611 RV1108_CLKGATE_CON(3), 6, GFLAGS, 612 &rv1108_uart2_fracmux), 613 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0, 614 RV1108_CLKGATE_CON(13), 10, GFLAGS), 615 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, 616 RV1108_CLKGATE_CON(13), 11, GFLAGS), 617 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, 618 RV1108_CLKGATE_CON(13), 12, GFLAGS), 619 620 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0, 621 RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS, 622 RV1108_CLKGATE_CON(3), 7, GFLAGS), 623 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0, 624 RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS, 625 RV1108_CLKGATE_CON(3), 8, GFLAGS), 626 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0, 627 RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS, 628 RV1108_CLKGATE_CON(3), 9, GFLAGS), 629 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, 630 RV1108_CLKGATE_CON(13), 0, GFLAGS), 631 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, 632 RV1108_CLKGATE_CON(13), 1, GFLAGS), 633 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, 634 RV1108_CLKGATE_CON(13), 2, GFLAGS), 635 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0, 636 RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, 637 RV1108_CLKGATE_CON(3), 10, GFLAGS), 638 GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0, 639 RV1108_CLKGATE_CON(13), 6, GFLAGS), 640 GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0, 641 RV1108_CLKGATE_CON(13), 3, GFLAGS), 642 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, 643 RV1108_CLKGATE_CON(13), 7, GFLAGS), 644 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, 645 RV1108_CLKGATE_CON(13), 8, GFLAGS), 646 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, 647 RV1108_CLKGATE_CON(13), 9, GFLAGS), 648 649 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, 650 RV1108_CLKGATE_CON(14), 0, GFLAGS), 651 GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0, 652 RV1108_CLKGATE_CON(12), 12, GFLAGS), 653 GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0, 654 RV1108_CLKGATE_CON(12), 13, GFLAGS), 655 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, 656 RV1108_CLKGATE_CON(13), 13, GFLAGS), 657 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, 658 RV1108_CLKSEL_CON(21), 0, 10, DFLAGS, 659 RV1108_CLKGATE_CON(3), 11, GFLAGS), 660 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, 661 RV1108_CLKGATE_CON(13), 14, GFLAGS), 662 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, 663 RV1108_CLKSEL_CON(22), 0, 10, DFLAGS, 664 RV1108_CLKGATE_CON(3), 12, GFLAGS), 665 666 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0, 667 RV1108_CLKGATE_CON(12), 2, GFLAGS), 668 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, 669 RV1108_CLKGATE_CON(12), 3, GFLAGS), 670 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, 671 RV1108_CLKGATE_CON(12), 1, GFLAGS), 672 673 /* PD_DDR */ 674 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, 675 RV1108_CLKGATE_CON(0), 8, GFLAGS), 676 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 677 RV1108_CLKGATE_CON(0), 9, GFLAGS), 678 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 679 RV1108_CLKGATE_CON(0), 10, GFLAGS), 680 COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, 681 RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, 682 DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 683 FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2), 684 GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED, 685 RV1108_CLKGATE_CON(10), 9, GFLAGS), 686 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 687 RV1108_CLKGATE_CON(12), 4, GFLAGS), 688 GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, 689 RV1108_CLKGATE_CON(12), 5, GFLAGS), 690 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 691 RV1108_CLKGATE_CON(12), 6, GFLAGS), 692 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED, 693 RV1108_CLKGATE_CON(0), 11, GFLAGS), 694 GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 695 RV1108_CLKGATE_CON(14), 2, GFLAGS), 696 GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 697 RV1108_CLKGATE_CON(14), 4, GFLAGS), 698 699 /* 700 * Clock-Architecture Diagram 6 701 */ 702 703 /* PD_PERI */ 704 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0, 705 RV1108_CLKSEL_CON(23), 10, 5, DFLAGS, 706 RV1108_CLKGATE_CON(4), 5, GFLAGS), 707 GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, 708 RV1108_CLKGATE_CON(15), 13, GFLAGS), 709 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0, 710 RV1108_CLKSEL_CON(23), 5, 5, DFLAGS, 711 RV1108_CLKGATE_CON(4), 4, GFLAGS), 712 GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, 713 RV1108_CLKGATE_CON(15), 12, GFLAGS), 714 715 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED, 716 RV1108_CLKGATE_CON(4), 1, GFLAGS), 717 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED, 718 RV1108_CLKGATE_CON(4), 2, GFLAGS), 719 COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0, 720 RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS, 721 RV1108_CLKGATE_CON(15), 11, GFLAGS), 722 723 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, 724 RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, 725 RV1108_CLKGATE_CON(5), 0, GFLAGS), 726 727 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 728 RV1108_CLKSEL_CON(25), 10, 2, MFLAGS, 729 RV1108_CLKGATE_CON(5), 2, GFLAGS), 730 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 731 RV1108_CLKSEL_CON(26), 0, 8, DFLAGS), 732 733 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, 734 RV1108_CLKSEL_CON(25), 12, 2, MFLAGS, 735 RV1108_CLKGATE_CON(5), 1, GFLAGS), 736 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, 737 RK2928_CLKSEL_CON(26), 8, 8, DFLAGS), 738 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS), 739 GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS), 740 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS), 741 742 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, 743 RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS, 744 RV1108_CLKGATE_CON(5), 3, GFLAGS), 745 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS), 746 747 GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS), 748 GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS), 749 GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS), 750 GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS), 751 GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS), 752 753 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0, 754 RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS, 755 RV1108_CLKGATE_CON(5), 4, GFLAGS), 756 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS), 757 758 COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0, 759 RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS, 760 RV1108_CLKGATE_CON(4), 10, GFLAGS), 761 MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT, 762 RV1108_CLKSEL_CON(24), 8, 1, MFLAGS), 763 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS), 764 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS), 765 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS), 766 GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS), 767 GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS), 768 769 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1), 770 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1), 771 772 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1), 773 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1), 774 775 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1), 776 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1), 777 }; 778 779 static const char *const rv1108_critical_clocks[] __initconst = { 780 "aclk_core", 781 "aclk_bus", 782 "hclk_bus", 783 "pclk_bus", 784 "aclk_periph", 785 "hclk_periph", 786 "pclk_periph", 787 "nclk_ddrupctl", 788 "pclk_ddrmon", 789 "pclk_acodecphy", 790 "pclk_pmu", 791 }; 792 793 static void __init rv1108_clk_init(struct device_node *np) 794 { 795 struct rockchip_clk_provider *ctx; 796 void __iomem *reg_base; 797 798 reg_base = of_iomap(np, 0); 799 if (!reg_base) { 800 pr_err("%s: could not map cru region\n", __func__); 801 return; 802 } 803 804 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 805 if (IS_ERR(ctx)) { 806 pr_err("%s: rockchip clk init failed\n", __func__); 807 iounmap(reg_base); 808 return; 809 } 810 811 rockchip_clk_register_plls(ctx, rv1108_pll_clks, 812 ARRAY_SIZE(rv1108_pll_clks), 813 RV1108_GRF_SOC_STATUS0); 814 rockchip_clk_register_branches(ctx, rv1108_clk_branches, 815 ARRAY_SIZE(rv1108_clk_branches)); 816 rockchip_clk_protect_critical(rv1108_critical_clocks, 817 ARRAY_SIZE(rv1108_critical_clocks)); 818 819 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 820 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 821 &rv1108_cpuclk_data, rv1108_cpuclk_rates, 822 ARRAY_SIZE(rv1108_cpuclk_rates)); 823 824 rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0), 825 ROCKCHIP_SOFTRST_HIWORD_MASK); 826 827 rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL); 828 829 rockchip_clk_of_add_provider(np, ctx); 830 } 831 CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init); 832