1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Shawn Lin <shawn.lin@rock-chips.com> 4 * Andy Yan <andy.yan@rock-chips.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk-provider.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/syscore_ops.h> 22 #include <dt-bindings/clock/rv1108-cru.h> 23 #include "clk.h" 24 25 #define RV1108_GRF_SOC_STATUS0 0x480 26 27 enum rv1108_plls { 28 apll, dpll, gpll, 29 }; 30 31 static struct rockchip_pll_rate_table rv1108_pll_rates[] = { 32 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 33 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 49 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 52 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 53 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 54 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 55 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 56 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 57 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 58 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 59 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 60 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 61 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 62 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 63 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 64 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 65 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 66 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 67 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 68 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 69 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 70 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 71 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 72 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 73 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 74 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 75 { /* sentinel */ }, 76 }; 77 78 #define RV1108_DIV_CORE_MASK 0xf 79 #define RV1108_DIV_CORE_SHIFT 4 80 81 #define RV1108_CLKSEL0(_core_peri_div) \ 82 { \ 83 .reg = RV1108_CLKSEL_CON(1), \ 84 .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\ 85 RV1108_DIV_CORE_SHIFT) \ 86 } 87 88 #define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \ 89 { \ 90 .prate = _prate, \ 91 .divs = { \ 92 RV1108_CLKSEL0(_core_peri_div), \ 93 }, \ 94 } 95 96 static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = { 97 RV1108_CPUCLK_RATE(1608000000, 7), 98 RV1108_CPUCLK_RATE(1512000000, 7), 99 RV1108_CPUCLK_RATE(1488000000, 5), 100 RV1108_CPUCLK_RATE(1416000000, 5), 101 RV1108_CPUCLK_RATE(1392000000, 5), 102 RV1108_CPUCLK_RATE(1296000000, 5), 103 RV1108_CPUCLK_RATE(1200000000, 5), 104 RV1108_CPUCLK_RATE(1104000000, 5), 105 RV1108_CPUCLK_RATE(1008000000, 5), 106 RV1108_CPUCLK_RATE(912000000, 5), 107 RV1108_CPUCLK_RATE(816000000, 3), 108 RV1108_CPUCLK_RATE(696000000, 3), 109 RV1108_CPUCLK_RATE(600000000, 3), 110 RV1108_CPUCLK_RATE(500000000, 3), 111 RV1108_CPUCLK_RATE(408000000, 1), 112 RV1108_CPUCLK_RATE(312000000, 1), 113 RV1108_CPUCLK_RATE(216000000, 1), 114 RV1108_CPUCLK_RATE(96000000, 1), 115 }; 116 117 static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { 118 .core_reg = RV1108_CLKSEL_CON(0), 119 .div_core_shift = 0, 120 .div_core_mask = 0x1f, 121 .mux_core_alt = 1, 122 .mux_core_main = 0, 123 .mux_core_shift = 8, 124 .mux_core_mask = 0x3, 125 }; 126 127 PNAME(mux_pll_p) = { "xin24m", "xin24m"}; 128 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; 129 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; 130 PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" }; 131 PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" }; 132 PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" }; 133 PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" }; 134 PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" }; 135 PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" }; 136 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" }; 137 PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" }; 138 PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" }; 139 PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" }; 140 PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" }; 141 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 142 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 143 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 144 PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" }; 145 PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; 146 PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" }; 147 PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" }; 148 PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" }; 149 PNAME(mux_wifi_src_p) = { "gpll", "xin24m" }; 150 PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" }; 151 PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" }; 152 PNAME(mux_sclk_cif0_src_p) = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" }; 153 PNAME(mux_sclk_cif1_src_p) = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" }; 154 PNAME(mux_sclk_cif2_src_p) = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" }; 155 PNAME(mux_sclk_cif3_src_p) = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" }; 156 PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" }; 157 PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" }; 158 PNAME(mux_dclk_vop_p) = { "dclk_hdmiphy", "dclk_vop_src" }; 159 PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" }; 160 PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" }; 161 162 static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = { 163 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), 164 RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates), 165 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), 166 RV1108_PLL_CON(11), 8, 1, 0, NULL), 167 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), 168 RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates), 169 }; 170 171 #define MFLAGS CLK_MUX_HIWORD_MASK 172 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 173 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 174 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 175 176 static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata = 177 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 178 RV1108_CLKSEL_CON(13), 8, 2, MFLAGS); 179 180 static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata = 181 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 182 RV1108_CLKSEL_CON(14), 8, 2, MFLAGS); 183 184 static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata = 185 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 186 RV1108_CLKSEL_CON(15), 8, 2, MFLAGS); 187 188 static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata = 189 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, 190 RV1108_CLKSEL_CON(5), 12, 2, MFLAGS); 191 192 static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata = 193 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, 194 RV1108_CLKSEL_CON(6), 12, 2, MFLAGS); 195 196 static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata = 197 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, 198 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS); 199 200 static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { 201 MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, 202 RV1108_MISC_CON, 13, 1, MFLAGS), 203 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, 204 RV1108_MISC_CON, 15, 1, MFLAGS), 205 /* 206 * Clock-Architecture Diagram 2 207 */ 208 209 /* PD_CORE */ 210 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, 211 RV1108_CLKGATE_CON(0), 1, GFLAGS), 212 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 213 RV1108_CLKGATE_CON(0), 0, GFLAGS), 214 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 215 RV1108_CLKGATE_CON(0), 2, GFLAGS), 216 COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED, 217 RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 218 RV1108_CLKGATE_CON(0), 5, GFLAGS), 219 COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED, 220 RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 221 RV1108_CLKGATE_CON(0), 4, GFLAGS), 222 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED, 223 RV1108_CLKGATE_CON(11), 0, GFLAGS), 224 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED, 225 RV1108_CLKGATE_CON(11), 1, GFLAGS), 226 227 /* PD_RKVENC */ 228 COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0, 229 RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS, 230 RV1108_CLKGATE_CON(8), 8, GFLAGS), 231 FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4, 232 RV1108_CLKGATE_CON(8), 10, GFLAGS), 233 COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0, 234 RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS, 235 RV1108_CLKGATE_CON(8), 9, GFLAGS), 236 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, 237 RV1108_CLKGATE_CON(19), 8, GFLAGS), 238 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, 239 RV1108_CLKGATE_CON(19), 9, GFLAGS), 240 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED, 241 RV1108_CLKGATE_CON(19), 11, GFLAGS), 242 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED, 243 RV1108_CLKGATE_CON(19), 10, GFLAGS), 244 245 /* PD_RKVDEC */ 246 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0, 247 RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS, 248 RV1108_CLKGATE_CON(8), 2, GFLAGS), 249 FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4, 250 RV1108_CLKGATE_CON(8), 10, GFLAGS), 251 COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0, 252 RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS, 253 RV1108_CLKGATE_CON(8), 1, GFLAGS), 254 255 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, 256 RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 257 RV1108_CLKGATE_CON(8), 0, GFLAGS), 258 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, 259 RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS, 260 RV1108_CLKGATE_CON(8), 3, GFLAGS), 261 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, 262 RV1108_CLKGATE_CON(19), 0, GFLAGS), 263 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, 264 RV1108_CLKGATE_CON(19), 1, GFLAGS), 265 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, 266 RV1108_CLKGATE_CON(19), 2, GFLAGS), 267 GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0, 268 RV1108_CLKGATE_CON(19), 3, GFLAGS), 269 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, 270 RV1108_CLKGATE_CON(19), 4, GFLAGS), 271 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, 272 RV1108_CLKGATE_CON(19), 5, GFLAGS), 273 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, 274 RV1108_CLKGATE_CON(19), 6, GFLAGS), 275 276 /* PD_PMU_wrapper */ 277 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED, 278 RV1108_CLKSEL_CON(38), 0, 5, DFLAGS, 279 RV1108_CLKGATE_CON(8), 12, GFLAGS), 280 GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 281 RV1108_CLKGATE_CON(10), 0, GFLAGS), 282 GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, 283 RV1108_CLKGATE_CON(10), 1, GFLAGS), 284 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0, 285 RV1108_CLKGATE_CON(10), 2, GFLAGS), 286 GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, 287 RV1108_CLKGATE_CON(10), 3, GFLAGS), 288 GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 289 RV1108_CLKGATE_CON(10), 4, GFLAGS), 290 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0, 291 RV1108_CLKGATE_CON(10), 5, GFLAGS), 292 GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0, 293 RV1108_CLKGATE_CON(10), 6, GFLAGS), 294 COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0, 295 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, 296 RV1108_CLKGATE_CON(8), 15, GFLAGS), 297 COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0, 298 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, 299 RV1108_CLKGATE_CON(8), 14, GFLAGS), 300 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, 301 RV1108_CLKGATE_CON(8), 13, GFLAGS), 302 303 /* 304 * Clock-Architecture Diagram 3 305 */ 306 COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0, 307 RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS, 308 RV1108_CLKGATE_CON(9), 8, GFLAGS), 309 COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0, 310 RV1108_CLKSEL_CON(40), 8, 1, MFLAGS, 311 RV1108_CLKGATE_CON(9), 11, GFLAGS), 312 COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0, 313 RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS), 314 COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0, 315 RV1108_CLKSEL_CON(41), 0, 5, DFLAGS, 316 RV1108_CLKGATE_CON(9), 12, GFLAGS), 317 318 GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 319 RV1108_CLKGATE_CON(14), 6, GFLAGS), 320 GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED, 321 RV1108_CLKGATE_CON(14), 14, GFLAGS), 322 323 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0, 324 RV1108_CLKGATE_CON(18), 10, GFLAGS), 325 GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0, 326 RV1108_CLKGATE_CON(18), 10, GFLAGS), 327 COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0, 328 RV1108_CLKSEL_CON(31), 0, 2, MFLAGS, 329 RV1108_CLKGATE_CON(7), 9, GFLAGS), 330 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0, 331 RV1108_CLKGATE_CON(17), 6, GFLAGS), 332 GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0, 333 RV1108_CLKGATE_CON(17), 7, GFLAGS), 334 COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0, 335 RV1108_CLKSEL_CON(31), 2, 2, MFLAGS, 336 RV1108_CLKGATE_CON(7), 10, GFLAGS), 337 GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0, 338 RV1108_CLKGATE_CON(17), 8, GFLAGS), 339 GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0, 340 RV1108_CLKGATE_CON(17), 9, GFLAGS), 341 COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0, 342 RV1108_CLKSEL_CON(31), 4, 2, MFLAGS, 343 RV1108_CLKGATE_CON(7), 11, GFLAGS), 344 GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0, 345 RV1108_CLKGATE_CON(17), 10, GFLAGS), 346 GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0, 347 RV1108_CLKGATE_CON(17), 11, GFLAGS), 348 COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0, 349 RV1108_CLKSEL_CON(31), 6, 2, MFLAGS, 350 RV1108_CLKGATE_CON(7), 12, GFLAGS), 351 GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED, 352 RV1108_CLKGATE_CON(7), 8, GFLAGS), 353 354 /* PD_DSP_wrapper */ 355 COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0, 356 RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS, 357 RV1108_CLKGATE_CON(9), 0, GFLAGS), 358 GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 359 RV1108_CLKGATE_CON(16), 0, GFLAGS), 360 GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 361 RV1108_CLKGATE_CON(16), 1, GFLAGS), 362 GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 363 RV1108_CLKGATE_CON(16), 2, GFLAGS), 364 GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED, 365 RV1108_CLKGATE_CON(16), 3, GFLAGS), 366 GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED, 367 RV1108_CLKGATE_CON(16), 13, GFLAGS), 368 COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0, 369 RV1108_CLKSEL_CON(44), 0, 5, DFLAGS, 370 RV1108_CLKGATE_CON(9), 1, GFLAGS), 371 COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0, 372 RV1108_CLKSEL_CON(44), 8, 5, DFLAGS, 373 RV1108_CLKGATE_CON(9), 2, GFLAGS), 374 COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0, 375 RV1108_CLKSEL_CON(45), 0, 5, DFLAGS, 376 RV1108_CLKGATE_CON(9), 3, GFLAGS), 377 COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0, 378 RV1108_CLKSEL_CON(45), 8, 5, DFLAGS, 379 RV1108_CLKGATE_CON(9), 4, GFLAGS), 380 GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED, 381 RV1108_CLKGATE_CON(16), 4, GFLAGS), 382 GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED, 383 RV1108_CLKGATE_CON(16), 5, GFLAGS), 384 GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED, 385 RV1108_CLKGATE_CON(16), 6, GFLAGS), 386 GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED, 387 RV1108_CLKGATE_CON(16), 7, GFLAGS), 388 GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED, 389 RV1108_CLKGATE_CON(16), 14, GFLAGS), 390 COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0, 391 RV1108_CLKSEL_CON(43), 0, 5, DFLAGS, 392 RV1108_CLKGATE_CON(9), 5, GFLAGS), 393 COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0, 394 RV1108_CLKSEL_CON(43), 8, 5, DFLAGS, 395 RV1108_CLKGATE_CON(9), 6, GFLAGS), 396 GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 397 RV1108_CLKGATE_CON(16), 8, GFLAGS), 398 GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 399 RV1108_CLKGATE_CON(16), 9, GFLAGS), 400 GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 401 RV1108_CLKGATE_CON(16), 10, GFLAGS), 402 GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 403 RV1108_CLKGATE_CON(16), 11, GFLAGS), 404 GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, 405 RV1108_CLKGATE_CON(16), 12, GFLAGS), 406 GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED, 407 RV1108_CLKGATE_CON(16), 15, GFLAGS), 408 GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED, 409 RV1108_CLKGATE_CON(11), 8, GFLAGS), 410 411 /* 412 * Clock-Architecture Diagram 4 413 */ 414 COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 415 RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 416 RV1108_CLKGATE_CON(6), 0, GFLAGS), 417 GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0, 418 RV1108_CLKGATE_CON(17), 0, GFLAGS), 419 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0, 420 RV1108_CLKSEL_CON(29), 0, 5, DFLAGS, 421 RV1108_CLKGATE_CON(7), 2, GFLAGS), 422 GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0, 423 RV1108_CLKGATE_CON(17), 2, GFLAGS), 424 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0, 425 RV1108_CLKSEL_CON(29), 8, 5, DFLAGS, 426 RV1108_CLKGATE_CON(7), 3, GFLAGS), 427 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0, 428 RV1108_CLKGATE_CON(17), 3, GFLAGS), 429 COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 430 RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS, 431 RV1108_CLKGATE_CON(6), 1, GFLAGS), 432 GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0, 433 RV1108_CLKGATE_CON(17), 1, GFLAGS), 434 435 INVERTER(0, "pclk_vip", "ext_vip", 436 RV1108_CLKSEL_CON(31), 8, IFLAGS), 437 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED, 438 RV1108_CLKGATE_CON(7), 6, GFLAGS), 439 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED, 440 RV1108_CLKGATE_CON(18), 10, GFLAGS), 441 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED, 442 RV1108_CLKGATE_CON(6), 5, GFLAGS), 443 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED, 444 RV1108_CLKGATE_CON(6), 4, GFLAGS), 445 COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0, 446 RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS), 447 COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0, 448 RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS), 449 MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT, 450 RV1108_CLKSEL_CON(32), 15, 1, MFLAGS), 451 MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT, 452 RV1108_CLKSEL_CON(32), 7, 1, MFLAGS), 453 GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0, 454 RV1108_CLKGATE_CON(18), 0, GFLAGS), 455 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, 456 RV1108_CLKGATE_CON(18), 1, GFLAGS), 457 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0, 458 RV1108_CLKGATE_CON(18), 2, GFLAGS), 459 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, 460 RV1108_CLKGATE_CON(18), 3, GFLAGS), 461 462 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0, 463 RV1108_CLKGATE_CON(18), 4, GFLAGS), 464 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, 465 RV1108_CLKGATE_CON(18), 5, GFLAGS), 466 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0, 467 RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS, 468 RV1108_CLKGATE_CON(6), 6, GFLAGS), 469 470 COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0, 471 RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS, 472 RV1108_CLKGATE_CON(6), 7, GFLAGS), 473 FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2), 474 475 GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0, 476 RV1108_CLKGATE_CON(6), 8, GFLAGS), 477 478 COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0, 479 RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS, 480 RV1108_CLKGATE_CON(6), 9, GFLAGS), 481 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0, 482 RV1108_CLKGATE_CON(18), 8, GFLAGS), 483 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0, 484 RV1108_CLKGATE_CON(18), 9, GFLAGS), 485 486 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0, 487 RV1108_CLKGATE_CON(18), 12, GFLAGS), 488 GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0, 489 RV1108_CLKGATE_CON(18), 11, GFLAGS), 490 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0, 491 RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, 492 RV1108_CLKGATE_CON(6), 3, GFLAGS), 493 494 GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED, 495 RV1108_CLKGATE_CON(9), 10, GFLAGS), 496 GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 497 RV1108_CLKGATE_CON(14), 9, GFLAGS), 498 GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 499 RV1108_CLKGATE_CON(14), 11, GFLAGS), 500 GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED, 501 RV1108_CLKGATE_CON(14), 12, GFLAGS), 502 503 /* 504 * Clock-Architecture Diagram 5 505 */ 506 507 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 508 509 510 COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0, 511 RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, 512 RV1108_CLKGATE_CON(2), 0, GFLAGS), 513 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, 514 RV1108_CLKSEL_CON(8), 0, 515 RV1108_CLKGATE_CON(2), 1, GFLAGS, 516 &rv1108_i2s0_fracmux), 517 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, 518 RV1108_CLKGATE_CON(2), 2, GFLAGS), 519 COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0, 520 RV1108_CLKSEL_CON(5), 15, 1, MFLAGS, 521 RV1108_CLKGATE_CON(2), 3, GFLAGS), 522 523 COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0, 524 RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, 525 RV1108_CLKGATE_CON(2), 4, GFLAGS), 526 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 527 RK2928_CLKSEL_CON(9), 0, 528 RK2928_CLKGATE_CON(2), 5, GFLAGS, 529 &rv1108_i2s1_fracmux), 530 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 531 RV1108_CLKGATE_CON(2), 6, GFLAGS), 532 533 COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0, 534 RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, 535 RV1108_CLKGATE_CON(3), 8, GFLAGS), 536 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, 537 RV1108_CLKSEL_CON(10), 0, 538 RV1108_CLKGATE_CON(2), 9, GFLAGS, 539 &rv1108_i2s2_fracmux), 540 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, 541 RV1108_CLKGATE_CON(2), 10, GFLAGS), 542 543 /* PD_BUS */ 544 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED, 545 RV1108_CLKGATE_CON(1), 0, GFLAGS), 546 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED, 547 RV1108_CLKGATE_CON(1), 1, GFLAGS), 548 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED, 549 RV1108_CLKGATE_CON(1), 2, GFLAGS), 550 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0, 551 RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), 552 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0, 553 RV1108_CLKSEL_CON(3), 0, 5, DFLAGS, 554 RV1108_CLKGATE_CON(1), 4, GFLAGS), 555 COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0, 556 RV1108_CLKSEL_CON(3), 8, 5, DFLAGS, 557 RV1108_CLKGATE_CON(1), 5, GFLAGS), 558 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0, 559 RV1108_CLKGATE_CON(1), 6, GFLAGS), 560 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 561 RV1108_CLKGATE_CON(1), 7, GFLAGS), 562 GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 563 RV1108_CLKGATE_CON(1), 8, GFLAGS), 564 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0, 565 RV1108_CLKGATE_CON(1), 9, GFLAGS), 566 GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED, 567 RV1108_CLKGATE_CON(1), 10, GFLAGS), 568 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, 569 RV1108_CLKGATE_CON(13), 4, GFLAGS), 570 571 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, 572 RV1108_CLKGATE_CON(12), 7, GFLAGS), 573 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0, 574 RV1108_CLKGATE_CON(12), 8, GFLAGS), 575 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, 576 RV1108_CLKGATE_CON(12), 9, GFLAGS), 577 578 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, 579 RV1108_CLKGATE_CON(12), 10, GFLAGS), 580 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, 581 RV1108_CLKGATE_CON(12), 11, GFLAGS), 582 COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0, 583 RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS, 584 RV1108_CLKGATE_CON(2), 12, GFLAGS), 585 586 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0, 587 RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS, 588 RV1108_CLKGATE_CON(3), 0, GFLAGS), 589 GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0, 590 RV1108_CLKGATE_CON(13), 5, GFLAGS), 591 592 COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 593 RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 594 RV1108_CLKGATE_CON(3), 1, GFLAGS), 595 COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 596 RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 597 RV1108_CLKGATE_CON(3), 3, GFLAGS), 598 COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 599 RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, 600 RV1108_CLKGATE_CON(3), 5, GFLAGS), 601 602 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 603 RV1108_CLKSEL_CON(16), 0, 604 RV1108_CLKGATE_CON(3), 2, GFLAGS, 605 &rv1108_uart0_fracmux), 606 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 607 RV1108_CLKSEL_CON(17), 0, 608 RV1108_CLKGATE_CON(3), 4, GFLAGS, 609 &rv1108_uart1_fracmux), 610 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 611 RV1108_CLKSEL_CON(18), 0, 612 RV1108_CLKGATE_CON(3), 6, GFLAGS, 613 &rv1108_uart2_fracmux), 614 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0, 615 RV1108_CLKGATE_CON(13), 10, GFLAGS), 616 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, 617 RV1108_CLKGATE_CON(13), 11, GFLAGS), 618 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, 619 RV1108_CLKGATE_CON(13), 12, GFLAGS), 620 621 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0, 622 RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS, 623 RV1108_CLKGATE_CON(3), 7, GFLAGS), 624 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0, 625 RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS, 626 RV1108_CLKGATE_CON(3), 8, GFLAGS), 627 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0, 628 RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS, 629 RV1108_CLKGATE_CON(3), 9, GFLAGS), 630 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, 631 RV1108_CLKGATE_CON(13), 0, GFLAGS), 632 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, 633 RV1108_CLKGATE_CON(13), 1, GFLAGS), 634 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, 635 RV1108_CLKGATE_CON(13), 2, GFLAGS), 636 COMPOSITE(SCLK_PWM, "clk_pwm", mux_pll_src_2plls_p, 0, 637 RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, 638 RV1108_CLKGATE_CON(3), 10, GFLAGS), 639 GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0, 640 RV1108_CLKGATE_CON(13), 6, GFLAGS), 641 GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0, 642 RV1108_CLKGATE_CON(13), 3, GFLAGS), 643 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, 644 RV1108_CLKGATE_CON(13), 7, GFLAGS), 645 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, 646 RV1108_CLKGATE_CON(13), 8, GFLAGS), 647 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, 648 RV1108_CLKGATE_CON(13), 9, GFLAGS), 649 650 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, 651 RV1108_CLKGATE_CON(14), 0, GFLAGS), 652 GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0, 653 RV1108_CLKGATE_CON(12), 12, GFLAGS), 654 GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0, 655 RV1108_CLKGATE_CON(12), 13, GFLAGS), 656 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, 657 RV1108_CLKGATE_CON(13), 13, GFLAGS), 658 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, 659 RV1108_CLKSEL_CON(21), 0, 10, DFLAGS, 660 RV1108_CLKGATE_CON(3), 11, GFLAGS), 661 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, 662 RV1108_CLKGATE_CON(13), 14, GFLAGS), 663 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, 664 RV1108_CLKSEL_CON(22), 0, 10, DFLAGS, 665 RV1108_CLKGATE_CON(3), 12, GFLAGS), 666 667 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0, 668 RV1108_CLKGATE_CON(12), 2, GFLAGS), 669 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, 670 RV1108_CLKGATE_CON(12), 3, GFLAGS), 671 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, 672 RV1108_CLKGATE_CON(12), 1, GFLAGS), 673 674 /* PD_DDR */ 675 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, 676 RV1108_CLKGATE_CON(0), 8, GFLAGS), 677 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 678 RV1108_CLKGATE_CON(0), 9, GFLAGS), 679 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 680 RV1108_CLKGATE_CON(0), 10, GFLAGS), 681 COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, 682 RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, 683 DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 684 FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2), 685 GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED, 686 RV1108_CLKGATE_CON(10), 9, GFLAGS), 687 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 688 RV1108_CLKGATE_CON(12), 4, GFLAGS), 689 GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, 690 RV1108_CLKGATE_CON(12), 5, GFLAGS), 691 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 692 RV1108_CLKGATE_CON(12), 6, GFLAGS), 693 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED, 694 RV1108_CLKGATE_CON(0), 11, GFLAGS), 695 GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 696 RV1108_CLKGATE_CON(14), 2, GFLAGS), 697 GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED, 698 RV1108_CLKGATE_CON(14), 4, GFLAGS), 699 700 /* 701 * Clock-Architecture Diagram 6 702 */ 703 704 /* PD_PERI */ 705 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0, 706 RV1108_CLKSEL_CON(23), 10, 5, DFLAGS, 707 RV1108_CLKGATE_CON(4), 5, GFLAGS), 708 GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, 709 RV1108_CLKGATE_CON(15), 13, GFLAGS), 710 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0, 711 RV1108_CLKSEL_CON(23), 5, 5, DFLAGS, 712 RV1108_CLKGATE_CON(4), 4, GFLAGS), 713 GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, 714 RV1108_CLKGATE_CON(15), 12, GFLAGS), 715 716 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED, 717 RV1108_CLKGATE_CON(4), 1, GFLAGS), 718 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED, 719 RV1108_CLKGATE_CON(4), 2, GFLAGS), 720 COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0, 721 RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS, 722 RV1108_CLKGATE_CON(15), 11, GFLAGS), 723 724 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, 725 RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, 726 RV1108_CLKGATE_CON(5), 0, GFLAGS), 727 728 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 729 RV1108_CLKSEL_CON(25), 10, 2, MFLAGS, 730 RV1108_CLKGATE_CON(5), 2, GFLAGS), 731 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 732 RV1108_CLKSEL_CON(26), 0, 8, DFLAGS), 733 734 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, 735 RV1108_CLKSEL_CON(25), 12, 2, MFLAGS, 736 RV1108_CLKGATE_CON(5), 1, GFLAGS), 737 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, 738 RK2928_CLKSEL_CON(26), 8, 8, DFLAGS), 739 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS), 740 GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS), 741 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS), 742 743 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, 744 RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS, 745 RV1108_CLKGATE_CON(5), 3, GFLAGS), 746 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS), 747 748 GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS), 749 GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS), 750 GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS), 751 GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS), 752 GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS), 753 754 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0, 755 RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS, 756 RV1108_CLKGATE_CON(5), 4, GFLAGS), 757 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS), 758 759 COMPOSITE(SCLK_MAC_PRE, "sclk_mac_pre", mux_pll_src_apll_gpll_p, 0, 760 RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS, 761 RV1108_CLKGATE_CON(4), 10, GFLAGS), 762 MUX(SCLK_MAC, "sclk_mac", mux_sclk_mac_p, CLK_SET_RATE_PARENT, 763 RV1108_CLKSEL_CON(24), 8, 1, MFLAGS), 764 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS), 765 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS), 766 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS), 767 GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS), 768 GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS), 769 770 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1), 771 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1), 772 773 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1), 774 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1), 775 776 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1), 777 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1), 778 }; 779 780 static const char *const rv1108_critical_clocks[] __initconst = { 781 "aclk_core", 782 "aclk_bus", 783 "hclk_bus", 784 "pclk_bus", 785 "aclk_periph", 786 "hclk_periph", 787 "pclk_periph", 788 "nclk_ddrupctl", 789 "pclk_ddrmon", 790 "pclk_acodecphy", 791 "pclk_pmu", 792 }; 793 794 static void __init rv1108_clk_init(struct device_node *np) 795 { 796 struct rockchip_clk_provider *ctx; 797 void __iomem *reg_base; 798 799 reg_base = of_iomap(np, 0); 800 if (!reg_base) { 801 pr_err("%s: could not map cru region\n", __func__); 802 return; 803 } 804 805 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 806 if (IS_ERR(ctx)) { 807 pr_err("%s: rockchip clk init failed\n", __func__); 808 iounmap(reg_base); 809 return; 810 } 811 812 rockchip_clk_register_plls(ctx, rv1108_pll_clks, 813 ARRAY_SIZE(rv1108_pll_clks), 814 RV1108_GRF_SOC_STATUS0); 815 rockchip_clk_register_branches(ctx, rv1108_clk_branches, 816 ARRAY_SIZE(rv1108_clk_branches)); 817 rockchip_clk_protect_critical(rv1108_critical_clocks, 818 ARRAY_SIZE(rv1108_critical_clocks)); 819 820 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 821 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 822 &rv1108_cpuclk_data, rv1108_cpuclk_rates, 823 ARRAY_SIZE(rv1108_cpuclk_rates)); 824 825 rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0), 826 ROCKCHIP_SOFTRST_HIWORD_MASK); 827 828 rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL); 829 830 rockchip_clk_of_add_provider(np, ctx); 831 } 832 CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init); 833