1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4  * Author: Elaine Zhang <zhangqing@rock-chips.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/of_address.h>
12 #include <linux/syscore_ops.h>
13 #include <dt-bindings/clock/rk3568-cru.h>
14 #include "clk.h"
15 
16 #define RK3568_GRF_SOC_STATUS0	0x580
17 
18 enum rk3568_pmu_plls {
19 	ppll, hpll,
20 };
21 
22 enum rk3568_plls {
23 	apll, dpll, gpll, cpll, npll, vpll,
24 };
25 
26 static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
27 	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
28 	RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
29 	RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
30 	RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
31 	RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
32 	RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
33 	RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
34 	RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
35 	RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
36 	RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
37 	RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
38 	RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
39 	RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
40 	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
41 	RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
42 	RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
43 	RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
44 	RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
45 	RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
46 	RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
47 	RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
48 	RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
49 	RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
50 	RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
51 	RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
52 	RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
53 	RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
54 	RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
55 	RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
56 	RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
57 	RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
58 	RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
59 	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
60 	RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
61 	RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
62 	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
63 	RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
64 	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
65 	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
66 	RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
67 	RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
68 	RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
69 	RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
70 	RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
71 	RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
72 	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
73 	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
74 	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
75 	RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
76 	RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
77 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
78 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
79 	RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
80 	{ /* sentinel */ },
81 };
82 
83 #define RK3568_DIV_ATCLK_CORE_MASK	0x1f
84 #define RK3568_DIV_ATCLK_CORE_SHIFT	0
85 #define RK3568_DIV_GICCLK_CORE_MASK	0x1f
86 #define RK3568_DIV_GICCLK_CORE_SHIFT	8
87 #define RK3568_DIV_PCLK_CORE_MASK	0x1f
88 #define RK3568_DIV_PCLK_CORE_SHIFT	0
89 #define RK3568_DIV_PERIPHCLK_CORE_MASK	0x1f
90 #define RK3568_DIV_PERIPHCLK_CORE_SHIFT	8
91 #define RK3568_DIV_ACLK_CORE_MASK	0x1f
92 #define RK3568_DIV_ACLK_CORE_SHIFT	8
93 
94 #define RK3568_DIV_SCLK_CORE_MASK	0xf
95 #define RK3568_DIV_SCLK_CORE_SHIFT	0
96 #define RK3568_MUX_SCLK_CORE_MASK	0x3
97 #define RK3568_MUX_SCLK_CORE_SHIFT	8
98 #define RK3568_MUX_SCLK_CORE_NPLL_MASK	0x1
99 #define RK3568_MUX_SCLK_CORE_NPLL_SHIFT	15
100 #define RK3568_MUX_CLK_CORE_APLL_MASK	0x1
101 #define RK3568_MUX_CLK_CORE_APLL_SHIFT	7
102 #define RK3568_MUX_CLK_PVTPLL_MASK	0x1
103 #define RK3568_MUX_CLK_PVTPLL_SHIFT	15
104 
105 #define RK3568_CLKSEL1(_sclk_core)					\
106 {								\
107 	.reg = RK3568_CLKSEL_CON(2),				\
108 	.val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
109 			RK3568_MUX_SCLK_CORE_NPLL_SHIFT) |		\
110 	       HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
111 			RK3568_MUX_SCLK_CORE_SHIFT) |		\
112 		HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
113 			RK3568_DIV_SCLK_CORE_SHIFT),		\
114 }
115 
116 #define RK3568_CLKSEL2(_aclk_core)					\
117 {								\
118 	.reg = RK3568_CLKSEL_CON(5),				\
119 	.val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
120 			RK3568_DIV_ACLK_CORE_SHIFT),		\
121 }
122 
123 #define RK3568_CLKSEL3(_atclk_core, _gic_core)	\
124 {								\
125 	.reg = RK3568_CLKSEL_CON(3),				\
126 	.val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
127 			RK3568_DIV_ATCLK_CORE_SHIFT) |		\
128 	       HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
129 			RK3568_DIV_GICCLK_CORE_SHIFT),		\
130 }
131 
132 #define RK3568_CLKSEL4(_pclk_core, _periph_core)	\
133 {								\
134 	.reg = RK3568_CLKSEL_CON(4),				\
135 	.val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
136 			RK3568_DIV_PCLK_CORE_SHIFT) |		\
137 	       HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
138 			RK3568_DIV_PERIPHCLK_CORE_SHIFT),		\
139 }
140 
141 #define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
142 {								\
143 	.prate = _prate##U,					\
144 	.divs = {						\
145 		RK3568_CLKSEL1(_sclk),				\
146 		RK3568_CLKSEL2(_acore),				\
147 		RK3568_CLKSEL3(_atcore, _gicclk),		\
148 		RK3568_CLKSEL4(_pclk, _periph),			\
149 	},							\
150 }
151 
152 static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
153 	RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
154 	RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
155 	RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
156 	RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
157 	RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
158 	RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
159 	RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
160 	RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
161 	RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
162 	RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
163 	RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
164 	RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
165 	RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
166 	RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
167 	RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5),
168 	RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
169 	RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
170 	RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
171 	RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
172 	RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
173 	RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
174 	RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
175 	RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
176 	RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
177 	RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
178 	RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
179 	RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
180 	RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
181 	RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
182 	RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
183 };
184 
185 static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
186 	.core_reg[0] = RK3568_CLKSEL_CON(0),
187 	.div_core_shift[0] = 0,
188 	.div_core_mask[0] = 0x1f,
189 	.core_reg[1] = RK3568_CLKSEL_CON(0),
190 	.div_core_shift[1] = 8,
191 	.div_core_mask[1] = 0x1f,
192 	.core_reg[2] = RK3568_CLKSEL_CON(1),
193 	.div_core_shift[2] = 0,
194 	.div_core_mask[2] = 0x1f,
195 	.core_reg[3] = RK3568_CLKSEL_CON(1),
196 	.div_core_shift[3] = 8,
197 	.div_core_mask[3] = 0x1f,
198 	.num_cores = 4,
199 	.mux_core_alt = 1,
200 	.mux_core_main = 0,
201 	.mux_core_shift = 6,
202 	.mux_core_mask = 0x1,
203 };
204 
205 PNAME(mux_pll_p)			= { "xin24m" };
206 PNAME(mux_usb480m_p)			= { "xin24m", "usb480m_phy", "clk_rtc_32k" };
207 PNAME(mux_armclk_p)			= { "apll", "gpll" };
208 PNAME(clk_i2s0_8ch_tx_p)		= { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
209 PNAME(clk_i2s0_8ch_rx_p)		= { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
210 PNAME(clk_i2s1_8ch_tx_p)		= { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" };
211 PNAME(clk_i2s1_8ch_rx_p)		= { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" };
212 PNAME(clk_i2s2_2ch_p)			= { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "};
213 PNAME(clk_i2s3_2ch_tx_p)		= { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" };
214 PNAME(clk_i2s3_2ch_rx_p)		= { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" };
215 PNAME(mclk_spdif_8ch_p)			= { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
216 PNAME(sclk_audpwm_p)			= { "sclk_audpwm_src", "sclk_audpwm_frac" };
217 PNAME(sclk_uart1_p)			= { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
218 PNAME(sclk_uart2_p)			= { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
219 PNAME(sclk_uart3_p)			= { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
220 PNAME(sclk_uart4_p)			= { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
221 PNAME(sclk_uart5_p)			= { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
222 PNAME(sclk_uart6_p)			= { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
223 PNAME(sclk_uart7_p)			= { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
224 PNAME(sclk_uart8_p)			= { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
225 PNAME(sclk_uart9_p)			= { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
226 PNAME(sclk_uart0_p)			= { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
227 PNAME(clk_rtc32k_pmu_p)			= { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" };
228 PNAME(mpll_gpll_cpll_npll_p)		= { "mpll", "gpll", "cpll", "npll" };
229 PNAME(gpll_cpll_npll_p)			= { "gpll", "cpll", "npll" };
230 PNAME(npll_gpll_p)			= { "npll", "gpll" };
231 PNAME(cpll_gpll_p)			= { "cpll", "gpll" };
232 PNAME(gpll_cpll_p)			= { "gpll", "cpll" };
233 PNAME(gpll_cpll_npll_vpll_p)		= { "gpll", "cpll", "npll", "vpll" };
234 PNAME(apll_gpll_npll_p)			= { "apll", "gpll", "npll" };
235 PNAME(sclk_core_pre_p)			= { "sclk_core_src", "npll" };
236 PNAME(gpll150_gpll100_gpll75_xin24m_p)	= { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" };
237 PNAME(clk_gpu_pre_mux_p)		= { "clk_gpu_src", "gpu_pvtpll_out" };
238 PNAME(clk_npu_pre_ndft_p)		= { "clk_npu_src", "dummy"};
239 PNAME(clk_npu_p)			= { "clk_npu_pre_ndft", "npu_pvtpll_out" };
240 PNAME(dpll_gpll_cpll_p)			= { "dpll", "gpll", "cpll" };
241 PNAME(clk_ddr1x_p)			= { "clk_ddrphy1x_src", "dpll" };
242 PNAME(gpll200_gpll150_gpll100_xin24m_p)	= { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
243 PNAME(gpll100_gpll75_gpll50_p)		= { "gpll_100m", "gpll_75m", "cpll_50m" };
244 PNAME(i2s0_mclkout_tx_p)		= { "clk_i2s0_8ch_tx", "xin_osc0_half" };
245 PNAME(i2s0_mclkout_rx_p)		= { "clk_i2s0_8ch_rx", "xin_osc0_half" };
246 PNAME(i2s1_mclkout_tx_p)		= { "clk_i2s1_8ch_tx", "xin_osc0_half" };
247 PNAME(i2s1_mclkout_rx_p)		= { "clk_i2s1_8ch_rx", "xin_osc0_half" };
248 PNAME(i2s2_mclkout_p)			= { "clk_i2s2_2ch", "xin_osc0_half" };
249 PNAME(i2s3_mclkout_tx_p)		= { "clk_i2s3_2ch_tx", "xin_osc0_half" };
250 PNAME(i2s3_mclkout_rx_p)		= { "clk_i2s3_2ch_rx", "xin_osc0_half" };
251 PNAME(mclk_pdm_p)			= { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
252 PNAME(clk_i2c_p)			= { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
253 PNAME(gpll200_gpll150_gpll100_p)	= { "gpll_200m", "gpll_150m", "gpll_100m" };
254 PNAME(gpll300_gpll200_gpll100_p)	= { "gpll_300m", "gpll_200m", "gpll_100m" };
255 PNAME(clk_nandc_p)			= { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" };
256 PNAME(sclk_sfc_p)			= { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" };
257 PNAME(gpll200_gpll150_cpll125_p)	= { "gpll_200m", "gpll_150m", "cpll_125m" };
258 PNAME(cclk_emmc_p)			= { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" };
259 PNAME(aclk_pipe_p)			= { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
260 PNAME(gpll200_cpll125_p)		= { "gpll_200m", "cpll_125m" };
261 PNAME(gpll300_gpll200_gpll100_xin24m_p)	= { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" };
262 PNAME(clk_sdmmc_p)			= { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" };
263 PNAME(cpll125_cpll50_cpll25_xin24m_p)	= { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" };
264 PNAME(clk_gmac_ptp_p)			= { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" };
265 PNAME(cpll333_gpll300_gpll200_p)	= { "cpll_333m", "gpll_300m", "gpll_200m" };
266 PNAME(cpll_gpll_hpll_p)			= { "cpll", "gpll", "hpll" };
267 PNAME(gpll_usb480m_xin24m_p)		= { "gpll", "usb480m", "xin24m", "xin24m" };
268 PNAME(gpll300_cpll250_gpll100_xin24m_p)	= { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" };
269 PNAME(cpll_gpll_hpll_vpll_p)		= { "cpll", "gpll", "hpll", "vpll" };
270 PNAME(hpll_vpll_gpll_cpll_p)		= { "hpll", "vpll", "gpll", "cpll" };
271 PNAME(gpll400_cpll333_gpll200_p)	= { "gpll_400m", "cpll_333m", "gpll_200m" };
272 PNAME(gpll100_gpll75_cpll50_xin24m_p)	= { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" };
273 PNAME(xin24m_gpll100_cpll100_p)		= { "xin24m", "gpll_100m", "cpll_100m" };
274 PNAME(gpll_cpll_usb480m_p)		= { "gpll", "cpll", "usb480m" };
275 PNAME(gpll100_xin24m_cpll100_p)		= { "gpll_100m", "xin24m", "cpll_100m" };
276 PNAME(gpll200_xin24m_cpll100_p)		= { "gpll_200m", "xin24m", "cpll_100m" };
277 PNAME(xin24m_32k_p)			= { "xin24m", "clk_rtc_32k" };
278 PNAME(cpll500_gpll400_gpll300_xin24m_p)	= { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" };
279 PNAME(gpll400_gpll300_gpll200_xin24m_p)	= { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
280 PNAME(xin24m_cpll100_p)			= { "xin24m", "cpll_100m" };
281 PNAME(ppll_usb480m_cpll_gpll_p)		= { "ppll", "usb480m", "cpll", "gpll"};
282 PNAME(clk_usbphy0_ref_p)		= { "clk_ref24m", "xin_osc0_usbphy0_g" };
283 PNAME(clk_usbphy1_ref_p)		= { "clk_ref24m", "xin_osc0_usbphy1_g" };
284 PNAME(clk_mipidsiphy0_ref_p)		= { "clk_ref24m", "xin_osc0_mipidsiphy0_g" };
285 PNAME(clk_mipidsiphy1_ref_p)		= { "clk_ref24m", "xin_osc0_mipidsiphy1_g" };
286 PNAME(clk_wifi_p)			= { "clk_wifi_osc0", "clk_wifi_div" };
287 PNAME(clk_pciephy0_ref_p)		= { "clk_pciephy0_osc0", "clk_pciephy0_div" };
288 PNAME(clk_pciephy1_ref_p)		= { "clk_pciephy1_osc0", "clk_pciephy1_div" };
289 PNAME(clk_pciephy2_ref_p)		= { "clk_pciephy2_osc0", "clk_pciephy2_div" };
290 PNAME(mux_gmac0_p)			= { "clk_mac0_2top", "gmac0_clkin" };
291 PNAME(mux_gmac0_rgmii_speed_p)		= { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" };
292 PNAME(mux_gmac0_rmii_speed_p)		= { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
293 PNAME(mux_gmac0_rx_tx_p)		= { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" };
294 PNAME(mux_gmac1_p)			= { "clk_mac1_2top", "gmac1_clkin" };
295 PNAME(mux_gmac1_rgmii_speed_p)		= { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" };
296 PNAME(mux_gmac1_rmii_speed_p)		= { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
297 PNAME(mux_gmac1_rx_tx_p)		= { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" };
298 PNAME(clk_hdmi_ref_p)			= { "hpll", "hpll_ph0" };
299 PNAME(clk_pdpmu_p)			= { "ppll", "gpll" };
300 PNAME(clk_mac_2top_p)			= { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
301 PNAME(clk_pwm0_p)			= { "xin24m", "clk_pdpmu" };
302 PNAME(aclk_rkvdec_pre_p)		= { "gpll", "cpll" };
303 PNAME(clk_rkvdec_core_p)		= { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
304 
305 static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
306 	[ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll",  mux_pll_p,
307 		     0, RK3568_PMU_PLL_CON(0),
308 		     RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates),
309 	[hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll",  mux_pll_p,
310 		     0, RK3568_PMU_PLL_CON(16),
311 		     RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates),
312 };
313 
314 static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = {
315 	[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
316 		     0, RK3568_PLL_CON(0),
317 		     RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
318 	[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
319 		     0, RK3568_PLL_CON(8),
320 		     RK3568_MODE_CON0, 2, 1, 0, NULL),
321 	[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
322 		     0, RK3568_PLL_CON(24),
323 		     RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates),
324 	[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
325 		     0, RK3568_PLL_CON(16),
326 		     RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates),
327 	[npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
328 		     0, RK3568_PLL_CON(32),
329 		     RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates),
330 	[vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
331 		     0, RK3568_PLL_CON(40),
332 		     RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates),
333 };
334 
335 #define MFLAGS CLK_MUX_HIWORD_MASK
336 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
337 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
338 
339 static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata =
340 	MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
341 			RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
342 
343 static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata =
344 	MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
345 			RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
346 
347 static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata =
348 	MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
349 			RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
350 
351 static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata =
352 	MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
353 			RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
354 
355 static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata =
356 	MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
357 			RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
358 
359 static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata =
360 	MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT,
361 			RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
362 
363 static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata =
364 	MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT,
365 			RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
366 
367 static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata =
368 	MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT,
369 			RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
370 
371 static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata =
372 	MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT,
373 			RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
374 
375 static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata =
376 	MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT,
377 			RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
378 
379 static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata =
380 	MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT,
381 			RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
382 
383 static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata =
384 	MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT,
385 			RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
386 
387 static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata =
388 	MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT,
389 			RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
390 
391 static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata =
392 	MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT,
393 			RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
394 
395 static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata =
396 	MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT,
397 			RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
398 
399 static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata =
400 	MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT,
401 			RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
402 
403 static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata =
404 	MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT,
405 			RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
406 
407 static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata =
408 	MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT,
409 			RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
410 
411 static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata =
412 	MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT,
413 			RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
414 
415 static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata =
416 	MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
417 			RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
418 
419 static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
420 	/*
421 	 * Clock-Architecture Diagram 1
422 	 */
423 	 /* SRC_CLK */
424 	COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED,
425 			RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
426 			RK3568_CLKGATE_CON(35), 0, GFLAGS),
427 	COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED,
428 			RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
429 			RK3568_CLKGATE_CON(35), 1, GFLAGS),
430 	COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED,
431 			RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
432 			RK3568_CLKGATE_CON(35), 2, GFLAGS),
433 	COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED,
434 			RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
435 			RK3568_CLKGATE_CON(35), 3, GFLAGS),
436 	COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED,
437 			RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
438 			RK3568_CLKGATE_CON(35), 4, GFLAGS),
439 	COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED,
440 			RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
441 			RK3568_CLKGATE_CON(35), 5, GFLAGS),
442 	COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED,
443 			RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
444 			RK3568_CLKGATE_CON(35), 6, GFLAGS),
445 	COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
446 			RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
447 			RK3568_CLKGATE_CON(35), 7, GFLAGS),
448 	COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
449 			RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
450 			RK3568_CLKGATE_CON(35), 8, GFLAGS),
451 	COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,
452 			RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
453 			RK3568_CLKGATE_CON(35), 9, GFLAGS),
454 	COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
455 			RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
456 			RK3568_CLKGATE_CON(35), 10, GFLAGS),
457 	COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
458 			RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
459 			RK3568_CLKGATE_CON(35), 11, GFLAGS),
460 	COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
461 			RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
462 			RK3568_CLKGATE_CON(35), 12, GFLAGS),
463 	COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
464 			RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
465 			RK3568_CLKGATE_CON(35), 13, GFLAGS),
466 	COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
467 			RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
468 			RK3568_CLKGATE_CON(35), 14, GFLAGS),
469 	COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
470 			RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
471 			RK3568_CLKGATE_CON(35), 15, GFLAGS),
472 	FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2),
473 	FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
474 	MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
475 			RK3568_MODE_CON0, 14, 2, MFLAGS),
476 
477 	/* PD_CORE */
478 	COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
479 			RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
480 			RK3568_CLKGATE_CON(0), 5, GFLAGS),
481 	COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED,
482 			RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
483 			RK3568_CLKGATE_CON(0), 7, GFLAGS),
484 
485 	COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED,
486 			RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
487 			RK3568_CLKGATE_CON(0), 8, GFLAGS),
488 	COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED,
489 			RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
490 			RK3568_CLKGATE_CON(0), 9, GFLAGS),
491 	COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
492 			RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
493 			RK3568_CLKGATE_CON(0), 10, GFLAGS),
494 	COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
495 			RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
496 			RK3568_CLKGATE_CON(0), 11, GFLAGS),
497 	COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
498 			RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
499 			RK3568_CLKGATE_CON(0), 14, GFLAGS),
500 	COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
501 			RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
502 			RK3568_CLKGATE_CON(0), 15, GFLAGS),
503 	COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED,
504 			RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
505 			RK3568_CLKGATE_CON(1), 0, GFLAGS),
506 
507 	COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
508 			RK3568_CLKSEL_CON(5), 14, 2, MFLAGS,
509 			RK3568_CLKGATE_CON(1), 2, GFLAGS),
510 
511 	GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
512 			RK3568_CLKGATE_CON(1), 10, GFLAGS),
513 	GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0,
514 			RK3568_CLKGATE_CON(1), 11, GFLAGS),
515 	GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED,
516 			RK3568_CLKGATE_CON(1), 12, GFLAGS),
517 	GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
518 			RK3568_CLKGATE_CON(1), 9, GFLAGS),
519 
520 	/* PD_GPU */
521 	COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,
522 			RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
523 			RK3568_CLKGATE_CON(2), 0, GFLAGS),
524 	MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT,
525 			RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
526 	DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0,
527 			RK3568_CLKSEL_CON(6), 8, 2, DFLAGS),
528 	DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0,
529 			RK3568_CLKSEL_CON(6), 12, 4, DFLAGS),
530 	GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0,
531 			RK3568_CLKGATE_CON(2), 3, GFLAGS),
532 
533 	GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0,
534 			RK3568_CLKGATE_CON(2), 6, GFLAGS),
535 	GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
536 			RK3568_CLKGATE_CON(2), 7, GFLAGS),
537 	GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0,
538 			RK3568_CLKGATE_CON(2), 8, GFLAGS),
539 	GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED,
540 			RK3568_CLKGATE_CON(2), 9, GFLAGS),
541 
542 	/* PD_NPU */
543 	COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
544 			RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
545 			RK3568_CLKGATE_CON(3), 0, GFLAGS),
546 	MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
547 			RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
548 	MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT,
549 			RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
550 	COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0,
551 			RK3568_CLKSEL_CON(8), 0, 4, DFLAGS,
552 			RK3568_CLKGATE_CON(3), 2, GFLAGS),
553 	COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0,
554 			RK3568_CLKSEL_CON(8), 4, 4, DFLAGS,
555 			RK3568_CLKGATE_CON(3), 3, GFLAGS),
556 	GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
557 			RK3568_CLKGATE_CON(3), 4, GFLAGS),
558 	GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
559 			RK3568_CLKGATE_CON(3), 7, GFLAGS),
560 	GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
561 			RK3568_CLKGATE_CON(3), 8, GFLAGS),
562 
563 	GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0,
564 			RK3568_CLKGATE_CON(3), 9, GFLAGS),
565 	GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
566 			RK3568_CLKGATE_CON(3), 10, GFLAGS),
567 	GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0,
568 			RK3568_CLKGATE_CON(3), 11, GFLAGS),
569 	GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED,
570 			RK3568_CLKGATE_CON(3), 12, GFLAGS),
571 
572 	/* PD_DDR */
573 	COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,
574 			RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
575 			RK3568_CLKGATE_CON(4), 0, GFLAGS),
576 	MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,
577 			RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
578 
579 	COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,
580 			RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
581 			RK3568_CLKGATE_CON(4), 2, GFLAGS),
582 	GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
583 			RK3568_CLKGATE_CON(4), 15, GFLAGS),
584 
585 	/* PD_GIC_AUDIO */
586 	COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
587 			RK3568_CLKSEL_CON(10), 8, 2, MFLAGS,
588 			RK3568_CLKGATE_CON(5), 0, GFLAGS),
589 	COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
590 			RK3568_CLKSEL_CON(10), 10, 2, MFLAGS,
591 			RK3568_CLKGATE_CON(5), 1, GFLAGS),
592 	GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0,
593 			RK3568_CLKGATE_CON(5), 8, GFLAGS),
594 	COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0,
595 			RK3568_CLKSEL_CON(10), 12, 2, MFLAGS,
596 			RK3568_CLKGATE_CON(5), 9, GFLAGS),
597 	GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED,
598 			RK3568_CLKGATE_CON(5), 4, GFLAGS),
599 	GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED,
600 			RK3568_CLKGATE_CON(5), 7, GFLAGS),
601 	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0,
602 			RK3568_CLKGATE_CON(5), 10, GFLAGS),
603 	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0,
604 			RK3568_CLKGATE_CON(5), 11, GFLAGS),
605 	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0,
606 			RK3568_CLKGATE_CON(5), 12, GFLAGS),
607 	GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0,
608 			RK3568_CLKGATE_CON(5), 13, GFLAGS),
609 
610 	COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0,
611 			RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS,
612 			RK3568_CLKGATE_CON(6), 0, GFLAGS),
613 	COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
614 			RK3568_CLKSEL_CON(12), 0,
615 			RK3568_CLKGATE_CON(6), 1, GFLAGS,
616 			&rk3568_i2s0_8ch_tx_fracmux),
617 	GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
618 			RK3568_CLKGATE_CON(6), 2, GFLAGS),
619 	COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT,
620 			RK3568_CLKSEL_CON(11), 15, 1, MFLAGS,
621 			RK3568_CLKGATE_CON(6), 3, GFLAGS),
622 
623 	COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0,
624 			RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS,
625 			RK3568_CLKGATE_CON(6), 4, GFLAGS),
626 	COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
627 			RK3568_CLKSEL_CON(14), 0,
628 			RK3568_CLKGATE_CON(6), 5, GFLAGS,
629 			&rk3568_i2s0_8ch_rx_fracmux),
630 	GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
631 			RK3568_CLKGATE_CON(6), 6, GFLAGS),
632 	COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT,
633 			RK3568_CLKSEL_CON(13), 15, 1, MFLAGS,
634 			RK3568_CLKGATE_CON(6), 7, GFLAGS),
635 
636 	COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0,
637 			RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS,
638 			RK3568_CLKGATE_CON(6), 8, GFLAGS),
639 	COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
640 			RK3568_CLKSEL_CON(16), 0,
641 			RK3568_CLKGATE_CON(6), 9, GFLAGS,
642 			&rk3568_i2s1_8ch_tx_fracmux),
643 	GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
644 			RK3568_CLKGATE_CON(6), 10, GFLAGS),
645 	COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT,
646 			RK3568_CLKSEL_CON(15), 15, 1, MFLAGS,
647 			RK3568_CLKGATE_CON(6), 11, GFLAGS),
648 
649 	COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0,
650 			RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS,
651 			RK3568_CLKGATE_CON(6), 12, GFLAGS),
652 	COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
653 			RK3568_CLKSEL_CON(18), 0,
654 			RK3568_CLKGATE_CON(6), 13, GFLAGS,
655 			&rk3568_i2s1_8ch_rx_fracmux),
656 	GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
657 			RK3568_CLKGATE_CON(6), 14, GFLAGS),
658 	COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT,
659 			RK3568_CLKSEL_CON(17), 15, 1, MFLAGS,
660 			RK3568_CLKGATE_CON(6), 15, GFLAGS),
661 
662 	COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0,
663 			RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS,
664 			RK3568_CLKGATE_CON(7), 0, GFLAGS),
665 	COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
666 			RK3568_CLKSEL_CON(20), 0,
667 			RK3568_CLKGATE_CON(7), 1, GFLAGS,
668 			&rk3568_i2s2_2ch_fracmux),
669 	GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
670 			RK3568_CLKGATE_CON(7), 2, GFLAGS),
671 	COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT,
672 			RK3568_CLKSEL_CON(19), 15, 1, MFLAGS,
673 			RK3568_CLKGATE_CON(7), 3, GFLAGS),
674 
675 	COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0,
676 			RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS,
677 			RK3568_CLKGATE_CON(7), 4, GFLAGS),
678 	COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT,
679 			RK3568_CLKSEL_CON(22), 0,
680 			RK3568_CLKGATE_CON(7), 5, GFLAGS,
681 			&rk3568_i2s3_2ch_tx_fracmux),
682 	GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0,
683 			RK3568_CLKGATE_CON(7), 6, GFLAGS),
684 	COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT,
685 			RK3568_CLKSEL_CON(21), 15, 1, MFLAGS,
686 			RK3568_CLKGATE_CON(7), 7, GFLAGS),
687 
688 	COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0,
689 			RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS,
690 			RK3568_CLKGATE_CON(7), 8, GFLAGS),
691 	COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT,
692 			RK3568_CLKSEL_CON(84), 0,
693 			RK3568_CLKGATE_CON(7), 9, GFLAGS,
694 			&rk3568_i2s3_2ch_rx_fracmux),
695 	GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0,
696 			RK3568_CLKGATE_CON(7), 10, GFLAGS),
697 	COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT,
698 			RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
699 			RK3568_CLKGATE_CON(7), 11, GFLAGS),
700 
701 	GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
702 			RK3568_CLKGATE_CON(5), 14, GFLAGS),
703 	COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
704 			RK3568_CLKSEL_CON(23), 8, 2, MFLAGS,
705 			RK3568_CLKGATE_CON(5), 15, GFLAGS),
706 	GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0,
707 			RK3568_CLKGATE_CON(7), 12, GFLAGS),
708 	GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0,
709 			RK3568_CLKGATE_CON(7), 13, GFLAGS),
710 
711 	COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0,
712 			RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS,
713 			RK3568_CLKGATE_CON(7), 14, GFLAGS),
714 	COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT,
715 			RK3568_CLKSEL_CON(24), 0,
716 			RK3568_CLKGATE_CON(7), 15, GFLAGS,
717 			&rk3568_spdif_8ch_fracmux),
718 
719 	GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0,
720 			RK3568_CLKGATE_CON(8), 0, GFLAGS),
721 	COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0,
722 			RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
723 			RK3568_CLKGATE_CON(8), 1, GFLAGS),
724 	COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT,
725 			RK3568_CLKSEL_CON(26), 0,
726 			RK3568_CLKGATE_CON(8), 2, GFLAGS,
727 			&rk3568_audpwm_fracmux),
728 
729 	GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
730 			RK3568_CLKGATE_CON(8), 3, GFLAGS),
731 	COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0,
732 			RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,
733 			RK3568_CLKGATE_CON(8), 4, GFLAGS),
734 	GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0,
735 			RK3568_CLKGATE_CON(8), 5, GFLAGS),
736 	GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0,
737 			RK3568_CLKGATE_CON(8), 6, GFLAGS),
738 
739 	/* PD_SECURE_FLASH */
740 	COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0,
741 			RK3568_CLKSEL_CON(27), 0, 2, MFLAGS,
742 			RK3568_CLKGATE_CON(8), 7, GFLAGS),
743 	COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0,
744 			RK3568_CLKSEL_CON(27), 2, 2, MFLAGS,
745 			RK3568_CLKGATE_CON(8), 8, GFLAGS),
746 	GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0,
747 			RK3568_CLKGATE_CON(8), 11, GFLAGS),
748 	GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0,
749 			RK3568_CLKGATE_CON(8), 12, GFLAGS),
750 	COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0,
751 			RK3568_CLKSEL_CON(27), 4, 2, MFLAGS,
752 			RK3568_CLKGATE_CON(8), 13, GFLAGS),
753 	COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0,
754 			RK3568_CLKSEL_CON(27), 6, 2, MFLAGS,
755 			RK3568_CLKGATE_CON(8), 14, GFLAGS),
756 	GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0,
757 			RK3568_CLKGATE_CON(8), 15, GFLAGS),
758 	GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
759 			RK3568_CLKGATE_CON(9), 10, GFLAGS),
760 	GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
761 			RK3568_CLKGATE_CON(9), 11, GFLAGS),
762 	GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0,
763 			RK3568_CLKGATE_CON(26), 9, GFLAGS),
764 	GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0,
765 			RK3568_CLKGATE_CON(26), 10, GFLAGS),
766 	GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0,
767 			RK3568_CLKGATE_CON(26), 11, GFLAGS),
768 	GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0,
769 			RK3568_CLKGATE_CON(9), 0, GFLAGS),
770 	COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0,
771 			RK3568_CLKSEL_CON(28), 0, 2, MFLAGS,
772 			RK3568_CLKGATE_CON(9), 1, GFLAGS),
773 	GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0,
774 			RK3568_CLKGATE_CON(9), 2, GFLAGS),
775 	GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0,
776 			RK3568_CLKGATE_CON(9), 3, GFLAGS),
777 	COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0,
778 			RK3568_CLKSEL_CON(28), 4, 3, MFLAGS,
779 			RK3568_CLKGATE_CON(9), 4, GFLAGS),
780 	GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0,
781 			RK3568_CLKGATE_CON(9), 5, GFLAGS),
782 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0,
783 			RK3568_CLKGATE_CON(9), 6, GFLAGS),
784 	COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0,
785 			RK3568_CLKSEL_CON(28), 8, 2, MFLAGS,
786 			RK3568_CLKGATE_CON(9), 7, GFLAGS),
787 	COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0,
788 			RK3568_CLKSEL_CON(28), 12, 3, MFLAGS,
789 			RK3568_CLKGATE_CON(9), 8, GFLAGS),
790 	GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
791 			RK3568_CLKGATE_CON(9), 9, GFLAGS),
792 	MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1),
793 	MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1),
794 
795 	/* PD_PIPE */
796 	COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0,
797 			RK3568_CLKSEL_CON(29), 0, 2, MFLAGS,
798 			RK3568_CLKGATE_CON(10), 0, GFLAGS),
799 	COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0,
800 			RK3568_CLKSEL_CON(29), 4, 4, DFLAGS,
801 			RK3568_CLKGATE_CON(10), 1, GFLAGS),
802 	GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0,
803 			RK3568_CLKGATE_CON(12), 0, GFLAGS),
804 	GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0,
805 			RK3568_CLKGATE_CON(12), 1, GFLAGS),
806 	GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0,
807 			RK3568_CLKGATE_CON(12), 2, GFLAGS),
808 	GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0,
809 			RK3568_CLKGATE_CON(12), 3, GFLAGS),
810 	GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
811 			RK3568_CLKGATE_CON(12), 4, GFLAGS),
812 	GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
813 			RK3568_CLKGATE_CON(12), 8, GFLAGS),
814 	GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
815 			RK3568_CLKGATE_CON(12), 9, GFLAGS),
816 	GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0,
817 			RK3568_CLKGATE_CON(12), 10, GFLAGS),
818 	GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0,
819 			RK3568_CLKGATE_CON(12), 11, GFLAGS),
820 	GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
821 			RK3568_CLKGATE_CON(12), 12, GFLAGS),
822 	GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
823 			RK3568_CLKGATE_CON(13), 0, GFLAGS),
824 	GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
825 			RK3568_CLKGATE_CON(13), 1, GFLAGS),
826 	GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0,
827 			RK3568_CLKGATE_CON(13), 2, GFLAGS),
828 	GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0,
829 			RK3568_CLKGATE_CON(13), 3, GFLAGS),
830 	GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
831 			RK3568_CLKGATE_CON(13), 4, GFLAGS),
832 	GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
833 			RK3568_CLKGATE_CON(11), 0, GFLAGS),
834 	GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
835 			RK3568_CLKGATE_CON(11), 1, GFLAGS),
836 	GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0,
837 			RK3568_CLKGATE_CON(11), 2, GFLAGS),
838 	GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0,
839 			RK3568_CLKGATE_CON(11), 4, GFLAGS),
840 	GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0,
841 			RK3568_CLKGATE_CON(11), 5, GFLAGS),
842 	GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0,
843 			RK3568_CLKGATE_CON(11), 6, GFLAGS),
844 	GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0,
845 			RK3568_CLKGATE_CON(11), 8, GFLAGS),
846 	GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0,
847 			RK3568_CLKGATE_CON(11), 9, GFLAGS),
848 	GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0,
849 			RK3568_CLKGATE_CON(11), 10, GFLAGS),
850 	GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0,
851 			RK3568_CLKGATE_CON(10), 8, GFLAGS),
852 	GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
853 			RK3568_CLKGATE_CON(10), 9, GFLAGS),
854 	COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0,
855 			RK3568_CLKSEL_CON(29), 8, 1, MFLAGS,
856 			RK3568_CLKGATE_CON(10), 10, GFLAGS),
857 	GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0,
858 			RK3568_CLKGATE_CON(10), 12, GFLAGS),
859 	GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
860 			RK3568_CLKGATE_CON(10), 13, GFLAGS),
861 	COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0,
862 			RK3568_CLKSEL_CON(29), 9, 1, MFLAGS,
863 			RK3568_CLKGATE_CON(10), 14, GFLAGS),
864 	COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0,
865 			RK3568_CLKSEL_CON(29), 13, 1, MFLAGS,
866 			RK3568_CLKGATE_CON(10), 4, GFLAGS),
867 	GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0,
868 			RK3568_CLKGATE_CON(13), 6, GFLAGS),
869 
870 	/* PD_PHP */
871 	COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0,
872 			RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
873 			RK3568_CLKGATE_CON(14), 8, GFLAGS),
874 	COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0,
875 			RK3568_CLKSEL_CON(30), 2, 2, MFLAGS,
876 			RK3568_CLKGATE_CON(14), 9, GFLAGS),
877 	COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0,
878 			RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
879 			RK3568_CLKGATE_CON(14), 10, GFLAGS),
880 	GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0,
881 			RK3568_CLKGATE_CON(15), 0, GFLAGS),
882 	COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0,
883 			RK3568_CLKSEL_CON(30), 8, 3, MFLAGS,
884 			RK3568_CLKGATE_CON(15), 1, GFLAGS),
885 	MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1),
886 	MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1),
887 
888 	GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0,
889 			RK3568_CLKGATE_CON(15), 2, GFLAGS),
890 	COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0,
891 			RK3568_CLKSEL_CON(30), 12, 3, MFLAGS,
892 			RK3568_CLKGATE_CON(15), 3, GFLAGS),
893 	MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1),
894 	MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1),
895 
896 	GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0,
897 			RK3568_CLKGATE_CON(15), 5, GFLAGS),
898 	GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0,
899 			RK3568_CLKGATE_CON(15), 6, GFLAGS),
900 	COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0,
901 			RK3568_CLKSEL_CON(31), 8, 2, MFLAGS,
902 			RK3568_CLKGATE_CON(15), 7, GFLAGS),
903 	COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0,
904 			RK3568_CLKSEL_CON(31), 14, 2, MFLAGS,
905 			RK3568_CLKGATE_CON(15), 8, GFLAGS),
906 	GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0,
907 			RK3568_CLKGATE_CON(15), 12, GFLAGS),
908 	COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0,
909 			RK3568_CLKSEL_CON(31), 12, 2, MFLAGS,
910 			RK3568_CLKGATE_CON(15), 4, GFLAGS),
911 	MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
912 			RK3568_CLKSEL_CON(31), 2, 1, MFLAGS),
913 	FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5),
914 	FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50),
915 	FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2),
916 	FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20),
917 	MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0,
918 			RK3568_CLKSEL_CON(31), 4, 2, MFLAGS),
919 	MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0,
920 			RK3568_CLKSEL_CON(31), 3, 1, MFLAGS),
921 	MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p,  CLK_SET_RATE_PARENT,
922 			RK3568_CLKSEL_CON(31), 0, 2, MFLAGS),
923 
924 	/* PD_USB */
925 	COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0,
926 			RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
927 			RK3568_CLKGATE_CON(16), 0, GFLAGS),
928 	COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0,
929 			RK3568_CLKSEL_CON(32), 2, 2, MFLAGS,
930 			RK3568_CLKGATE_CON(16), 1, GFLAGS),
931 	COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0,
932 			RK3568_CLKSEL_CON(32), 4, 4, DFLAGS,
933 			RK3568_CLKGATE_CON(16), 2, GFLAGS),
934 	GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0,
935 			RK3568_CLKGATE_CON(16), 12, GFLAGS),
936 	GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0,
937 			RK3568_CLKGATE_CON(16), 13, GFLAGS),
938 	GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0,
939 			RK3568_CLKGATE_CON(16), 14, GFLAGS),
940 	GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0,
941 			RK3568_CLKGATE_CON(16), 15, GFLAGS),
942 	GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0,
943 			RK3568_CLKGATE_CON(17), 0, GFLAGS),
944 	COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0,
945 			RK3568_CLKSEL_CON(32), 8, 3, MFLAGS,
946 			RK3568_CLKGATE_CON(17), 1, GFLAGS),
947 	MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1),
948 	MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1),
949 
950 	GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0,
951 			RK3568_CLKGATE_CON(17), 3, GFLAGS),
952 	GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0,
953 			RK3568_CLKGATE_CON(17), 4, GFLAGS),
954 	COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0,
955 			RK3568_CLKSEL_CON(33), 8, 2, MFLAGS,
956 			RK3568_CLKGATE_CON(17), 5, GFLAGS),
957 	COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0,
958 			RK3568_CLKSEL_CON(33), 14, 2, MFLAGS,
959 			RK3568_CLKGATE_CON(17), 6, GFLAGS),
960 	GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0,
961 			RK3568_CLKGATE_CON(17), 10, GFLAGS),
962 	COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0,
963 			RK3568_CLKSEL_CON(33), 12, 2, MFLAGS,
964 			RK3568_CLKGATE_CON(17), 2, GFLAGS),
965 	MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
966 			RK3568_CLKSEL_CON(33), 2, 1, MFLAGS),
967 	FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5),
968 	FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50),
969 	FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2),
970 	FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20),
971 	MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0,
972 			RK3568_CLKSEL_CON(33), 4, 2, MFLAGS),
973 	MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0,
974 			RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
975 	MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p,  CLK_SET_RATE_PARENT,
976 			RK3568_CLKSEL_CON(33), 0, 2, MFLAGS),
977 
978 	/* PD_PERI */
979 	COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
980 			RK3568_CLKSEL_CON(10), 4, 2, MFLAGS,
981 			RK3568_CLKGATE_CON(14), 0, GFLAGS),
982 	COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
983 			RK3568_CLKSEL_CON(10), 6, 2, MFLAGS,
984 			RK3568_CLKGATE_CON(14), 1, GFLAGS),
985 
986 	/* PD_VI */
987 	COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0,
988 			RK3568_CLKSEL_CON(34), 0, 2, MFLAGS,
989 			RK3568_CLKGATE_CON(18), 0, GFLAGS),
990 	COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0,
991 			RK3568_CLKSEL_CON(34), 4, 4, DFLAGS,
992 			RK3568_CLKGATE_CON(18), 1, GFLAGS),
993 	COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0,
994 			RK3568_CLKSEL_CON(34), 8, 4, DFLAGS,
995 			RK3568_CLKGATE_CON(18), 2, GFLAGS),
996 	GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0,
997 			RK3568_CLKGATE_CON(18), 9, GFLAGS),
998 	GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
999 			RK3568_CLKGATE_CON(18), 10, GFLAGS),
1000 	COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0,
1001 			RK3568_CLKSEL_CON(34), 14, 2, MFLAGS,
1002 			RK3568_CLKGATE_CON(18), 11, GFLAGS),
1003 	GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0,
1004 			RK3568_CLKGATE_CON(18), 13, GFLAGS),
1005 	GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0,
1006 			RK3568_CLKGATE_CON(19), 0, GFLAGS),
1007 	GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
1008 			RK3568_CLKGATE_CON(19), 1, GFLAGS),
1009 	COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0,
1010 			RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
1011 			RK3568_CLKGATE_CON(19), 2, GFLAGS),
1012 	GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0,
1013 			RK3568_CLKGATE_CON(19), 4, GFLAGS),
1014 	COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0,
1015 			RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
1016 			RK3568_CLKGATE_CON(19), 8, GFLAGS),
1017 	COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0,
1018 			RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
1019 			RK3568_CLKGATE_CON(19), 9, GFLAGS),
1020 	COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0,
1021 			RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS,
1022 			RK3568_CLKGATE_CON(19), 10, GFLAGS),
1023 
1024 	/* PD_VO */
1025 	COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0,
1026 			RK3568_CLKSEL_CON(37), 0, 2, MFLAGS,
1027 			RK3568_CLKGATE_CON(20), 0, GFLAGS),
1028 	COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0,
1029 			RK3568_CLKSEL_CON(37), 8, 4, DFLAGS,
1030 			RK3568_CLKGATE_CON(20), 1, GFLAGS),
1031 	COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0,
1032 			RK3568_CLKSEL_CON(37), 12, 4, DFLAGS,
1033 			RK3568_CLKGATE_CON(20), 2, GFLAGS),
1034 	COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0,
1035 			RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
1036 			RK3568_CLKGATE_CON(20), 6, GFLAGS),
1037 	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0,
1038 			RK3568_CLKGATE_CON(20), 8, GFLAGS),
1039 	GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
1040 			RK3568_CLKGATE_CON(20), 9, GFLAGS),
1041 	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1042 			RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
1043 			RK3568_CLKGATE_CON(20), 10, GFLAGS),
1044 	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1045 			RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
1046 			RK3568_CLKGATE_CON(20), 11, GFLAGS),
1047 	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0,
1048 			RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
1049 			RK3568_CLKGATE_CON(20), 12, GFLAGS),
1050 	GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
1051 			RK3568_CLKGATE_CON(20), 13, GFLAGS),
1052 	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,
1053 			RK3568_CLKGATE_CON(21), 0, GFLAGS),
1054 	GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0,
1055 			RK3568_CLKGATE_CON(21), 1, GFLAGS),
1056 	GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0,
1057 			RK3568_CLKGATE_CON(21), 2, GFLAGS),
1058 	GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0,
1059 			RK3568_CLKGATE_CON(21), 3, GFLAGS),
1060 	GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1061 			RK3568_CLKGATE_CON(21), 4, GFLAGS),
1062 	GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0,
1063 			RK3568_CLKGATE_CON(21), 5, GFLAGS),
1064 	GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0,
1065 			RK3568_CLKGATE_CON(21), 6, GFLAGS),
1066 	GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0,
1067 			RK3568_CLKGATE_CON(21), 7, GFLAGS),
1068 	GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0,
1069 			RK3568_CLKGATE_CON(21), 8, GFLAGS),
1070 	COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0,
1071 			RK3568_CLKSEL_CON(38), 8, 2, MFLAGS,
1072 			RK3568_CLKGATE_CON(21), 9, GFLAGS),
1073 
1074 	/* PD_VPU */
1075 	COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0,
1076 			RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
1077 			RK3568_CLKGATE_CON(22), 0, GFLAGS),
1078 	COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0,
1079 			RK3568_CLKSEL_CON(42), 8, 4, DFLAGS,
1080 			RK3568_CLKGATE_CON(22), 1, GFLAGS),
1081 	GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
1082 			RK3568_CLKGATE_CON(22), 4, GFLAGS),
1083 	GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
1084 			RK3568_CLKGATE_CON(22), 5, GFLAGS),
1085 
1086 	/* PD_RGA */
1087 	COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0,
1088 			RK3568_CLKSEL_CON(43), 0, 2, MFLAGS,
1089 			RK3568_CLKGATE_CON(23), 0, GFLAGS),
1090 	COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0,
1091 			RK3568_CLKSEL_CON(43), 8, 4, DFLAGS,
1092 			RK3568_CLKGATE_CON(23), 1, GFLAGS),
1093 	COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0,
1094 			RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
1095 			RK3568_CLKGATE_CON(22), 12, GFLAGS),
1096 	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
1097 			RK3568_CLKGATE_CON(23), 4, GFLAGS),
1098 	GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
1099 			RK3568_CLKGATE_CON(23), 5, GFLAGS),
1100 	COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0,
1101 			RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
1102 			RK3568_CLKGATE_CON(23), 6, GFLAGS),
1103 	GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0,
1104 			RK3568_CLKGATE_CON(23), 7, GFLAGS),
1105 	GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0,
1106 			RK3568_CLKGATE_CON(23), 8, GFLAGS),
1107 	COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0,
1108 			RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
1109 			RK3568_CLKGATE_CON(23), 9, GFLAGS),
1110 	GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
1111 	COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0,
1112 			RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
1113 			RK3568_CLKGATE_CON(23), 11, GFLAGS),
1114 	GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0,
1115 			RK3568_CLKGATE_CON(23), 12, GFLAGS),
1116 	GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
1117 			RK3568_CLKGATE_CON(23), 13, GFLAGS),
1118 	GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0,
1119 			RK3568_CLKGATE_CON(23), 14, GFLAGS),
1120 	GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0,
1121 			RK3568_CLKGATE_CON(23), 15, GFLAGS),
1122 	GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0,
1123 			RK3568_CLKGATE_CON(22), 14, GFLAGS),
1124 	GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0,
1125 			RK3568_CLKGATE_CON(22), 15, GFLAGS),
1126 
1127 	/* PD_RKVENC */
1128 	COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0,
1129 			RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
1130 			RK3568_CLKGATE_CON(24), 0, GFLAGS),
1131 	COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0,
1132 			RK3568_CLKSEL_CON(44), 8, 4, DFLAGS,
1133 			RK3568_CLKGATE_CON(24), 1, GFLAGS),
1134 	GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
1135 			RK3568_CLKGATE_CON(24), 6, GFLAGS),
1136 	GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
1137 			RK3568_CLKGATE_CON(24), 7, GFLAGS),
1138 	COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0,
1139 			RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS,
1140 			RK3568_CLKGATE_CON(24), 8, GFLAGS),
1141 	COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT,
1142 			RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
1143 			RK3568_CLKGATE_CON(25), 0, GFLAGS),
1144 	COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0,
1145 			RK3568_CLKSEL_CON(47), 8, 4, DFLAGS,
1146 			RK3568_CLKGATE_CON(25), 1, GFLAGS),
1147 	GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
1148 			RK3568_CLKGATE_CON(25), 4, GFLAGS),
1149 	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
1150 			RK3568_CLKGATE_CON(25), 5, GFLAGS),
1151 	COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0,
1152 			RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1153 			RK3568_CLKGATE_CON(25), 6, GFLAGS),
1154 	COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT,
1155 			RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS,
1156 			RK3568_CLKGATE_CON(25), 7, GFLAGS),
1157 	COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0,
1158 			RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
1159 			RK3568_CLKGATE_CON(25), 8, GFLAGS),
1160 
1161 	/* PD_BUS */
1162 	COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0,
1163 			RK3568_CLKSEL_CON(50), 0, 2, MFLAGS,
1164 			RK3568_CLKGATE_CON(26), 0, GFLAGS),
1165 	COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0,
1166 			RK3568_CLKSEL_CON(50), 4, 2, MFLAGS,
1167 			RK3568_CLKGATE_CON(26), 1, GFLAGS),
1168 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
1169 			RK3568_CLKGATE_CON(26), 4, GFLAGS),
1170 	COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0,
1171 			RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS,
1172 			RK3568_CLKGATE_CON(26), 5, GFLAGS),
1173 	COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0,
1174 			RK3568_CLKSEL_CON(51), 8, 7, DFLAGS,
1175 			RK3568_CLKGATE_CON(26), 6, GFLAGS),
1176 	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0,
1177 			RK3568_CLKGATE_CON(26), 7, GFLAGS),
1178 	GATE(CLK_SARADC, "clk_saradc", "xin24m", 0,
1179 			RK3568_CLKGATE_CON(26), 8, GFLAGS),
1180 	GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED,
1181 			RK3568_CLKGATE_CON(26), 12, GFLAGS),
1182 	GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0,
1183 			RK3568_CLKGATE_CON(26), 13, GFLAGS),
1184 	GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
1185 			RK3568_CLKGATE_CON(26), 14, GFLAGS),
1186 	GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED,
1187 			RK3568_CLKGATE_CON(32), 13, GFLAGS),
1188 	GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED,
1189 			RK3568_CLKGATE_CON(32), 14, GFLAGS),
1190 	GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
1191 			RK3568_CLKGATE_CON(32), 15, GFLAGS),
1192 
1193 	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0,
1194 			RK3568_CLKGATE_CON(27), 12, GFLAGS),
1195 	COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0,
1196 			RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
1197 			RK3568_CLKGATE_CON(27), 13, GFLAGS),
1198 	COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
1199 			RK3568_CLKSEL_CON(53), 0,
1200 			RK3568_CLKGATE_CON(27), 14, GFLAGS,
1201 			&rk3568_uart1_fracmux),
1202 	GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
1203 			RK3568_CLKGATE_CON(27), 15, GFLAGS),
1204 
1205 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0,
1206 			RK3568_CLKGATE_CON(28), 0, GFLAGS),
1207 	COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0,
1208 			RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
1209 			RK3568_CLKGATE_CON(28), 1, GFLAGS),
1210 	COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
1211 			RK3568_CLKSEL_CON(55), 0,
1212 			RK3568_CLKGATE_CON(28), 2, GFLAGS,
1213 			&rk3568_uart2_fracmux),
1214 	GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
1215 			RK3568_CLKGATE_CON(28), 3, GFLAGS),
1216 
1217 	GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0,
1218 			RK3568_CLKGATE_CON(28), 4, GFLAGS),
1219 	COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0,
1220 			RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
1221 			RK3568_CLKGATE_CON(28), 5, GFLAGS),
1222 	COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
1223 			RK3568_CLKSEL_CON(57), 0,
1224 			RK3568_CLKGATE_CON(28), 6, GFLAGS,
1225 			&rk3568_uart3_fracmux),
1226 	GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
1227 			RK3568_CLKGATE_CON(28), 7, GFLAGS),
1228 
1229 	GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0,
1230 			RK3568_CLKGATE_CON(28), 8, GFLAGS),
1231 	COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0,
1232 			RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
1233 			RK3568_CLKGATE_CON(28), 9, GFLAGS),
1234 	COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
1235 			RK3568_CLKSEL_CON(59), 0,
1236 			RK3568_CLKGATE_CON(28), 10, GFLAGS,
1237 			&rk3568_uart4_fracmux),
1238 	GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
1239 			RK3568_CLKGATE_CON(28), 11, GFLAGS),
1240 
1241 	GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
1242 			RK3568_CLKGATE_CON(28), 12, GFLAGS),
1243 	COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0,
1244 			RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
1245 			RK3568_CLKGATE_CON(28), 13, GFLAGS),
1246 	COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
1247 			RK3568_CLKSEL_CON(61), 0,
1248 			RK3568_CLKGATE_CON(28), 14, GFLAGS,
1249 			&rk3568_uart5_fracmux),
1250 	GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
1251 			RK3568_CLKGATE_CON(28), 15, GFLAGS),
1252 
1253 	GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0,
1254 			RK3568_CLKGATE_CON(29), 0, GFLAGS),
1255 	COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0,
1256 			RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
1257 			RK3568_CLKGATE_CON(29), 1, GFLAGS),
1258 	COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
1259 			RK3568_CLKSEL_CON(63), 0,
1260 			RK3568_CLKGATE_CON(29), 2, GFLAGS,
1261 			&rk3568_uart6_fracmux),
1262 	GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0,
1263 			RK3568_CLKGATE_CON(29), 3, GFLAGS),
1264 
1265 	GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0,
1266 			RK3568_CLKGATE_CON(29), 4, GFLAGS),
1267 	COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0,
1268 			RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
1269 			RK3568_CLKGATE_CON(29), 5, GFLAGS),
1270 	COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
1271 			RK3568_CLKSEL_CON(65), 0,
1272 			RK3568_CLKGATE_CON(29), 6, GFLAGS,
1273 			&rk3568_uart7_fracmux),
1274 	GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0,
1275 			RK3568_CLKGATE_CON(29), 7, GFLAGS),
1276 
1277 	GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0,
1278 			RK3568_CLKGATE_CON(29), 8, GFLAGS),
1279 	COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0,
1280 			RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
1281 			RK3568_CLKGATE_CON(29), 9, GFLAGS),
1282 	COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
1283 			RK3568_CLKSEL_CON(67), 0,
1284 			RK3568_CLKGATE_CON(29), 10, GFLAGS,
1285 			&rk3568_uart8_fracmux),
1286 	GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0,
1287 			RK3568_CLKGATE_CON(29), 11, GFLAGS),
1288 
1289 	GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0,
1290 			RK3568_CLKGATE_CON(29), 12, GFLAGS),
1291 	COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0,
1292 			RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
1293 			RK3568_CLKGATE_CON(29), 13, GFLAGS),
1294 	COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
1295 			RK3568_CLKSEL_CON(69), 0,
1296 			RK3568_CLKGATE_CON(29), 14, GFLAGS,
1297 			&rk3568_uart9_fracmux),
1298 	GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0,
1299 			RK3568_CLKGATE_CON(29), 15, GFLAGS),
1300 
1301 	GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0,
1302 			RK3568_CLKGATE_CON(27), 5, GFLAGS),
1303 	COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
1304 			RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
1305 			RK3568_CLKGATE_CON(27), 6, GFLAGS),
1306 	GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0,
1307 			RK3568_CLKGATE_CON(27), 7, GFLAGS),
1308 	COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
1309 			RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
1310 			RK3568_CLKGATE_CON(27), 8, GFLAGS),
1311 	GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0,
1312 			RK3568_CLKGATE_CON(27), 9, GFLAGS),
1313 	COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
1314 			RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
1315 			RK3568_CLKGATE_CON(27), 10, GFLAGS),
1316 	COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0,
1317 			RK3568_CLKSEL_CON(71), 8, 2, MFLAGS,
1318 			RK3568_CLKGATE_CON(32), 10, GFLAGS),
1319 	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
1320 			RK3568_CLKGATE_CON(30), 0, GFLAGS),
1321 	GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
1322 			RK3568_CLKGATE_CON(30), 1, GFLAGS),
1323 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
1324 			RK3568_CLKGATE_CON(30), 2, GFLAGS),
1325 	GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
1326 			RK3568_CLKGATE_CON(30), 3, GFLAGS),
1327 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
1328 			RK3568_CLKGATE_CON(30), 4, GFLAGS),
1329 	GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
1330 			RK3568_CLKGATE_CON(30), 5, GFLAGS),
1331 	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
1332 			RK3568_CLKGATE_CON(30), 6, GFLAGS),
1333 	GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
1334 			RK3568_CLKGATE_CON(30), 7, GFLAGS),
1335 	GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
1336 			RK3568_CLKGATE_CON(30), 8, GFLAGS),
1337 	GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
1338 			RK3568_CLKGATE_CON(30), 9, GFLAGS),
1339 	GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0,
1340 			RK3568_CLKGATE_CON(30), 10, GFLAGS),
1341 	COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0,
1342 			RK3568_CLKSEL_CON(72), 0, 1, MFLAGS,
1343 			RK3568_CLKGATE_CON(30), 11, GFLAGS),
1344 	GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0,
1345 			RK3568_CLKGATE_CON(30), 12, GFLAGS),
1346 	COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0,
1347 			RK3568_CLKSEL_CON(72), 2, 1, MFLAGS,
1348 			RK3568_CLKGATE_CON(30), 13, GFLAGS),
1349 	GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0,
1350 			RK3568_CLKGATE_CON(30), 14, GFLAGS),
1351 	COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0,
1352 			RK3568_CLKSEL_CON(72), 4, 1, MFLAGS,
1353 			RK3568_CLKGATE_CON(30), 15, GFLAGS),
1354 	GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0,
1355 			RK3568_CLKGATE_CON(31), 0, GFLAGS),
1356 	COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0,
1357 			RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS),
1358 	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
1359 	COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,
1360 			RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
1361 			RK3568_CLKGATE_CON(31), 11, GFLAGS),
1362 	GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1363 			RK3568_CLKGATE_CON(31), 12, GFLAGS),
1364 	GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
1365 			RK3568_CLKGATE_CON(31), 13, GFLAGS),
1366 	COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0,
1367 			RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
1368 			RK3568_CLKGATE_CON(31), 14, GFLAGS),
1369 	GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1370 			RK3568_CLKGATE_CON(31), 15, GFLAGS),
1371 	GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
1372 			RK3568_CLKGATE_CON(32), 0, GFLAGS),
1373 	COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0,
1374 			RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
1375 			RK3568_CLKGATE_CON(32), 1, GFLAGS),
1376 	GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1377 			RK3568_CLKGATE_CON(32), 2, GFLAGS),
1378 	COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0,
1379 			RK3568_CLKSEL_CON(72), 14, 1, MFLAGS,
1380 			RK3568_CLKGATE_CON(32), 11, GFLAGS),
1381 	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0,
1382 			RK3568_CLKGATE_CON(31), 2, GFLAGS),
1383 	GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0,
1384 			RK3568_CLKGATE_CON(31), 3, GFLAGS),
1385 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0,
1386 			RK3568_CLKGATE_CON(31), 4, GFLAGS),
1387 	GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0,
1388 			RK3568_CLKGATE_CON(31), 5, GFLAGS),
1389 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0,
1390 			RK3568_CLKGATE_CON(31), 6, GFLAGS),
1391 	GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0,
1392 			RK3568_CLKGATE_CON(31), 7, GFLAGS),
1393 	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0,
1394 			RK3568_CLKGATE_CON(31), 8, GFLAGS),
1395 	GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0,
1396 			RK3568_CLKGATE_CON(31), 9, GFLAGS),
1397 	GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
1398 			RK3568_CLKGATE_CON(32), 3, GFLAGS),
1399 	GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
1400 			RK3568_CLKGATE_CON(32), 4, GFLAGS),
1401 	GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
1402 			RK3568_CLKGATE_CON(32), 5, GFLAGS),
1403 	GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
1404 			RK3568_CLKGATE_CON(32), 6, GFLAGS),
1405 	GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
1406 			RK3568_CLKGATE_CON(32), 7, GFLAGS),
1407 	GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
1408 			RK3568_CLKGATE_CON(32), 8, GFLAGS),
1409 	GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
1410 			RK3568_CLKGATE_CON(32), 9, GFLAGS),
1411 
1412 	/* PD_TOP */
1413 	COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0,
1414 			RK3568_CLKSEL_CON(73), 0, 2, MFLAGS,
1415 			RK3568_CLKGATE_CON(33), 0, GFLAGS),
1416 	COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0,
1417 			RK3568_CLKSEL_CON(73), 4, 2, MFLAGS,
1418 			RK3568_CLKGATE_CON(33), 1, GFLAGS),
1419 	COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0,
1420 			RK3568_CLKSEL_CON(73), 8, 2, MFLAGS,
1421 			RK3568_CLKGATE_CON(33), 2, GFLAGS),
1422 	COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0,
1423 			RK3568_CLKSEL_CON(73), 12, 2, MFLAGS,
1424 			RK3568_CLKGATE_CON(33), 3, GFLAGS),
1425 	GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0,
1426 			RK3568_CLKGATE_CON(33), 8, GFLAGS),
1427 	COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0,
1428 			RK3568_CLKSEL_CON(73), 15, 1, MFLAGS,
1429 			RK3568_CLKGATE_CON(33), 9, GFLAGS),
1430 	GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0,
1431 			RK3568_CLKGATE_CON(33), 13, GFLAGS),
1432 	GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0,
1433 			RK3568_CLKGATE_CON(33), 14, GFLAGS),
1434 	GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0,
1435 			RK3568_CLKGATE_CON(33), 15, GFLAGS),
1436 	GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,
1437 			RK3568_CLKGATE_CON(34), 4, GFLAGS),
1438 	GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0,
1439 			RK3568_CLKGATE_CON(34), 5, GFLAGS),
1440 	GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0,
1441 			RK3568_CLKGATE_CON(34), 6, GFLAGS),
1442 	GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0,
1443 			RK3568_CLKGATE_CON(34), 11, GFLAGS),
1444 	GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0,
1445 			RK3568_CLKGATE_CON(34), 12, GFLAGS),
1446 	GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0,
1447 			RK3568_CLKGATE_CON(34), 13, GFLAGS),
1448 	GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0,
1449 			RK3568_CLKGATE_CON(34), 14, GFLAGS),
1450 };
1451 
1452 static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
1453 	/* PD_PMU */
1454 	FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
1455 	FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
1456 	FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2),
1457 
1458 	MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0,
1459 			RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
1460 	COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0,
1461 			RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
1462 			RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
1463 	GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0,
1464 			RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
1465 	GATE(CLK_PMU, "clk_pmu", "xin24m", 0,
1466 			RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
1467 	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
1468 			RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
1469 	COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0,
1470 			RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1471 			RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS),
1472 	GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0,
1473 			RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS),
1474 
1475 	COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
1476 			RK3568_PMU_CLKSEL_CON(1), 0,
1477 			RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS,
1478 			&rk3568_rtc32k_pmu_fracmux),
1479 
1480 	COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED,
1481 			RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
1482 			RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS),
1483 
1484 	COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0,
1485 			RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
1486 			RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
1487 	COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
1488 			RK3568_PMU_CLKSEL_CON(5), 0,
1489 			RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
1490 			&rk3568_uart0_fracmux),
1491 	GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
1492 			RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
1493 
1494 	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
1495 			RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS),
1496 	COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0,
1497 			RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS,
1498 			RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS),
1499 	GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
1500 			RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS),
1501 	COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0,
1502 			RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
1503 			RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS),
1504 	GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0,
1505 			RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS),
1506 	GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
1507 			RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS),
1508 	GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
1509 			RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS),
1510 	GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
1511 			RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS),
1512 	COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0,
1513 			RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
1514 			RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS),
1515 	GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0,
1516 			RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS),
1517 	MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0,
1518 			RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
1519 	GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0,
1520 			RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS),
1521 	MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0,
1522 			RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
1523 	GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0,
1524 			RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS),
1525 	MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0,
1526 			RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
1527 	GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0,
1528 			RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS),
1529 	MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0,
1530 			RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
1531 	COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0,
1532 			RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS,
1533 			RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS),
1534 	GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
1535 			RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS),
1536 	MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT,
1537 			RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
1538 	COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0,
1539 			RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,
1540 			RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS),
1541 	GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0,
1542 			RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS),
1543 	MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,
1544 			RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS),
1545 	COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0,
1546 			RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS,
1547 			RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS),
1548 	GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0,
1549 			RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS),
1550 	MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT,
1551 			RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS),
1552 	COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0,
1553 			RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS,
1554 			RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS),
1555 	GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0,
1556 			RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS),
1557 	MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT,
1558 			RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS),
1559 	GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0,
1560 			RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),
1561 	GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0,
1562 			RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
1563 	GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
1564 			RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
1565 	MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0,
1566 			RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
1567 };
1568 
1569 static const char *const rk3568_cru_critical_clocks[] __initconst = {
1570 	"armclk",
1571 	"pclk_core_pre",
1572 	"aclk_bus",
1573 	"pclk_bus",
1574 	"aclk_top_high",
1575 	"aclk_top_low",
1576 	"hclk_top",
1577 	"pclk_top",
1578 	"aclk_perimid",
1579 	"hclk_perimid",
1580 	"aclk_secure_flash",
1581 	"hclk_secure_flash",
1582 	"aclk_core_niu2bus",
1583 	"npll",
1584 	"clk_optc_arb",
1585 	"hclk_php",
1586 	"pclk_php",
1587 	"hclk_usb",
1588 };
1589 
1590 static const char *const rk3568_pmucru_critical_clocks[] __initconst = {
1591 	"pclk_pdpmu",
1592 	"pclk_pmu",
1593 	"clk_pmu",
1594 };
1595 
1596 static void __init rk3568_pmu_clk_init(struct device_node *np)
1597 {
1598 	struct rockchip_clk_provider *ctx;
1599 	void __iomem *reg_base;
1600 
1601 	reg_base = of_iomap(np, 0);
1602 	if (!reg_base) {
1603 		pr_err("%s: could not map cru pmu region\n", __func__);
1604 		return;
1605 	}
1606 
1607 	ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1608 	if (IS_ERR(ctx)) {
1609 		pr_err("%s: rockchip pmu clk init failed\n", __func__);
1610 		return;
1611 	}
1612 
1613 	rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks,
1614 				   ARRAY_SIZE(rk3568_pmu_pll_clks),
1615 				   RK3568_GRF_SOC_STATUS0);
1616 
1617 	rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches,
1618 				       ARRAY_SIZE(rk3568_clk_pmu_branches));
1619 
1620 	rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0),
1621 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
1622 
1623 	rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks,
1624 				      ARRAY_SIZE(rk3568_pmucru_critical_clocks));
1625 
1626 	rockchip_clk_of_add_provider(np, ctx);
1627 }
1628 
1629 CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
1630 
1631 static void __init rk3568_clk_init(struct device_node *np)
1632 {
1633 	struct rockchip_clk_provider *ctx;
1634 	void __iomem *reg_base;
1635 
1636 	reg_base = of_iomap(np, 0);
1637 	if (!reg_base) {
1638 		pr_err("%s: could not map cru region\n", __func__);
1639 		return;
1640 	}
1641 
1642 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1643 	if (IS_ERR(ctx)) {
1644 		pr_err("%s: rockchip clk init failed\n", __func__);
1645 		iounmap(reg_base);
1646 		return;
1647 	}
1648 
1649 	rockchip_clk_register_plls(ctx, rk3568_pll_clks,
1650 				   ARRAY_SIZE(rk3568_pll_clks),
1651 				   RK3568_GRF_SOC_STATUS0);
1652 
1653 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1654 				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1655 				     &rk3568_cpuclk_data, rk3568_cpuclk_rates,
1656 				     ARRAY_SIZE(rk3568_cpuclk_rates));
1657 
1658 	rockchip_clk_register_branches(ctx, rk3568_clk_branches,
1659 				       ARRAY_SIZE(rk3568_clk_branches));
1660 
1661 	rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0),
1662 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
1663 
1664 	rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL);
1665 
1666 	rockchip_clk_protect_critical(rk3568_cru_critical_clocks,
1667 				      ARRAY_SIZE(rk3568_cru_critical_clocks));
1668 
1669 	rockchip_clk_of_add_provider(np, ctx);
1670 }
1671 
1672 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
1673 
1674 struct clk_rk3568_inits {
1675 	void (*inits)(struct device_node *np);
1676 };
1677 
1678 static const struct clk_rk3568_inits clk_rk3568_pmucru_init = {
1679 	.inits = rk3568_pmu_clk_init,
1680 };
1681 
1682 static const struct clk_rk3568_inits clk_3568_cru_init = {
1683 	.inits = rk3568_clk_init,
1684 };
1685 
1686 static const struct of_device_id clk_rk3568_match_table[] = {
1687 	{
1688 		.compatible = "rockchip,rk3568-cru",
1689 		.data = &clk_3568_cru_init,
1690 	},  {
1691 		.compatible = "rockchip,rk3568-pmucru",
1692 		.data = &clk_rk3568_pmucru_init,
1693 	},
1694 	{ }
1695 };
1696 MODULE_DEVICE_TABLE(of, clk_rk3568_match_table);
1697 
1698 static int __init clk_rk3568_probe(struct platform_device *pdev)
1699 {
1700 	struct device_node *np = pdev->dev.of_node;
1701 	const struct of_device_id *match;
1702 	const struct clk_rk3568_inits *init_data;
1703 
1704 	match = of_match_device(clk_rk3568_match_table, &pdev->dev);
1705 	if (!match || !match->data)
1706 		return -EINVAL;
1707 
1708 	init_data = match->data;
1709 	if (init_data->inits)
1710 		init_data->inits(np);
1711 
1712 	return 0;
1713 }
1714 
1715 static struct platform_driver clk_rk3568_driver = {
1716 	.driver		= {
1717 		.name	= "clk-rk3568",
1718 		.of_match_table = clk_rk3568_match_table,
1719 		.suppress_bind_attrs = true,
1720 	},
1721 };
1722 builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
1723 
1724 MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver");
1725 MODULE_LICENSE("GPL");
1726