1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Xing Zheng <zhengxing@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 #include "clk.h" 23 24 enum rk3399_plls { 25 lpll, bpll, dpll, cpll, gpll, npll, vpll, 26 }; 27 28 enum rk3399_pmu_plls { 29 ppll, 30 }; 31 32 static struct rockchip_pll_rate_table rk3399_pll_rates[] = { 33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 80 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), 81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 90 RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), 91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 95 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 96 RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), 97 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 98 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 99 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 100 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 101 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), 102 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 103 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), 104 RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), 105 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 106 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), 107 RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), 108 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), 109 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), 110 { /* sentinel */ }, 111 }; 112 113 /* CRU parents */ 114 PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 115 116 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src", 117 "clk_core_l_bpll_src", 118 "clk_core_l_dpll_src", 119 "clk_core_l_gpll_src" }; 120 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", 121 "clk_core_b_bpll_src", 122 "clk_core_b_dpll_src", 123 "clk_core_b_gpll_src" }; 124 PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", 125 "clk_ddrc_bpll_src", 126 "clk_ddrc_dpll_src", 127 "clk_ddrc_gpll_src" }; 128 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", 129 "gpll_aclk_cci_src", 130 "npll_aclk_cci_src", 131 "vpll_aclk_cci_src" }; 132 PNAME(mux_cci_trace_p) = { "cpll_cci_trace", 133 "gpll_cci_trace" }; 134 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", 135 "npll_cs"}; 136 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", 137 "gpll_aclk_perihp_src" }; 138 139 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 140 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; 141 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" }; 142 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" }; 143 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; 144 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", 145 "ppll" }; 146 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", 147 "xin24m" }; 148 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", 149 "clk_usbphy_480m" }; 150 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", 151 "npll", "upll" }; 152 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", 153 "upll", "xin24m" }; 154 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", 155 "ppll", "upll", "xin24m" }; 156 157 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; 158 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", 159 "npll" }; 160 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", 161 "xin24m" }; 162 163 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", 164 "dclk_vop0_frac" }; 165 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", 166 "dclk_vop1_frac" }; 167 168 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" }; 169 170 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; 171 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; 172 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", 173 "cpll", "gpll" }; 174 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", 175 "clk_pcie_core_phy" }; 176 177 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", 178 "gpll_aclk_emmc_src" }; 179 180 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", 181 "gpll_aclk_perilp0_src" }; 182 183 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", 184 "gpll_fclk_cm0s_src" }; 185 186 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", 187 "gpll_hclk_perilp1_src" }; 188 189 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; 190 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; 191 192 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", 193 "clk_usbphy1_480m_src" }; 194 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", 195 "gpll_aclk_gmac_src" }; 196 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; 197 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", 198 "clkin_i2s", "xin12m" }; 199 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", 200 "clkin_i2s", "xin12m" }; 201 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", 202 "clkin_i2s", "xin12m" }; 203 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", 204 "clkin_i2s", "xin12m" }; 205 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", 206 "clk_i2s2" }; 207 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; 208 209 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 210 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 211 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 212 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 213 214 /* PMU CRU parents */ 215 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; 216 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 217 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; 218 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; 219 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", 220 "xin24m" }; 221 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; 222 223 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { 224 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), 225 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates), 226 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8), 227 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates), 228 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), 229 RK3399_PLL_CON(19), 8, 31, 0, NULL), 230 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), 231 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 232 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), 233 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 234 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), 235 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 236 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), 237 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 238 }; 239 240 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { 241 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0), 242 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 243 }; 244 245 #define MFLAGS CLK_MUX_HIWORD_MASK 246 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 247 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 248 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 249 250 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata = 251 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, 252 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS); 253 254 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata = 255 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, 256 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS); 257 258 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata = 259 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, 260 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS); 261 262 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata = 263 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, 264 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS); 265 266 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata = 267 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 268 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS); 269 270 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata = 271 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 272 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS); 273 274 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata = 275 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 276 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS); 277 278 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata = 279 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, 280 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS); 281 282 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = 283 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT, 284 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); 285 286 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = 287 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, 288 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); 289 290 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = 291 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT, 292 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS); 293 294 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata = 295 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, 296 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS); 297 298 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = { 299 .core_reg = RK3399_CLKSEL_CON(0), 300 .div_core_shift = 0, 301 .div_core_mask = 0x1f, 302 .mux_core_alt = 3, 303 .mux_core_main = 0, 304 .mux_core_shift = 6, 305 .mux_core_mask = 0x3, 306 }; 307 308 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { 309 .core_reg = RK3399_CLKSEL_CON(2), 310 .div_core_shift = 0, 311 .div_core_mask = 0x1f, 312 .mux_core_alt = 3, 313 .mux_core_main = 1, 314 .mux_core_shift = 6, 315 .mux_core_mask = 0x3, 316 }; 317 318 #define RK3399_DIV_ACLKM_MASK 0x1f 319 #define RK3399_DIV_ACLKM_SHIFT 8 320 #define RK3399_DIV_ATCLK_MASK 0x1f 321 #define RK3399_DIV_ATCLK_SHIFT 0 322 #define RK3399_DIV_PCLK_DBG_MASK 0x1f 323 #define RK3399_DIV_PCLK_DBG_SHIFT 8 324 325 #define RK3399_CLKSEL0(_offs, _aclkm) \ 326 { \ 327 .reg = RK3399_CLKSEL_CON(0 + _offs), \ 328 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \ 329 RK3399_DIV_ACLKM_SHIFT), \ 330 } 331 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \ 332 { \ 333 .reg = RK3399_CLKSEL_CON(1 + _offs), \ 334 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \ 335 RK3399_DIV_ATCLK_SHIFT) | \ 336 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \ 337 RK3399_DIV_PCLK_DBG_SHIFT), \ 338 } 339 340 /* cluster_l: aclkm in clksel0, rest in clksel1 */ 341 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \ 342 { \ 343 .prate = _prate##U, \ 344 .divs = { \ 345 RK3399_CLKSEL0(0, _aclkm), \ 346 RK3399_CLKSEL1(0, _atclk, _pdbg), \ 347 }, \ 348 } 349 350 /* cluster_b: aclkm in clksel2, rest in clksel3 */ 351 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \ 352 { \ 353 .prate = _prate##U, \ 354 .divs = { \ 355 RK3399_CLKSEL0(2, _aclkm), \ 356 RK3399_CLKSEL1(2, _atclk, _pdbg), \ 357 }, \ 358 } 359 360 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { 361 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), 362 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), 363 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), 364 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), 365 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), 366 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6), 367 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), 368 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5), 369 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4), 370 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3), 371 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3), 372 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2), 373 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1), 374 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1), 375 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1), 376 }; 377 378 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { 379 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), 380 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), 381 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), 382 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), 383 RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9), 384 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), 385 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), 386 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8), 387 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), 388 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7), 389 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), 390 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6), 391 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), 392 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5), 393 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), 394 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4), 395 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3), 396 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3), 397 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2), 398 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1), 399 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1), 400 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1), 401 }; 402 403 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 404 /* 405 * CRU Clock-Architecture 406 */ 407 408 /* usbphy */ 409 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED, 410 RK3399_CLKGATE_CON(6), 5, GFLAGS), 411 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED, 412 RK3399_CLKGATE_CON(6), 6, GFLAGS), 413 414 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0, 415 RK3399_CLKGATE_CON(13), 12, GFLAGS), 416 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0, 417 RK3399_CLKGATE_CON(13), 12, GFLAGS), 418 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0, 419 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS), 420 421 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0, 422 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS), 423 424 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0, 425 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS, 426 RK3399_CLKGATE_CON(6), 4, GFLAGS), 427 428 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0, 429 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, 430 RK3399_CLKGATE_CON(12), 0, GFLAGS), 431 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED, 432 RK3399_CLKGATE_CON(30), 0, GFLAGS), 433 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0, 434 RK3399_CLKGATE_CON(30), 1, GFLAGS), 435 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0, 436 RK3399_CLKGATE_CON(30), 2, GFLAGS), 437 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0, 438 RK3399_CLKGATE_CON(30), 3, GFLAGS), 439 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0, 440 RK3399_CLKGATE_CON(30), 4, GFLAGS), 441 442 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, 443 RK3399_CLKGATE_CON(12), 1, GFLAGS), 444 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, 445 RK3399_CLKGATE_CON(12), 2, GFLAGS), 446 447 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0, 448 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS, 449 RK3399_CLKGATE_CON(12), 3, GFLAGS), 450 451 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0, 452 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS, 453 RK3399_CLKGATE_CON(12), 4, GFLAGS), 454 455 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0, 456 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS, 457 RK3399_CLKGATE_CON(13), 4, GFLAGS), 458 459 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, 460 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS, 461 RK3399_CLKGATE_CON(13), 5, GFLAGS), 462 463 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0, 464 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS, 465 RK3399_CLKGATE_CON(13), 6, GFLAGS), 466 467 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, 468 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS, 469 RK3399_CLKGATE_CON(13), 7, GFLAGS), 470 471 /* little core */ 472 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED, 473 RK3399_CLKGATE_CON(0), 0, GFLAGS), 474 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED, 475 RK3399_CLKGATE_CON(0), 1, GFLAGS), 476 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED, 477 RK3399_CLKGATE_CON(0), 2, GFLAGS), 478 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED, 479 RK3399_CLKGATE_CON(0), 3, GFLAGS), 480 481 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED, 482 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 483 RK3399_CLKGATE_CON(0), 4, GFLAGS), 484 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED, 485 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 486 RK3399_CLKGATE_CON(0), 5, GFLAGS), 487 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED, 488 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 489 RK3399_CLKGATE_CON(0), 6, GFLAGS), 490 491 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED, 492 RK3399_CLKGATE_CON(14), 12, GFLAGS), 493 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, 494 RK3399_CLKGATE_CON(14), 13, GFLAGS), 495 496 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, 497 RK3399_CLKGATE_CON(14), 9, GFLAGS), 498 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED, 499 RK3399_CLKGATE_CON(14), 10, GFLAGS), 500 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED, 501 RK3399_CLKGATE_CON(14), 11, GFLAGS), 502 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 503 RK3399_CLKGATE_CON(0), 7, GFLAGS), 504 505 /* big core */ 506 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED, 507 RK3399_CLKGATE_CON(1), 0, GFLAGS), 508 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED, 509 RK3399_CLKGATE_CON(1), 1, GFLAGS), 510 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED, 511 RK3399_CLKGATE_CON(1), 2, GFLAGS), 512 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED, 513 RK3399_CLKGATE_CON(1), 3, GFLAGS), 514 515 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED, 516 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 517 RK3399_CLKGATE_CON(1), 4, GFLAGS), 518 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED, 519 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 520 RK3399_CLKGATE_CON(1), 5, GFLAGS), 521 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED, 522 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 523 RK3399_CLKGATE_CON(1), 6, GFLAGS), 524 525 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED, 526 RK3399_CLKGATE_CON(14), 5, GFLAGS), 527 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, 528 RK3399_CLKGATE_CON(14), 6, GFLAGS), 529 530 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, 531 RK3399_CLKGATE_CON(14), 1, GFLAGS), 532 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED, 533 RK3399_CLKGATE_CON(14), 3, GFLAGS), 534 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED, 535 RK3399_CLKGATE_CON(14), 4, GFLAGS), 536 537 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 538 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY), 539 540 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 541 RK3399_CLKGATE_CON(14), 2, GFLAGS), 542 543 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0, 544 RK3399_CLKGATE_CON(1), 7, GFLAGS), 545 546 /* gmac */ 547 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED, 548 RK3399_CLKGATE_CON(6), 9, GFLAGS), 549 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED, 550 RK3399_CLKGATE_CON(6), 8, GFLAGS), 551 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0, 552 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS, 553 RK3399_CLKGATE_CON(6), 10, GFLAGS), 554 555 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, 556 RK3399_CLKGATE_CON(32), 0, GFLAGS), 557 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 558 RK3399_CLKGATE_CON(32), 1, GFLAGS), 559 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0, 560 RK3399_CLKGATE_CON(32), 4, GFLAGS), 561 562 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, 563 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS, 564 RK3399_CLKGATE_CON(6), 11, GFLAGS), 565 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, 566 RK3399_CLKGATE_CON(32), 2, GFLAGS), 567 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED, 568 RK3399_CLKGATE_CON(32), 3, GFLAGS), 569 570 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0, 571 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, 572 RK3399_CLKGATE_CON(5), 5, GFLAGS), 573 574 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT, 575 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS), 576 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0, 577 RK3399_CLKGATE_CON(5), 6, GFLAGS), 578 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0, 579 RK3399_CLKGATE_CON(5), 7, GFLAGS), 580 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0, 581 RK3399_CLKGATE_CON(5), 8, GFLAGS), 582 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0, 583 RK3399_CLKGATE_CON(5), 9, GFLAGS), 584 585 /* spdif */ 586 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, 587 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, 588 RK3399_CLKGATE_CON(8), 13, GFLAGS), 589 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0, 590 RK3399_CLKSEL_CON(99), 0, 591 RK3399_CLKGATE_CON(8), 14, GFLAGS, 592 &rk3399_spdif_fracmux), 593 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT, 594 RK3399_CLKGATE_CON(8), 15, GFLAGS), 595 596 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, 597 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, 598 RK3399_CLKGATE_CON(10), 6, GFLAGS), 599 /* i2s */ 600 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, 601 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, 602 RK3399_CLKGATE_CON(8), 3, GFLAGS), 603 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0, 604 RK3399_CLKSEL_CON(96), 0, 605 RK3399_CLKGATE_CON(8), 4, GFLAGS, 606 &rk3399_i2s0_fracmux), 607 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT, 608 RK3399_CLKGATE_CON(8), 5, GFLAGS), 609 610 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, 611 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, 612 RK3399_CLKGATE_CON(8), 6, GFLAGS), 613 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0, 614 RK3399_CLKSEL_CON(97), 0, 615 RK3399_CLKGATE_CON(8), 7, GFLAGS, 616 &rk3399_i2s1_fracmux), 617 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, 618 RK3399_CLKGATE_CON(8), 8, GFLAGS), 619 620 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, 621 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, 622 RK3399_CLKGATE_CON(8), 9, GFLAGS), 623 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0, 624 RK3399_CLKSEL_CON(98), 0, 625 RK3399_CLKGATE_CON(8), 10, GFLAGS, 626 &rk3399_i2s2_fracmux), 627 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, 628 RK3399_CLKGATE_CON(8), 11, GFLAGS), 629 630 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, 631 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), 632 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, 633 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS, 634 RK3399_CLKGATE_CON(8), 12, GFLAGS), 635 636 /* uart */ 637 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0, 638 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS), 639 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, 640 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, 641 RK3399_CLKGATE_CON(9), 0, GFLAGS), 642 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0, 643 RK3399_CLKSEL_CON(100), 0, 644 RK3399_CLKGATE_CON(9), 1, GFLAGS, 645 &rk3399_uart0_fracmux), 646 647 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0, 648 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS), 649 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, 650 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, 651 RK3399_CLKGATE_CON(9), 2, GFLAGS), 652 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0, 653 RK3399_CLKSEL_CON(101), 0, 654 RK3399_CLKGATE_CON(9), 3, GFLAGS, 655 &rk3399_uart1_fracmux), 656 657 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, 658 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, 659 RK3399_CLKGATE_CON(9), 4, GFLAGS), 660 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0, 661 RK3399_CLKSEL_CON(102), 0, 662 RK3399_CLKGATE_CON(9), 5, GFLAGS, 663 &rk3399_uart2_fracmux), 664 665 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, 666 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, 667 RK3399_CLKGATE_CON(9), 6, GFLAGS), 668 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0, 669 RK3399_CLKSEL_CON(103), 0, 670 RK3399_CLKGATE_CON(9), 7, GFLAGS, 671 &rk3399_uart3_fracmux), 672 673 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 674 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, 675 RK3399_CLKGATE_CON(3), 4, GFLAGS), 676 677 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED, 678 RK3399_CLKGATE_CON(18), 10, GFLAGS), 679 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0, 680 RK3399_CLKGATE_CON(18), 12, GFLAGS), 681 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED, 682 RK3399_CLKGATE_CON(18), 15, GFLAGS), 683 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED, 684 RK3399_CLKGATE_CON(19), 2, GFLAGS), 685 686 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0, 687 RK3399_CLKGATE_CON(4), 11, GFLAGS), 688 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0, 689 RK3399_CLKGATE_CON(3), 5, GFLAGS), 690 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0, 691 RK3399_CLKGATE_CON(3), 6, GFLAGS), 692 693 /* cci */ 694 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED, 695 RK3399_CLKGATE_CON(2), 0, GFLAGS), 696 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED, 697 RK3399_CLKGATE_CON(2), 1, GFLAGS), 698 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED, 699 RK3399_CLKGATE_CON(2), 2, GFLAGS), 700 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED, 701 RK3399_CLKGATE_CON(2), 3, GFLAGS), 702 703 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED, 704 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, 705 RK3399_CLKGATE_CON(2), 4, GFLAGS), 706 707 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, 708 RK3399_CLKGATE_CON(15), 0, GFLAGS), 709 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, 710 RK3399_CLKGATE_CON(15), 1, GFLAGS), 711 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, 712 RK3399_CLKGATE_CON(15), 2, GFLAGS), 713 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED, 714 RK3399_CLKGATE_CON(15), 3, GFLAGS), 715 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED, 716 RK3399_CLKGATE_CON(15), 4, GFLAGS), 717 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED, 718 RK3399_CLKGATE_CON(15), 7, GFLAGS), 719 720 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED, 721 RK3399_CLKGATE_CON(2), 5, GFLAGS), 722 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED, 723 RK3399_CLKGATE_CON(2), 6, GFLAGS), 724 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED, 725 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS, 726 RK3399_CLKGATE_CON(2), 7, GFLAGS), 727 728 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED, 729 RK3399_CLKGATE_CON(2), 8, GFLAGS), 730 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED, 731 RK3399_CLKGATE_CON(2), 9, GFLAGS), 732 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED, 733 RK3399_CLKGATE_CON(2), 10, GFLAGS), 734 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED, 735 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS), 736 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED, 737 RK3399_CLKGATE_CON(15), 5, GFLAGS), 738 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED, 739 RK3399_CLKGATE_CON(15), 6, GFLAGS), 740 741 /* vcodec */ 742 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 743 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS, 744 RK3399_CLKGATE_CON(4), 0, GFLAGS), 745 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 746 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS, 747 RK3399_CLKGATE_CON(4), 1, GFLAGS), 748 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, 749 RK3399_CLKGATE_CON(17), 2, GFLAGS), 750 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED, 751 RK3399_CLKGATE_CON(17), 3, GFLAGS), 752 753 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, 754 RK3399_CLKGATE_CON(17), 0, GFLAGS), 755 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED, 756 RK3399_CLKGATE_CON(17), 1, GFLAGS), 757 758 /* vdu */ 759 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0, 760 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, 761 RK3399_CLKGATE_CON(4), 4, GFLAGS), 762 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0, 763 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS, 764 RK3399_CLKGATE_CON(4), 5, GFLAGS), 765 766 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 767 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS, 768 RK3399_CLKGATE_CON(4), 2, GFLAGS), 769 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0, 770 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS, 771 RK3399_CLKGATE_CON(4), 3, GFLAGS), 772 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0, 773 RK3399_CLKGATE_CON(17), 10, GFLAGS), 774 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED, 775 RK3399_CLKGATE_CON(17), 11, GFLAGS), 776 777 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0, 778 RK3399_CLKGATE_CON(17), 8, GFLAGS), 779 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED, 780 RK3399_CLKGATE_CON(17), 9, GFLAGS), 781 782 /* iep */ 783 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 784 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, 785 RK3399_CLKGATE_CON(4), 6, GFLAGS), 786 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0, 787 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS, 788 RK3399_CLKGATE_CON(4), 7, GFLAGS), 789 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0, 790 RK3399_CLKGATE_CON(16), 2, GFLAGS), 791 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED, 792 RK3399_CLKGATE_CON(16), 3, GFLAGS), 793 794 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, 795 RK3399_CLKGATE_CON(16), 0, GFLAGS), 796 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, 797 RK3399_CLKGATE_CON(16), 1, GFLAGS), 798 799 /* rga */ 800 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 801 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, 802 RK3399_CLKGATE_CON(4), 10, GFLAGS), 803 804 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 805 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, 806 RK3399_CLKGATE_CON(4), 8, GFLAGS), 807 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0, 808 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS, 809 RK3399_CLKGATE_CON(4), 9, GFLAGS), 810 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, 811 RK3399_CLKGATE_CON(16), 10, GFLAGS), 812 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED, 813 RK3399_CLKGATE_CON(16), 11, GFLAGS), 814 815 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, 816 RK3399_CLKGATE_CON(16), 8, GFLAGS), 817 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, 818 RK3399_CLKGATE_CON(16), 9, GFLAGS), 819 820 /* center */ 821 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 822 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, 823 RK3399_CLKGATE_CON(3), 7, GFLAGS), 824 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED, 825 RK3399_CLKGATE_CON(19), 0, GFLAGS), 826 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED, 827 RK3399_CLKGATE_CON(19), 1, GFLAGS), 828 829 /* gpu */ 830 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 831 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, 832 RK3399_CLKGATE_CON(13), 0, GFLAGS), 833 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, 834 RK3399_CLKGATE_CON(30), 8, GFLAGS), 835 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0, 836 RK3399_CLKGATE_CON(30), 10, GFLAGS), 837 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0, 838 RK3399_CLKGATE_CON(30), 11, GFLAGS), 839 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0, 840 RK3399_CLKGATE_CON(13), 1, GFLAGS), 841 842 /* perihp */ 843 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED, 844 RK3399_CLKGATE_CON(5), 1, GFLAGS), 845 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED, 846 RK3399_CLKGATE_CON(5), 0, GFLAGS), 847 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED, 848 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS, 849 RK3399_CLKGATE_CON(5), 2, GFLAGS), 850 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, 851 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS, 852 RK3399_CLKGATE_CON(5), 3, GFLAGS), 853 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, 854 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS, 855 RK3399_CLKGATE_CON(5), 4, GFLAGS), 856 857 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0, 858 RK3399_CLKGATE_CON(20), 2, GFLAGS), 859 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0, 860 RK3399_CLKGATE_CON(20), 10, GFLAGS), 861 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED, 862 RK3399_CLKGATE_CON(20), 12, GFLAGS), 863 864 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0, 865 RK3399_CLKGATE_CON(20), 5, GFLAGS), 866 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0, 867 RK3399_CLKGATE_CON(20), 6, GFLAGS), 868 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0, 869 RK3399_CLKGATE_CON(20), 7, GFLAGS), 870 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0, 871 RK3399_CLKGATE_CON(20), 8, GFLAGS), 872 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0, 873 RK3399_CLKGATE_CON(20), 9, GFLAGS), 874 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED, 875 RK3399_CLKGATE_CON(20), 13, GFLAGS), 876 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED, 877 RK3399_CLKGATE_CON(20), 15, GFLAGS), 878 879 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED, 880 RK3399_CLKGATE_CON(20), 4, GFLAGS), 881 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0, 882 RK3399_CLKGATE_CON(20), 11, GFLAGS), 883 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED, 884 RK3399_CLKGATE_CON(20), 14, GFLAGS), 885 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0, 886 RK3399_CLKGATE_CON(31), 8, GFLAGS), 887 888 /* sdio & sdmmc */ 889 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, 890 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, 891 RK3399_CLKGATE_CON(12), 13, GFLAGS), 892 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0, 893 RK3399_CLKGATE_CON(33), 8, GFLAGS), 894 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED, 895 RK3399_CLKGATE_CON(33), 9, GFLAGS), 896 897 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, 898 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS, 899 RK3399_CLKGATE_CON(6), 0, GFLAGS), 900 901 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, 902 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS, 903 RK3399_CLKGATE_CON(6), 1, GFLAGS), 904 905 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), 906 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), 907 908 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), 909 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), 910 911 /* pcie */ 912 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0, 913 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS, 914 RK3399_CLKGATE_CON(6), 2, GFLAGS), 915 916 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0, 917 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS, 918 RK3399_CLKGATE_CON(12), 6, GFLAGS), 919 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT, 920 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS), 921 922 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0, 923 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS, 924 RK3399_CLKGATE_CON(6), 3, GFLAGS), 925 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT, 926 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS), 927 928 /* emmc */ 929 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0, 930 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS, 931 RK3399_CLKGATE_CON(6), 14, GFLAGS), 932 933 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED, 934 RK3399_CLKGATE_CON(6), 13, GFLAGS), 935 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED, 936 RK3399_CLKGATE_CON(6), 12, GFLAGS), 937 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED, 938 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS), 939 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED, 940 RK3399_CLKGATE_CON(32), 8, GFLAGS), 941 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED, 942 RK3399_CLKGATE_CON(32), 9, GFLAGS), 943 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED, 944 RK3399_CLKGATE_CON(32), 10, GFLAGS), 945 946 /* perilp0 */ 947 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED, 948 RK3399_CLKGATE_CON(7), 1, GFLAGS), 949 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED, 950 RK3399_CLKGATE_CON(7), 0, GFLAGS), 951 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED, 952 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS, 953 RK3399_CLKGATE_CON(7), 2, GFLAGS), 954 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED, 955 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS, 956 RK3399_CLKGATE_CON(7), 3, GFLAGS), 957 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0, 958 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS, 959 RK3399_CLKGATE_CON(7), 4, GFLAGS), 960 961 /* aclk_perilp0 gates */ 962 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS), 963 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS), 964 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS), 965 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS), 966 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS), 967 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS), 968 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS), 969 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS), 970 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS), 971 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS), 972 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS), 973 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS), 974 975 /* hclk_perilp0 gates */ 976 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS), 977 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS), 978 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS), 979 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS), 980 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS), 981 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS), 982 983 /* pclk_perilp0 gates */ 984 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS), 985 986 /* crypto */ 987 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0, 988 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS, 989 RK3399_CLKGATE_CON(7), 7, GFLAGS), 990 991 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0, 992 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS, 993 RK3399_CLKGATE_CON(7), 8, GFLAGS), 994 995 /* cm0s_perilp */ 996 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0, 997 RK3399_CLKGATE_CON(7), 6, GFLAGS), 998 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0, 999 RK3399_CLKGATE_CON(7), 5, GFLAGS), 1000 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0, 1001 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS, 1002 RK3399_CLKGATE_CON(7), 9, GFLAGS), 1003 1004 /* fclk_cm0s gates */ 1005 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS), 1006 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS), 1007 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS), 1008 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS), 1009 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS), 1010 1011 /* perilp1 */ 1012 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED, 1013 RK3399_CLKGATE_CON(8), 1, GFLAGS), 1014 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED, 1015 RK3399_CLKGATE_CON(8), 0, GFLAGS), 1016 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED, 1017 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS), 1018 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED, 1019 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS, 1020 RK3399_CLKGATE_CON(8), 2, GFLAGS), 1021 1022 /* hclk_perilp1 gates */ 1023 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS), 1024 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS), 1025 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS), 1026 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS), 1027 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS), 1028 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS), 1029 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS), 1030 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS), 1031 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS), 1032 1033 /* pclk_perilp1 gates */ 1034 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS), 1035 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS), 1036 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS), 1037 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS), 1038 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS), 1039 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS), 1040 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS), 1041 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS), 1042 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS), 1043 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS), 1044 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS), 1045 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS), 1046 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS), 1047 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS), 1048 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS), 1049 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS), 1050 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS), 1051 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), 1052 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS), 1053 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS), 1054 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), 1055 1056 /* saradc */ 1057 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, 1058 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS, 1059 RK3399_CLKGATE_CON(9), 11, GFLAGS), 1060 1061 /* tsadc */ 1062 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0, 1063 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS, 1064 RK3399_CLKGATE_CON(9), 10, GFLAGS), 1065 1066 /* cif_testout */ 1067 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, 1068 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS), 1069 COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0, 1070 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, 1071 RK3399_CLKGATE_CON(13), 14, GFLAGS), 1072 1073 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, 1074 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS), 1075 COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0, 1076 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS, 1077 RK3399_CLKGATE_CON(13), 15, GFLAGS), 1078 1079 /* vio */ 1080 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 1081 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, 1082 RK3399_CLKGATE_CON(11), 0, GFLAGS), 1083 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0, 1084 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS, 1085 RK3399_CLKGATE_CON(11), 1, GFLAGS), 1086 1087 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED, 1088 RK3399_CLKGATE_CON(29), 0, GFLAGS), 1089 1090 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0, 1091 RK3399_CLKGATE_CON(29), 1, GFLAGS), 1092 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0, 1093 RK3399_CLKGATE_CON(29), 2, GFLAGS), 1094 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED, 1095 RK3399_CLKGATE_CON(29), 12, GFLAGS), 1096 1097 /* hdcp */ 1098 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0, 1099 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, 1100 RK3399_CLKGATE_CON(11), 12, GFLAGS), 1101 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0, 1102 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS, 1103 RK3399_CLKGATE_CON(11), 3, GFLAGS), 1104 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0, 1105 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS, 1106 RK3399_CLKGATE_CON(11), 10, GFLAGS), 1107 1108 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED, 1109 RK3399_CLKGATE_CON(29), 4, GFLAGS), 1110 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0, 1111 RK3399_CLKGATE_CON(29), 10, GFLAGS), 1112 1113 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED, 1114 RK3399_CLKGATE_CON(29), 5, GFLAGS), 1115 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0, 1116 RK3399_CLKGATE_CON(29), 9, GFLAGS), 1117 1118 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED, 1119 RK3399_CLKGATE_CON(29), 3, GFLAGS), 1120 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0, 1121 RK3399_CLKGATE_CON(29), 6, GFLAGS), 1122 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0, 1123 RK3399_CLKGATE_CON(29), 7, GFLAGS), 1124 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0, 1125 RK3399_CLKGATE_CON(29), 8, GFLAGS), 1126 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0, 1127 RK3399_CLKGATE_CON(29), 11, GFLAGS), 1128 1129 /* edp */ 1130 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0, 1131 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS, 1132 RK3399_CLKGATE_CON(11), 8, GFLAGS), 1133 1134 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0, 1135 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS, 1136 RK3399_CLKGATE_CON(11), 11, GFLAGS), 1137 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED, 1138 RK3399_CLKGATE_CON(32), 12, GFLAGS), 1139 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0, 1140 RK3399_CLKGATE_CON(32), 13, GFLAGS), 1141 1142 /* hdmi */ 1143 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, 1144 RK3399_CLKGATE_CON(11), 6, GFLAGS), 1145 1146 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0, 1147 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS, 1148 RK3399_CLKGATE_CON(11), 7, GFLAGS), 1149 1150 /* vop0 */ 1151 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, 1152 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS, 1153 RK3399_CLKGATE_CON(10), 8, GFLAGS), 1154 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0, 1155 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS, 1156 RK3399_CLKGATE_CON(10), 9, GFLAGS), 1157 1158 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0, 1159 RK3399_CLKGATE_CON(28), 3, GFLAGS), 1160 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED, 1161 RK3399_CLKGATE_CON(28), 1, GFLAGS), 1162 1163 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0, 1164 RK3399_CLKGATE_CON(28), 2, GFLAGS), 1165 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, 1166 RK3399_CLKGATE_CON(28), 0, GFLAGS), 1167 1168 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, 1169 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, 1170 RK3399_CLKGATE_CON(10), 12, GFLAGS), 1171 1172 COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0, 1173 RK3399_CLKSEL_CON(106), 0, 1174 &rk3399_dclk_vop0_fracmux), 1175 1176 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0, 1177 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, 1178 RK3399_CLKGATE_CON(10), 14, GFLAGS), 1179 1180 /* vop1 */ 1181 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, 1182 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, 1183 RK3399_CLKGATE_CON(10), 10, GFLAGS), 1184 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0, 1185 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS, 1186 RK3399_CLKGATE_CON(10), 11, GFLAGS), 1187 1188 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0, 1189 RK3399_CLKGATE_CON(28), 7, GFLAGS), 1190 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED, 1191 RK3399_CLKGATE_CON(28), 5, GFLAGS), 1192 1193 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0, 1194 RK3399_CLKGATE_CON(28), 6, GFLAGS), 1195 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED, 1196 RK3399_CLKGATE_CON(28), 4, GFLAGS), 1197 1198 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0, 1199 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, 1200 RK3399_CLKGATE_CON(10), 13, GFLAGS), 1201 1202 COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0, 1203 RK3399_CLKSEL_CON(107), 0, 1204 &rk3399_dclk_vop1_fracmux), 1205 1206 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED, 1207 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS, 1208 RK3399_CLKGATE_CON(10), 15, GFLAGS), 1209 1210 /* isp */ 1211 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0, 1212 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS, 1213 RK3399_CLKGATE_CON(12), 8, GFLAGS), 1214 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0, 1215 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS, 1216 RK3399_CLKGATE_CON(12), 9, GFLAGS), 1217 1218 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED, 1219 RK3399_CLKGATE_CON(27), 1, GFLAGS), 1220 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0, 1221 RK3399_CLKGATE_CON(27), 5, GFLAGS), 1222 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0, 1223 RK3399_CLKGATE_CON(27), 7, GFLAGS), 1224 1225 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED, 1226 RK3399_CLKGATE_CON(27), 0, GFLAGS), 1227 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0, 1228 RK3399_CLKGATE_CON(27), 4, GFLAGS), 1229 1230 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0, 1231 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS, 1232 RK3399_CLKGATE_CON(11), 4, GFLAGS), 1233 1234 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0, 1235 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS, 1236 RK3399_CLKGATE_CON(12), 10, GFLAGS), 1237 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0, 1238 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS, 1239 RK3399_CLKGATE_CON(12), 11, GFLAGS), 1240 1241 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED, 1242 RK3399_CLKGATE_CON(27), 3, GFLAGS), 1243 1244 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED, 1245 RK3399_CLKGATE_CON(27), 2, GFLAGS), 1246 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0, 1247 RK3399_CLKGATE_CON(27), 8, GFLAGS), 1248 1249 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0, 1250 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS, 1251 RK3399_CLKGATE_CON(11), 5, GFLAGS), 1252 1253 /* 1254 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system, 1255 * so we ignore the mux and make clocks nodes as following, 1256 * 1257 * pclkin_cifinv --|-------\ 1258 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper 1259 * pclkin_cif --|-------/ 1260 */ 1261 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0, 1262 RK3399_CLKGATE_CON(27), 6, GFLAGS), 1263 1264 /* cif */ 1265 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0, 1266 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 1267 RK3399_CLKGATE_CON(10), 7, GFLAGS), 1268 1269 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, 1270 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), 1271 1272 /* gic */ 1273 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 1274 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS, 1275 RK3399_CLKGATE_CON(12), 12, GFLAGS), 1276 1277 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS), 1278 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS), 1279 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS), 1280 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS), 1281 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS), 1282 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS), 1283 1284 /* alive */ 1285 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */ 1286 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, 1287 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS), 1288 1289 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS), 1290 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS), 1291 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS), 1292 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS), 1293 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS), 1294 1295 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS), 1296 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS), 1297 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS), 1298 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS), 1299 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS), 1300 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS), 1301 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS), 1302 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS), 1303 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS), 1304 1305 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS), 1306 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS), 1307 1308 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS), 1309 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS), 1310 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS), 1311 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS), 1312 1313 /* testout */ 1314 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, 1315 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), 1316 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0, 1317 RK3399_CLKSEL_CON(105), 0, 1318 RK3399_CLKGATE_CON(13), 9, GFLAGS), 1319 1320 DIV(0, "clk_test_24m", "xin24m", 0, 1321 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS), 1322 1323 /* spi */ 1324 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0, 1325 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS, 1326 RK3399_CLKGATE_CON(9), 12, GFLAGS), 1327 1328 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0, 1329 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS, 1330 RK3399_CLKGATE_CON(9), 13, GFLAGS), 1331 1332 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0, 1333 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS, 1334 RK3399_CLKGATE_CON(9), 14, GFLAGS), 1335 1336 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0, 1337 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS, 1338 RK3399_CLKGATE_CON(9), 15, GFLAGS), 1339 1340 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0, 1341 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS, 1342 RK3399_CLKGATE_CON(13), 13, GFLAGS), 1343 1344 /* i2c */ 1345 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0, 1346 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS, 1347 RK3399_CLKGATE_CON(10), 0, GFLAGS), 1348 1349 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0, 1350 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS, 1351 RK3399_CLKGATE_CON(10), 2, GFLAGS), 1352 1353 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0, 1354 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS, 1355 RK3399_CLKGATE_CON(10), 4, GFLAGS), 1356 1357 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0, 1358 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS, 1359 RK3399_CLKGATE_CON(10), 1, GFLAGS), 1360 1361 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0, 1362 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS, 1363 RK3399_CLKGATE_CON(10), 3, GFLAGS), 1364 1365 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0, 1366 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS, 1367 RK3399_CLKGATE_CON(10), 5, GFLAGS), 1368 1369 /* timer */ 1370 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS), 1371 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS), 1372 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS), 1373 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS), 1374 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS), 1375 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS), 1376 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS), 1377 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS), 1378 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS), 1379 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS), 1380 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS), 1381 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS), 1382 1383 /* clk_test */ 1384 /* clk_test_pre is controlled by CRU_MISC_CON[3] */ 1385 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, 1386 RK3399_CLKSEL_CON(58), 0, 5, DFLAGS, 1387 RK3399_CLKGATE_CON(13), 11, GFLAGS), 1388 1389 /* ddrc */ 1390 GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), 1391 0, GFLAGS), 1392 GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), 1393 1, GFLAGS), 1394 GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), 1395 2, GFLAGS), 1396 GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), 1397 3, GFLAGS), 1398 COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0, 1399 RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP), 1400 }; 1401 1402 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { 1403 /* 1404 * PMU CRU Clock-Architecture 1405 */ 1406 1407 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0, 1408 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS), 1409 1410 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0, 1411 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS), 1412 1413 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0, 1414 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS, 1415 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS), 1416 1417 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED, 1418 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, 1419 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), 1420 1421 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0, 1422 RK3399_PMU_CLKSEL_CON(7), 0, 1423 &rk3399_pmuclk_wifi_fracmux), 1424 1425 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED, 1426 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS), 1427 1428 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0, 1429 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS, 1430 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS), 1431 1432 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0, 1433 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, 1434 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS), 1435 1436 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0, 1437 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS, 1438 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS), 1439 1440 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED, 1441 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS), 1442 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, 1443 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), 1444 1445 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0, 1446 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, 1447 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), 1448 1449 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0, 1450 RK3399_PMU_CLKSEL_CON(6), 0, 1451 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, 1452 &rk3399_uart4_pmu_fracmux), 1453 1454 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED, 1455 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS), 1456 1457 /* pmu clock gates */ 1458 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS), 1459 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS), 1460 1461 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS), 1462 1463 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS), 1464 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS), 1465 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS), 1466 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS), 1467 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS), 1468 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS), 1469 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS), 1470 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS), 1471 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS), 1472 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS), 1473 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS), 1474 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS), 1475 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS), 1476 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS), 1477 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), 1478 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), 1479 1480 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), 1481 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), 1482 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), 1483 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), 1484 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), 1485 }; 1486 1487 static const char *const rk3399_cru_critical_clocks[] __initconst = { 1488 "aclk_cci_pre", 1489 "aclk_gic", 1490 "aclk_gic_noc", 1491 "aclk_hdcp_noc", 1492 "hclk_hdcp_noc", 1493 "pclk_hdcp_noc", 1494 "pclk_perilp0", 1495 "pclk_perilp0", 1496 "hclk_perilp0", 1497 "hclk_perilp0_noc", 1498 "pclk_perilp1", 1499 "pclk_perilp1_noc", 1500 "pclk_perihp", 1501 "pclk_perihp_noc", 1502 "hclk_perihp", 1503 "aclk_perihp", 1504 "aclk_perihp_noc", 1505 "aclk_perilp0", 1506 "aclk_perilp0_noc", 1507 "hclk_perilp1", 1508 "hclk_perilp1_noc", 1509 "aclk_dmac0_perilp", 1510 "aclk_emmc_noc", 1511 "gpll_hclk_perilp1_src", 1512 "gpll_aclk_perilp0_src", 1513 "gpll_aclk_perihp_src", 1514 "aclk_vio_noc", 1515 1516 /* ddrc */ 1517 "sclk_ddrc" 1518 }; 1519 1520 static const char *const rk3399_pmucru_critical_clocks[] __initconst = { 1521 "ppll", 1522 "pclk_pmu_src", 1523 "fclk_cm0s_src_pmu", 1524 "clk_timer_src_pmu", 1525 }; 1526 1527 static void __init rk3399_clk_init(struct device_node *np) 1528 { 1529 struct rockchip_clk_provider *ctx; 1530 void __iomem *reg_base; 1531 struct clk *clk; 1532 1533 reg_base = of_iomap(np, 0); 1534 if (!reg_base) { 1535 pr_err("%s: could not map cru region\n", __func__); 1536 return; 1537 } 1538 1539 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 1540 if (IS_ERR(ctx)) { 1541 pr_err("%s: rockchip clk init failed\n", __func__); 1542 iounmap(reg_base); 1543 return; 1544 } 1545 1546 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ 1547 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1); 1548 if (IS_ERR(clk)) 1549 pr_warn("%s: could not register clock pclk_wdt: %ld\n", 1550 __func__, PTR_ERR(clk)); 1551 else 1552 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); 1553 1554 rockchip_clk_register_plls(ctx, rk3399_pll_clks, 1555 ARRAY_SIZE(rk3399_pll_clks), -1); 1556 1557 rockchip_clk_register_branches(ctx, rk3399_clk_branches, 1558 ARRAY_SIZE(rk3399_clk_branches)); 1559 1560 rockchip_clk_protect_critical(rk3399_cru_critical_clocks, 1561 ARRAY_SIZE(rk3399_cru_critical_clocks)); 1562 1563 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", 1564 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), 1565 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates, 1566 ARRAY_SIZE(rk3399_cpuclkl_rates)); 1567 1568 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", 1569 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), 1570 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates, 1571 ARRAY_SIZE(rk3399_cpuclkb_rates)); 1572 1573 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), 1574 ROCKCHIP_SOFTRST_HIWORD_MASK); 1575 1576 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL); 1577 1578 rockchip_clk_of_add_provider(np, ctx); 1579 } 1580 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init); 1581 1582 static void __init rk3399_pmu_clk_init(struct device_node *np) 1583 { 1584 struct rockchip_clk_provider *ctx; 1585 void __iomem *reg_base; 1586 1587 reg_base = of_iomap(np, 0); 1588 if (!reg_base) { 1589 pr_err("%s: could not map cru pmu region\n", __func__); 1590 return; 1591 } 1592 1593 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 1594 if (IS_ERR(ctx)) { 1595 pr_err("%s: rockchip pmu clk init failed\n", __func__); 1596 iounmap(reg_base); 1597 return; 1598 } 1599 1600 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks, 1601 ARRAY_SIZE(rk3399_pmu_pll_clks), -1); 1602 1603 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches, 1604 ARRAY_SIZE(rk3399_clk_pmu_branches)); 1605 1606 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks, 1607 ARRAY_SIZE(rk3399_pmucru_critical_clocks)); 1608 1609 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), 1610 ROCKCHIP_SOFTRST_HIWORD_MASK); 1611 1612 rockchip_clk_of_add_provider(np, ctx); 1613 } 1614 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init); 1615