1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
4  * Author: Xing Zheng <zhengxing@rock-chips.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <dt-bindings/clock/rk3399-cru.h>
16 #include "clk.h"
17 
18 enum rk3399_plls {
19 	lpll, bpll, dpll, cpll, gpll, npll, vpll,
20 };
21 
22 enum rk3399_pmu_plls {
23 	ppll,
24 };
25 
26 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
27 	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
28 	RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
29 	RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
30 	RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
31 	RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
32 	RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
33 	RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
34 	RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
35 	RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
36 	RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
37 	RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
38 	RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
39 	RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
40 	RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
41 	RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
42 	RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
43 	RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
44 	RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
45 	RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
46 	RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
47 	RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
48 	RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
49 	RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
50 	RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
51 	RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
52 	RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
53 	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
54 	RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
55 	RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
56 	RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
57 	RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
58 	RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
59 	RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
60 	RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
61 	RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
62 	RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
63 	RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
64 	RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
65 	RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
66 	RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
67 	RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
68 	RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
69 	RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
70 	RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
71 	RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
72 	RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
73 	RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
74 	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
75 	RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
76 	RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
77 	RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
78 	RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
79 	RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
80 	RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
81 	RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
82 	RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
83 	RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
84 	RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
85 	RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
86 	RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
87 	RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
88 	RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
89 	RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
90 	RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
91 	RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
92 	RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
93 	RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
94 	RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
95 	RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
96 	RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
97 	RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
98 	RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
99 	RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
100 	RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
101 	RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
102 	RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),
103 	RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),
104 	RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),
105 	{ /* sentinel */ },
106 };
107 
108 /* CRU parents */
109 PNAME(mux_pll_p)				= { "xin24m", "xin32k" };
110 
111 PNAME(mux_armclkl_p)				= { "clk_core_l_lpll_src",
112 						    "clk_core_l_bpll_src",
113 						    "clk_core_l_dpll_src",
114 						    "clk_core_l_gpll_src" };
115 PNAME(mux_armclkb_p)				= { "clk_core_b_lpll_src",
116 						    "clk_core_b_bpll_src",
117 						    "clk_core_b_dpll_src",
118 						    "clk_core_b_gpll_src" };
119 PNAME(mux_ddrclk_p)				= { "clk_ddrc_lpll_src",
120 						    "clk_ddrc_bpll_src",
121 						    "clk_ddrc_dpll_src",
122 						    "clk_ddrc_gpll_src" };
123 PNAME(mux_aclk_cci_p)				= { "cpll_aclk_cci_src",
124 						    "gpll_aclk_cci_src",
125 						    "npll_aclk_cci_src",
126 						    "vpll_aclk_cci_src" };
127 PNAME(mux_cci_trace_p)				= { "cpll_cci_trace",
128 						    "gpll_cci_trace" };
129 PNAME(mux_cs_p)					= { "cpll_cs", "gpll_cs",
130 						    "npll_cs"};
131 PNAME(mux_aclk_perihp_p)			= { "cpll_aclk_perihp_src",
132 						    "gpll_aclk_perihp_src" };
133 
134 PNAME(mux_pll_src_cpll_gpll_p)			= { "cpll", "gpll" };
135 PNAME(mux_pll_src_cpll_gpll_npll_p)		= { "cpll", "gpll", "npll" };
136 PNAME(mux_pll_src_cpll_gpll_ppll_p)		= { "cpll", "gpll", "ppll" };
137 PNAME(mux_pll_src_cpll_gpll_upll_p)		= { "cpll", "gpll", "upll" };
138 PNAME(mux_pll_src_npll_cpll_gpll_p)		= { "npll", "cpll", "gpll" };
139 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p)	= { "cpll", "gpll", "npll",
140 						    "ppll" };
141 PNAME(mux_pll_src_cpll_gpll_npll_24m_p)		= { "cpll", "gpll", "npll",
142 						    "xin24m" };
143 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p)	= { "cpll", "gpll", "npll",
144 						    "clk_usbphy_480m" };
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p)	= { "ppll", "cpll", "gpll",
146 						    "npll", "upll" };
147 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)	= { "cpll", "gpll", "npll",
148 						    "upll", "xin24m" };
149 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
150 						    "ppll", "upll", "xin24m" };
151 
152 PNAME(mux_pll_src_vpll_cpll_gpll_p)		= { "vpll", "cpll", "gpll" };
153 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)	= { "vpll", "cpll", "gpll",
154 						    "npll" };
155 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)		= { "vpll", "cpll", "gpll",
156 						    "xin24m" };
157 
158 PNAME(mux_dclk_vop0_p)			= { "dclk_vop0_div",
159 					    "dclk_vop0_frac" };
160 PNAME(mux_dclk_vop1_p)			= { "dclk_vop1_div",
161 					    "dclk_vop1_frac" };
162 
163 PNAME(mux_clk_cif_p)			= { "clk_cifout_src", "xin24m" };
164 
165 PNAME(mux_pll_src_24m_usbphy480m_p)	= { "xin24m", "clk_usbphy_480m" };
166 PNAME(mux_pll_src_24m_pciephy_p)	= { "xin24m", "clk_pciephy_ref100m" };
167 PNAME(mux_pll_src_24m_32k_cpll_gpll_p)	= { "xin24m", "xin32k",
168 					    "cpll", "gpll" };
169 PNAME(mux_pciecore_cru_phy_p)		= { "clk_pcie_core_cru",
170 					    "clk_pcie_core_phy" };
171 
172 PNAME(mux_aclk_emmc_p)			= { "cpll_aclk_emmc_src",
173 					    "gpll_aclk_emmc_src" };
174 
175 PNAME(mux_aclk_perilp0_p)		= { "cpll_aclk_perilp0_src",
176 					    "gpll_aclk_perilp0_src" };
177 
178 PNAME(mux_fclk_cm0s_p)			= { "cpll_fclk_cm0s_src",
179 					    "gpll_fclk_cm0s_src" };
180 
181 PNAME(mux_hclk_perilp1_p)		= { "cpll_hclk_perilp1_src",
182 					    "gpll_hclk_perilp1_src" };
183 
184 PNAME(mux_clk_testout1_p)		= { "clk_testout1_pll_src", "xin24m" };
185 PNAME(mux_clk_testout2_p)		= { "clk_testout2_pll_src", "xin24m" };
186 
187 PNAME(mux_usbphy_480m_p)		= { "clk_usbphy0_480m_src",
188 					    "clk_usbphy1_480m_src" };
189 PNAME(mux_aclk_gmac_p)			= { "cpll_aclk_gmac_src",
190 					    "gpll_aclk_gmac_src" };
191 PNAME(mux_rmii_p)			= { "clk_gmac", "clkin_gmac" };
192 PNAME(mux_spdif_p)			= { "clk_spdif_div", "clk_spdif_frac",
193 					    "clkin_i2s", "xin12m" };
194 PNAME(mux_i2s0_p)			= { "clk_i2s0_div", "clk_i2s0_frac",
195 					    "clkin_i2s", "xin12m" };
196 PNAME(mux_i2s1_p)			= { "clk_i2s1_div", "clk_i2s1_frac",
197 					    "clkin_i2s", "xin12m" };
198 PNAME(mux_i2s2_p)			= { "clk_i2s2_div", "clk_i2s2_frac",
199 					    "clkin_i2s", "xin12m" };
200 PNAME(mux_i2sch_p)			= { "clk_i2s0", "clk_i2s1",
201 					    "clk_i2s2" };
202 PNAME(mux_i2sout_p)			= { "clk_i2sout_src", "xin12m" };
203 
204 PNAME(mux_uart0_p)	= { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
205 PNAME(mux_uart1_p)	= { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
206 PNAME(mux_uart2_p)	= { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
207 PNAME(mux_uart3_p)	= { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
208 
209 /* PMU CRU parents */
210 PNAME(mux_ppll_24m_p)		= { "ppll", "xin24m" };
211 PNAME(mux_24m_ppll_p)		= { "xin24m", "ppll" };
212 PNAME(mux_fclk_cm0s_pmu_ppll_p)	= { "fclk_cm0s_pmu_ppll_src", "xin24m" };
213 PNAME(mux_wifi_pmu_p)		= { "clk_wifi_div", "clk_wifi_frac" };
214 PNAME(mux_uart4_pmu_p)		= { "clk_uart4_div", "clk_uart4_frac",
215 				    "xin24m" };
216 PNAME(mux_clk_testout2_2io_p)	= { "clk_testout2", "clk_32k_suspend_pmu" };
217 
218 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
219 	[lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
220 		     RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
221 	[bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
222 		     RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
223 	[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
224 		     RK3399_PLL_CON(19), 8, 31, 0, NULL),
225 	[cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
226 		     RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
227 	[gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
228 		     RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
229 	[npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, RK3399_PLL_CON(40),
230 		     RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
231 	[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, RK3399_PLL_CON(48),
232 		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
233 };
234 
235 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
236 	[ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll",  mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
237 		     RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
238 };
239 
240 #define MFLAGS CLK_MUX_HIWORD_MASK
241 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
242 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
243 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
244 
245 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
246 	MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
247 			RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
248 
249 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
250 	MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
251 			RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
252 
253 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
254 	MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
255 			RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
256 
257 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
258 	MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
259 			RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
260 
261 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
262 	MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
263 			RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
264 
265 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
266 	MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
267 			RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
268 
269 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
270 	MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
271 			RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
272 
273 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
274 	MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
275 			RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
276 
277 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
278 	MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
279 			RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
280 
281 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
282 	MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
283 			RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
284 
285 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
286 	MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
287 			RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
288 
289 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
290 	MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
291 			RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
292 
293 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
294 	.core_reg = RK3399_CLKSEL_CON(0),
295 	.div_core_shift = 0,
296 	.div_core_mask = 0x1f,
297 	.mux_core_alt = 3,
298 	.mux_core_main = 0,
299 	.mux_core_shift = 6,
300 	.mux_core_mask = 0x3,
301 };
302 
303 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
304 	.core_reg = RK3399_CLKSEL_CON(2),
305 	.div_core_shift = 0,
306 	.div_core_mask = 0x1f,
307 	.mux_core_alt = 3,
308 	.mux_core_main = 1,
309 	.mux_core_shift = 6,
310 	.mux_core_mask = 0x3,
311 };
312 
313 #define RK3399_DIV_ACLKM_MASK		0x1f
314 #define RK3399_DIV_ACLKM_SHIFT		8
315 #define RK3399_DIV_ATCLK_MASK		0x1f
316 #define RK3399_DIV_ATCLK_SHIFT		0
317 #define RK3399_DIV_PCLK_DBG_MASK	0x1f
318 #define RK3399_DIV_PCLK_DBG_SHIFT	8
319 
320 #define RK3399_CLKSEL0(_offs, _aclkm)					\
321 	{								\
322 		.reg = RK3399_CLKSEL_CON(0 + _offs),			\
323 		.val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK,	\
324 				RK3399_DIV_ACLKM_SHIFT),		\
325 	}
326 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg)				\
327 	{								\
328 		.reg = RK3399_CLKSEL_CON(1 + _offs),			\
329 		.val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK,	\
330 				RK3399_DIV_ATCLK_SHIFT) |		\
331 		       HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK,	\
332 				RK3399_DIV_PCLK_DBG_SHIFT),		\
333 	}
334 
335 /* cluster_l: aclkm in clksel0, rest in clksel1 */
336 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg)		\
337 	{								\
338 		.prate = _prate##U,					\
339 		.divs = {						\
340 			RK3399_CLKSEL0(0, _aclkm),			\
341 			RK3399_CLKSEL1(0, _atclk, _pdbg),		\
342 		},							\
343 	}
344 
345 /* cluster_b: aclkm in clksel2, rest in clksel3 */
346 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg)		\
347 	{								\
348 		.prate = _prate##U,					\
349 		.divs = {						\
350 			RK3399_CLKSEL0(2, _aclkm),			\
351 			RK3399_CLKSEL1(2, _atclk, _pdbg),		\
352 		},							\
353 	}
354 
355 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
356 	RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
357 	RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
358 	RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
359 	RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
360 	RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
361 	RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
362 	RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
363 	RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
364 	RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
365 	RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
366 	RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
367 	RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
368 	RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
369 	RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
370 	RK3399_CPUCLKL_RATE(  96000000, 1, 1, 1),
371 };
372 
373 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
374 	RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
375 	RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
376 	RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
377 	RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
378 	RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9),
379 	RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
380 	RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
381 	RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
382 	RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
383 	RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
384 	RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
385 	RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
386 	RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
387 	RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
388 	RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
389 	RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
390 	RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
391 	RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
392 	RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
393 	RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
394 	RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
395 	RK3399_CPUCLKB_RATE(  96000000, 1, 1, 1),
396 };
397 
398 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
399 	/*
400 	 * CRU Clock-Architecture
401 	 */
402 
403 	/* usbphy */
404 	GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
405 			RK3399_CLKGATE_CON(6), 5, GFLAGS),
406 	GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
407 			RK3399_CLKGATE_CON(6), 6, GFLAGS),
408 
409 	GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
410 			RK3399_CLKGATE_CON(13), 12, GFLAGS),
411 	GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
412 			RK3399_CLKGATE_CON(13), 12, GFLAGS),
413 	MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
414 			RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
415 
416 	MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
417 			RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
418 
419 	COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
420 			RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
421 			RK3399_CLKGATE_CON(6), 4, GFLAGS),
422 
423 	COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
424 			RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
425 			RK3399_CLKGATE_CON(12), 0, GFLAGS),
426 	GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
427 			RK3399_CLKGATE_CON(30), 0, GFLAGS),
428 	GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
429 			RK3399_CLKGATE_CON(30), 1, GFLAGS),
430 	GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
431 			RK3399_CLKGATE_CON(30), 2, GFLAGS),
432 	GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
433 			RK3399_CLKGATE_CON(30), 3, GFLAGS),
434 	GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
435 			RK3399_CLKGATE_CON(30), 4, GFLAGS),
436 
437 	GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
438 			RK3399_CLKGATE_CON(12), 1, GFLAGS),
439 	GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
440 			RK3399_CLKGATE_CON(12), 2, GFLAGS),
441 
442 	COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
443 			RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
444 			RK3399_CLKGATE_CON(12), 3, GFLAGS),
445 
446 	COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
447 			RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
448 			RK3399_CLKGATE_CON(12), 4, GFLAGS),
449 
450 	COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
451 			RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
452 			RK3399_CLKGATE_CON(13), 4, GFLAGS),
453 
454 	COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
455 			RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
456 			RK3399_CLKGATE_CON(13), 5, GFLAGS),
457 
458 	COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
459 			RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
460 			RK3399_CLKGATE_CON(13), 6, GFLAGS),
461 
462 	COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
463 			RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
464 			RK3399_CLKGATE_CON(13), 7, GFLAGS),
465 
466 	/* little core */
467 	GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
468 			RK3399_CLKGATE_CON(0), 0, GFLAGS),
469 	GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
470 			RK3399_CLKGATE_CON(0), 1, GFLAGS),
471 	GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
472 			RK3399_CLKGATE_CON(0), 2, GFLAGS),
473 	GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
474 			RK3399_CLKGATE_CON(0), 3, GFLAGS),
475 
476 	COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
477 			RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
478 			RK3399_CLKGATE_CON(0), 4, GFLAGS),
479 	COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
480 			RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
481 			RK3399_CLKGATE_CON(0), 5, GFLAGS),
482 	COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
483 			RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
484 			RK3399_CLKGATE_CON(0), 6, GFLAGS),
485 
486 	GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
487 			RK3399_CLKGATE_CON(14), 12, GFLAGS),
488 	GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
489 			RK3399_CLKGATE_CON(14), 13, GFLAGS),
490 
491 	GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
492 			RK3399_CLKGATE_CON(14), 9, GFLAGS),
493 	GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
494 			RK3399_CLKGATE_CON(14), 10, GFLAGS),
495 	GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
496 			RK3399_CLKGATE_CON(14), 11, GFLAGS),
497 	GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
498 			RK3399_CLKGATE_CON(0), 7, GFLAGS),
499 
500 	/* big core */
501 	GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
502 			RK3399_CLKGATE_CON(1), 0, GFLAGS),
503 	GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
504 			RK3399_CLKGATE_CON(1), 1, GFLAGS),
505 	GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
506 			RK3399_CLKGATE_CON(1), 2, GFLAGS),
507 	GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
508 			RK3399_CLKGATE_CON(1), 3, GFLAGS),
509 
510 	COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
511 			RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
512 			RK3399_CLKGATE_CON(1), 4, GFLAGS),
513 	COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
514 			RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
515 			RK3399_CLKGATE_CON(1), 5, GFLAGS),
516 	COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
517 			RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
518 			RK3399_CLKGATE_CON(1), 6, GFLAGS),
519 
520 	GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
521 			RK3399_CLKGATE_CON(14), 5, GFLAGS),
522 	GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
523 			RK3399_CLKGATE_CON(14), 6, GFLAGS),
524 
525 	GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
526 			RK3399_CLKGATE_CON(14), 1, GFLAGS),
527 	GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
528 			RK3399_CLKGATE_CON(14), 3, GFLAGS),
529 	GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
530 			RK3399_CLKGATE_CON(14), 4, GFLAGS),
531 
532 	DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
533 			RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
534 
535 	GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
536 			RK3399_CLKGATE_CON(14), 2, GFLAGS),
537 
538 	GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
539 			RK3399_CLKGATE_CON(1), 7, GFLAGS),
540 
541 	/* gmac */
542 	GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
543 			RK3399_CLKGATE_CON(6), 9, GFLAGS),
544 	GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
545 			RK3399_CLKGATE_CON(6), 8, GFLAGS),
546 	COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
547 			RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
548 			RK3399_CLKGATE_CON(6), 10, GFLAGS),
549 
550 	GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
551 			RK3399_CLKGATE_CON(32), 0, GFLAGS),
552 	GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
553 			RK3399_CLKGATE_CON(32), 1, GFLAGS),
554 	GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
555 			RK3399_CLKGATE_CON(32), 4, GFLAGS),
556 
557 	COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
558 			RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
559 			RK3399_CLKGATE_CON(6), 11, GFLAGS),
560 	GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
561 			RK3399_CLKGATE_CON(32), 2, GFLAGS),
562 	GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
563 			RK3399_CLKGATE_CON(32), 3, GFLAGS),
564 
565 	COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
566 			RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
567 			RK3399_CLKGATE_CON(5), 5, GFLAGS),
568 
569 	MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
570 			RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
571 	GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
572 			RK3399_CLKGATE_CON(5), 6, GFLAGS),
573 	GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
574 			RK3399_CLKGATE_CON(5), 7, GFLAGS),
575 	GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
576 			RK3399_CLKGATE_CON(5), 8, GFLAGS),
577 	GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
578 			RK3399_CLKGATE_CON(5), 9, GFLAGS),
579 
580 	/* spdif */
581 	COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
582 			RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
583 			RK3399_CLKGATE_CON(8), 13, GFLAGS),
584 	COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
585 			RK3399_CLKSEL_CON(99), 0,
586 			RK3399_CLKGATE_CON(8), 14, GFLAGS,
587 			&rk3399_spdif_fracmux),
588 	GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
589 			RK3399_CLKGATE_CON(8), 15, GFLAGS),
590 
591 	COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
592 			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
593 			RK3399_CLKGATE_CON(10), 6, GFLAGS),
594 	/* i2s */
595 	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
596 			RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
597 			RK3399_CLKGATE_CON(8), 3, GFLAGS),
598 	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
599 			RK3399_CLKSEL_CON(96), 0,
600 			RK3399_CLKGATE_CON(8), 4, GFLAGS,
601 			&rk3399_i2s0_fracmux),
602 	GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
603 			RK3399_CLKGATE_CON(8), 5, GFLAGS),
604 
605 	COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
606 			RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
607 			RK3399_CLKGATE_CON(8), 6, GFLAGS),
608 	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
609 			RK3399_CLKSEL_CON(97), 0,
610 			RK3399_CLKGATE_CON(8), 7, GFLAGS,
611 			&rk3399_i2s1_fracmux),
612 	GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
613 			RK3399_CLKGATE_CON(8), 8, GFLAGS),
614 
615 	COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
616 			RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
617 			RK3399_CLKGATE_CON(8), 9, GFLAGS),
618 	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
619 			RK3399_CLKSEL_CON(98), 0,
620 			RK3399_CLKGATE_CON(8), 10, GFLAGS,
621 			&rk3399_i2s2_fracmux),
622 	GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
623 			RK3399_CLKGATE_CON(8), 11, GFLAGS),
624 
625 	MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
626 			RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
627 	COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
628 			RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
629 			RK3399_CLKGATE_CON(8), 12, GFLAGS),
630 
631 	/* uart */
632 	MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
633 			RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
634 	COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
635 			RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
636 			RK3399_CLKGATE_CON(9), 0, GFLAGS),
637 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
638 			RK3399_CLKSEL_CON(100), 0,
639 			RK3399_CLKGATE_CON(9), 1, GFLAGS,
640 			&rk3399_uart0_fracmux),
641 
642 	MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
643 			RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
644 	COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
645 			RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
646 			RK3399_CLKGATE_CON(9), 2, GFLAGS),
647 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
648 			RK3399_CLKSEL_CON(101), 0,
649 			RK3399_CLKGATE_CON(9), 3, GFLAGS,
650 			&rk3399_uart1_fracmux),
651 
652 	COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
653 			RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
654 			RK3399_CLKGATE_CON(9), 4, GFLAGS),
655 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
656 			RK3399_CLKSEL_CON(102), 0,
657 			RK3399_CLKGATE_CON(9), 5, GFLAGS,
658 			&rk3399_uart2_fracmux),
659 
660 	COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
661 			RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
662 			RK3399_CLKGATE_CON(9), 6, GFLAGS),
663 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0,
664 			RK3399_CLKSEL_CON(103), 0,
665 			RK3399_CLKGATE_CON(9), 7, GFLAGS,
666 			&rk3399_uart3_fracmux),
667 
668 	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
669 			RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
670 			RK3399_CLKGATE_CON(3), 4, GFLAGS),
671 
672 	GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
673 			RK3399_CLKGATE_CON(18), 10, GFLAGS),
674 	GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
675 			RK3399_CLKGATE_CON(18), 12, GFLAGS),
676 	GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
677 			RK3399_CLKGATE_CON(18), 15, GFLAGS),
678 	GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
679 			RK3399_CLKGATE_CON(19), 2, GFLAGS),
680 
681 	GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
682 			RK3399_CLKGATE_CON(4), 11, GFLAGS),
683 	GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
684 			RK3399_CLKGATE_CON(3), 5, GFLAGS),
685 	GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
686 			RK3399_CLKGATE_CON(3), 6, GFLAGS),
687 
688 	/* cci */
689 	GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
690 			RK3399_CLKGATE_CON(2), 0, GFLAGS),
691 	GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
692 			RK3399_CLKGATE_CON(2), 1, GFLAGS),
693 	GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
694 			RK3399_CLKGATE_CON(2), 2, GFLAGS),
695 	GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
696 			RK3399_CLKGATE_CON(2), 3, GFLAGS),
697 
698 	COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
699 			RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
700 			RK3399_CLKGATE_CON(2), 4, GFLAGS),
701 
702 	GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
703 			RK3399_CLKGATE_CON(15), 0, GFLAGS),
704 	GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
705 			RK3399_CLKGATE_CON(15), 1, GFLAGS),
706 	GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
707 			RK3399_CLKGATE_CON(15), 2, GFLAGS),
708 	GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
709 			RK3399_CLKGATE_CON(15), 3, GFLAGS),
710 	GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
711 			RK3399_CLKGATE_CON(15), 4, GFLAGS),
712 	GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
713 			RK3399_CLKGATE_CON(15), 7, GFLAGS),
714 
715 	GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
716 			RK3399_CLKGATE_CON(2), 5, GFLAGS),
717 	GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
718 			RK3399_CLKGATE_CON(2), 6, GFLAGS),
719 	COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
720 			RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
721 			RK3399_CLKGATE_CON(2), 7, GFLAGS),
722 
723 	GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
724 			RK3399_CLKGATE_CON(2), 8, GFLAGS),
725 	GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
726 			RK3399_CLKGATE_CON(2), 9, GFLAGS),
727 	GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
728 			RK3399_CLKGATE_CON(2), 10, GFLAGS),
729 	COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
730 			RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
731 	GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
732 			RK3399_CLKGATE_CON(15), 5, GFLAGS),
733 	GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
734 			RK3399_CLKGATE_CON(15), 6, GFLAGS),
735 
736 	/* vcodec */
737 	COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
738 			RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
739 			RK3399_CLKGATE_CON(4), 0, GFLAGS),
740 	COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
741 			RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
742 			RK3399_CLKGATE_CON(4), 1, GFLAGS),
743 	GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
744 			RK3399_CLKGATE_CON(17), 2, GFLAGS),
745 	GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
746 			RK3399_CLKGATE_CON(17), 3, GFLAGS),
747 
748 	GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
749 			RK3399_CLKGATE_CON(17), 0, GFLAGS),
750 	GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
751 			RK3399_CLKGATE_CON(17), 1, GFLAGS),
752 
753 	/* vdu */
754 	COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
755 			RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
756 			RK3399_CLKGATE_CON(4), 4, GFLAGS),
757 	COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
758 			RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
759 			RK3399_CLKGATE_CON(4), 5, GFLAGS),
760 
761 	COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
762 			RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
763 			RK3399_CLKGATE_CON(4), 2, GFLAGS),
764 	COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
765 			RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
766 			RK3399_CLKGATE_CON(4), 3, GFLAGS),
767 	GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
768 			RK3399_CLKGATE_CON(17), 10, GFLAGS),
769 	GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
770 			RK3399_CLKGATE_CON(17), 11, GFLAGS),
771 
772 	GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
773 			RK3399_CLKGATE_CON(17), 8, GFLAGS),
774 	GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
775 			RK3399_CLKGATE_CON(17), 9, GFLAGS),
776 
777 	/* iep */
778 	COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
779 			RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
780 			RK3399_CLKGATE_CON(4), 6, GFLAGS),
781 	COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
782 			RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
783 			RK3399_CLKGATE_CON(4), 7, GFLAGS),
784 	GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
785 			RK3399_CLKGATE_CON(16), 2, GFLAGS),
786 	GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
787 			RK3399_CLKGATE_CON(16), 3, GFLAGS),
788 
789 	GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
790 			RK3399_CLKGATE_CON(16), 0, GFLAGS),
791 	GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
792 			RK3399_CLKGATE_CON(16), 1, GFLAGS),
793 
794 	/* rga */
795 	COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
796 			RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
797 			RK3399_CLKGATE_CON(4), 10, GFLAGS),
798 
799 	COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
800 			RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
801 			RK3399_CLKGATE_CON(4), 8, GFLAGS),
802 	COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
803 			RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
804 			RK3399_CLKGATE_CON(4), 9, GFLAGS),
805 	GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
806 			RK3399_CLKGATE_CON(16), 10, GFLAGS),
807 	GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
808 			RK3399_CLKGATE_CON(16), 11, GFLAGS),
809 
810 	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
811 			RK3399_CLKGATE_CON(16), 8, GFLAGS),
812 	GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
813 			RK3399_CLKGATE_CON(16), 9, GFLAGS),
814 
815 	/* center */
816 	COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
817 			RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
818 			RK3399_CLKGATE_CON(3), 7, GFLAGS),
819 	GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
820 			RK3399_CLKGATE_CON(19), 0, GFLAGS),
821 	GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
822 			RK3399_CLKGATE_CON(19), 1, GFLAGS),
823 
824 	/* gpu */
825 	COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
826 			RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
827 			RK3399_CLKGATE_CON(13), 0, GFLAGS),
828 	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
829 			RK3399_CLKGATE_CON(30), 8, GFLAGS),
830 	GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
831 			RK3399_CLKGATE_CON(30), 10, GFLAGS),
832 	GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
833 			RK3399_CLKGATE_CON(30), 11, GFLAGS),
834 	GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
835 			RK3399_CLKGATE_CON(13), 1, GFLAGS),
836 
837 	/* perihp */
838 	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
839 			RK3399_CLKGATE_CON(5), 1, GFLAGS),
840 	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
841 			RK3399_CLKGATE_CON(5), 0, GFLAGS),
842 	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
843 			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
844 			RK3399_CLKGATE_CON(5), 2, GFLAGS),
845 	COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
846 			RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
847 			RK3399_CLKGATE_CON(5), 3, GFLAGS),
848 	COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
849 			RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
850 			RK3399_CLKGATE_CON(5), 4, GFLAGS),
851 
852 	GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
853 			RK3399_CLKGATE_CON(20), 2, GFLAGS),
854 	GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
855 			RK3399_CLKGATE_CON(20), 10, GFLAGS),
856 	GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
857 			RK3399_CLKGATE_CON(20), 12, GFLAGS),
858 
859 	GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
860 			RK3399_CLKGATE_CON(20), 5, GFLAGS),
861 	GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
862 			RK3399_CLKGATE_CON(20), 6, GFLAGS),
863 	GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
864 			RK3399_CLKGATE_CON(20), 7, GFLAGS),
865 	GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
866 			RK3399_CLKGATE_CON(20), 8, GFLAGS),
867 	GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
868 			RK3399_CLKGATE_CON(20), 9, GFLAGS),
869 	GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
870 			RK3399_CLKGATE_CON(20), 13, GFLAGS),
871 	GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
872 			RK3399_CLKGATE_CON(20), 15, GFLAGS),
873 
874 	GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
875 			RK3399_CLKGATE_CON(20), 4, GFLAGS),
876 	GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
877 			RK3399_CLKGATE_CON(20), 11, GFLAGS),
878 	GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
879 			RK3399_CLKGATE_CON(20), 14, GFLAGS),
880 	GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
881 			RK3399_CLKGATE_CON(31), 8, GFLAGS),
882 
883 	/* sdio & sdmmc */
884 	COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
885 			RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
886 			RK3399_CLKGATE_CON(12), 13, GFLAGS),
887 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
888 			RK3399_CLKGATE_CON(33), 8, GFLAGS),
889 	GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
890 			RK3399_CLKGATE_CON(33), 9, GFLAGS),
891 
892 	COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
893 			RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
894 			RK3399_CLKGATE_CON(6), 0, GFLAGS),
895 
896 	COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
897 			RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
898 			RK3399_CLKGATE_CON(6), 1, GFLAGS),
899 
900 	MMC(SCLK_SDMMC_DRV,     "sdmmc_drv",    "clk_sdmmc", RK3399_SDMMC_CON0, 1),
901 	MMC(SCLK_SDMMC_SAMPLE,  "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
902 
903 	MMC(SCLK_SDIO_DRV,      "sdio_drv",    "clk_sdio",  RK3399_SDIO_CON0,  1),
904 	MMC(SCLK_SDIO_SAMPLE,   "sdio_sample", "clk_sdio",  RK3399_SDIO_CON1,  1),
905 
906 	/* pcie */
907 	COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
908 			RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
909 			RK3399_CLKGATE_CON(6), 2, GFLAGS),
910 
911 	COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
912 			RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
913 			RK3399_CLKGATE_CON(12), 6, GFLAGS),
914 	MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
915 			RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
916 
917 	COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
918 			RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
919 			RK3399_CLKGATE_CON(6), 3, GFLAGS),
920 	MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
921 			RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
922 
923 	/* emmc */
924 	COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
925 			RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
926 			RK3399_CLKGATE_CON(6), 14, GFLAGS),
927 
928 	GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
929 			RK3399_CLKGATE_CON(6), 13, GFLAGS),
930 	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
931 			RK3399_CLKGATE_CON(6), 12, GFLAGS),
932 	COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
933 			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
934 	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
935 			RK3399_CLKGATE_CON(32), 8, GFLAGS),
936 	GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
937 			RK3399_CLKGATE_CON(32), 9, GFLAGS),
938 	GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
939 			RK3399_CLKGATE_CON(32), 10, GFLAGS),
940 
941 	/* perilp0 */
942 	GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
943 			RK3399_CLKGATE_CON(7), 1, GFLAGS),
944 	GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
945 			RK3399_CLKGATE_CON(7), 0, GFLAGS),
946 	COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
947 			RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
948 			RK3399_CLKGATE_CON(7), 2, GFLAGS),
949 	COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
950 			RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
951 			RK3399_CLKGATE_CON(7), 3, GFLAGS),
952 	COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
953 			RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
954 			RK3399_CLKGATE_CON(7), 4, GFLAGS),
955 
956 	/* aclk_perilp0 gates */
957 	GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
958 	GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
959 	GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
960 	GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
961 	GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
962 	GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
963 	GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
964 	GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
965 	GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
966 	GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
967 	GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
968 	GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
969 
970 	/* hclk_perilp0 gates */
971 	GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
972 	GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
973 	GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
974 	GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
975 	GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
976 	GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
977 
978 	/* pclk_perilp0 gates */
979 	GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
980 
981 	/* crypto */
982 	COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
983 			RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
984 			RK3399_CLKGATE_CON(7), 7, GFLAGS),
985 
986 	COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
987 			RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
988 			RK3399_CLKGATE_CON(7), 8, GFLAGS),
989 
990 	/* cm0s_perilp */
991 	GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
992 			RK3399_CLKGATE_CON(7), 6, GFLAGS),
993 	GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
994 			RK3399_CLKGATE_CON(7), 5, GFLAGS),
995 	COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
996 			RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
997 			RK3399_CLKGATE_CON(7), 9, GFLAGS),
998 
999 	/* fclk_cm0s gates */
1000 	GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
1001 	GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
1002 	GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
1003 	GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
1004 	GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1005 
1006 	/* perilp1 */
1007 	GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
1008 			RK3399_CLKGATE_CON(8), 1, GFLAGS),
1009 	GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
1010 			RK3399_CLKGATE_CON(8), 0, GFLAGS),
1011 	COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1012 			RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1013 	COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1014 			RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1015 			RK3399_CLKGATE_CON(8), 2, GFLAGS),
1016 
1017 	/* hclk_perilp1 gates */
1018 	GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1019 	GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1020 	GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1021 	GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1022 	GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1023 	GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1024 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1025 	GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1026 	GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1027 
1028 	/* pclk_perilp1 gates */
1029 	GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1030 	GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1031 	GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1032 	GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1033 	GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1034 	GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1035 	GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1036 	GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1037 	GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1038 	GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1039 	GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1040 	GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1041 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1042 	GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1043 	GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1044 	GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1045 	GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1046 	GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1047 	GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1048 	GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1049 	GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1050 
1051 	/* saradc */
1052 	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1053 			RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1054 			RK3399_CLKGATE_CON(9), 11, GFLAGS),
1055 
1056 	/* tsadc */
1057 	COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1058 			RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1059 			RK3399_CLKGATE_CON(9), 10, GFLAGS),
1060 
1061 	/* cif_testout */
1062 	MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1063 			RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1064 	COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0,
1065 			RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1066 			RK3399_CLKGATE_CON(13), 14, GFLAGS),
1067 
1068 	MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1069 			RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1070 	COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0,
1071 			RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1072 			RK3399_CLKGATE_CON(13), 15, GFLAGS),
1073 
1074 	/* vio */
1075 	COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1076 			RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1077 			RK3399_CLKGATE_CON(11), 0, GFLAGS),
1078 	COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1079 			RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1080 			RK3399_CLKGATE_CON(11), 1, GFLAGS),
1081 
1082 	GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1083 			RK3399_CLKGATE_CON(29), 0, GFLAGS),
1084 
1085 	GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1086 			RK3399_CLKGATE_CON(29), 1, GFLAGS),
1087 	GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1088 			RK3399_CLKGATE_CON(29), 2, GFLAGS),
1089 	GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1090 			RK3399_CLKGATE_CON(29), 12, GFLAGS),
1091 
1092 	/* hdcp */
1093 	COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1094 			RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1095 			RK3399_CLKGATE_CON(11), 12, GFLAGS),
1096 	COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1097 			RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1098 			RK3399_CLKGATE_CON(11), 3, GFLAGS),
1099 	COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1100 			RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1101 			RK3399_CLKGATE_CON(11), 10, GFLAGS),
1102 
1103 	GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1104 			RK3399_CLKGATE_CON(29), 4, GFLAGS),
1105 	GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1106 			RK3399_CLKGATE_CON(29), 10, GFLAGS),
1107 
1108 	GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1109 			RK3399_CLKGATE_CON(29), 5, GFLAGS),
1110 	GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1111 			RK3399_CLKGATE_CON(29), 9, GFLAGS),
1112 
1113 	GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1114 			RK3399_CLKGATE_CON(29), 3, GFLAGS),
1115 	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1116 			RK3399_CLKGATE_CON(29), 6, GFLAGS),
1117 	GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1118 			RK3399_CLKGATE_CON(29), 7, GFLAGS),
1119 	GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1120 			RK3399_CLKGATE_CON(29), 8, GFLAGS),
1121 	GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1122 			RK3399_CLKGATE_CON(29), 11, GFLAGS),
1123 
1124 	/* edp */
1125 	COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1126 			RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1127 			RK3399_CLKGATE_CON(11), 8, GFLAGS),
1128 
1129 	COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1130 			RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
1131 			RK3399_CLKGATE_CON(11), 11, GFLAGS),
1132 	GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1133 			RK3399_CLKGATE_CON(32), 12, GFLAGS),
1134 	GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1135 			RK3399_CLKGATE_CON(32), 13, GFLAGS),
1136 
1137 	/* hdmi */
1138 	GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1139 			RK3399_CLKGATE_CON(11), 6, GFLAGS),
1140 
1141 	COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1142 			RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1143 			RK3399_CLKGATE_CON(11), 7, GFLAGS),
1144 
1145 	/* vop0 */
1146 	COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
1147 			RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1148 			RK3399_CLKGATE_CON(10), 8, GFLAGS),
1149 	COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1150 			RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1151 			RK3399_CLKGATE_CON(10), 9, GFLAGS),
1152 
1153 	GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1154 			RK3399_CLKGATE_CON(28), 3, GFLAGS),
1155 	GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1156 			RK3399_CLKGATE_CON(28), 1, GFLAGS),
1157 
1158 	GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1159 			RK3399_CLKGATE_CON(28), 2, GFLAGS),
1160 	GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1161 			RK3399_CLKGATE_CON(28), 0, GFLAGS),
1162 
1163 	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1164 			RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1165 			RK3399_CLKGATE_CON(10), 12, GFLAGS),
1166 
1167 	COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
1168 			RK3399_CLKSEL_CON(106), 0,
1169 			&rk3399_dclk_vop0_fracmux),
1170 
1171 	COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
1172 			RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1173 			RK3399_CLKGATE_CON(10), 14, GFLAGS),
1174 
1175 	/* vop1 */
1176 	COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
1177 			RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1178 			RK3399_CLKGATE_CON(10), 10, GFLAGS),
1179 	COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1180 			RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1181 			RK3399_CLKGATE_CON(10), 11, GFLAGS),
1182 
1183 	GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1184 			RK3399_CLKGATE_CON(28), 7, GFLAGS),
1185 	GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1186 			RK3399_CLKGATE_CON(28), 5, GFLAGS),
1187 
1188 	GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1189 			RK3399_CLKGATE_CON(28), 6, GFLAGS),
1190 	GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1191 			RK3399_CLKGATE_CON(28), 4, GFLAGS),
1192 
1193 	COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1194 			RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1195 			RK3399_CLKGATE_CON(10), 13, GFLAGS),
1196 
1197 	COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
1198 			RK3399_CLKSEL_CON(107), 0,
1199 			&rk3399_dclk_vop1_fracmux),
1200 
1201 	COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1202 			RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1203 			RK3399_CLKGATE_CON(10), 15, GFLAGS),
1204 
1205 	/* isp */
1206 	COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1207 			RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1208 			RK3399_CLKGATE_CON(12), 8, GFLAGS),
1209 	COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
1210 			RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1211 			RK3399_CLKGATE_CON(12), 9, GFLAGS),
1212 
1213 	GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1214 			RK3399_CLKGATE_CON(27), 1, GFLAGS),
1215 	GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1216 			RK3399_CLKGATE_CON(27), 5, GFLAGS),
1217 	GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
1218 			RK3399_CLKGATE_CON(27), 7, GFLAGS),
1219 
1220 	GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1221 			RK3399_CLKGATE_CON(27), 0, GFLAGS),
1222 	GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1223 			RK3399_CLKGATE_CON(27), 4, GFLAGS),
1224 
1225 	COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1226 			RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1227 			RK3399_CLKGATE_CON(11), 4, GFLAGS),
1228 
1229 	COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1230 			RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1231 			RK3399_CLKGATE_CON(12), 10, GFLAGS),
1232 	COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
1233 			RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1234 			RK3399_CLKGATE_CON(12), 11, GFLAGS),
1235 
1236 	GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1237 			RK3399_CLKGATE_CON(27), 3, GFLAGS),
1238 
1239 	GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1240 			RK3399_CLKGATE_CON(27), 2, GFLAGS),
1241 	GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
1242 			RK3399_CLKGATE_CON(27), 8, GFLAGS),
1243 
1244 	COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1245 			RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1246 			RK3399_CLKGATE_CON(11), 5, GFLAGS),
1247 
1248 	/*
1249 	 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1250 	 * so we ignore the mux and make clocks nodes as following,
1251 	 *
1252 	 * pclkin_cifinv --|-------\
1253 	 *                 |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1254 	 * pclkin_cif    --|-------/
1255 	 */
1256 	GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1257 			RK3399_CLKGATE_CON(27), 6, GFLAGS),
1258 
1259 	/* cif */
1260 	COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1261 			RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1262 			RK3399_CLKGATE_CON(10), 7, GFLAGS),
1263 
1264 	COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1265 			 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1266 
1267 	/* gic */
1268 	COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1269 			RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1270 			RK3399_CLKGATE_CON(12), 12, GFLAGS),
1271 
1272 	GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1273 	GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1274 	GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1275 	GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1276 	GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1277 	GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1278 
1279 	/* alive */
1280 	/* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1281 	DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1282 			RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1283 
1284 	GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1285 	GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1286 	GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1287 	GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1288 	GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1289 
1290 	GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1291 	GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1292 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1293 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1294 	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1295 	GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1296 	GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1297 	GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1298 	GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1299 
1300 	/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1301 	SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
1302 
1303 	GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1304 	GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1305 
1306 	GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1307 	GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1308 	GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1309 	GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1310 
1311 	/* testout */
1312 	MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1313 			RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1314 	COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
1315 			RK3399_CLKSEL_CON(105), 0,
1316 			RK3399_CLKGATE_CON(13), 9, GFLAGS),
1317 
1318 	DIV(0, "clk_test_24m", "xin24m", 0,
1319 			RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1320 
1321 	/* spi */
1322 	COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1323 			RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1324 			RK3399_CLKGATE_CON(9), 12, GFLAGS),
1325 
1326 	COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1327 			RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1328 			RK3399_CLKGATE_CON(9), 13, GFLAGS),
1329 
1330 	COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1331 			RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1332 			RK3399_CLKGATE_CON(9), 14, GFLAGS),
1333 
1334 	COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1335 			RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1336 			RK3399_CLKGATE_CON(9), 15, GFLAGS),
1337 
1338 	COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1339 			RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1340 			RK3399_CLKGATE_CON(13), 13, GFLAGS),
1341 
1342 	/* i2c */
1343 	COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1344 			RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1345 			RK3399_CLKGATE_CON(10), 0, GFLAGS),
1346 
1347 	COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1348 			RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1349 			RK3399_CLKGATE_CON(10), 2, GFLAGS),
1350 
1351 	COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1352 			RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1353 			RK3399_CLKGATE_CON(10), 4, GFLAGS),
1354 
1355 	COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1356 			RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1357 			RK3399_CLKGATE_CON(10), 1, GFLAGS),
1358 
1359 	COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1360 			RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1361 			RK3399_CLKGATE_CON(10), 3, GFLAGS),
1362 
1363 	COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1364 			RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1365 			RK3399_CLKGATE_CON(10), 5, GFLAGS),
1366 
1367 	/* timer */
1368 	GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1369 	GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1370 	GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1371 	GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1372 	GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1373 	GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1374 	GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1375 	GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1376 	GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1377 	GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1378 	GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1379 	GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1380 
1381 	/* clk_test */
1382 	/* clk_test_pre is controlled by CRU_MISC_CON[3] */
1383 	COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1384 			RK3399_CLKSEL_CON(58), 0, 5, DFLAGS,
1385 			RK3399_CLKGATE_CON(13), 11, GFLAGS),
1386 
1387 	/* ddrc */
1388 	GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
1389 	     0, GFLAGS),
1390 	GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
1391 	     1, GFLAGS),
1392 	GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
1393 	     2, GFLAGS),
1394 	GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
1395 	     3, GFLAGS),
1396 	COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0,
1397 		       RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
1398 };
1399 
1400 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1401 	/*
1402 	 * PMU CRU Clock-Architecture
1403 	 */
1404 
1405 	GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1406 			RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1407 
1408 	COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1409 			RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1410 
1411 	COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1412 			RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1413 			RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1414 
1415 	COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1416 			RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1417 			RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1418 
1419 	COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0,
1420 			RK3399_PMU_CLKSEL_CON(7), 0,
1421 			&rk3399_pmuclk_wifi_fracmux),
1422 
1423 	MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1424 			RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1425 
1426 	COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1427 			RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1428 			RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1429 
1430 	COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1431 			RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1432 			RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1433 
1434 	COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1435 			RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1436 			RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1437 
1438 	DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1439 			RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1440 	MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1441 			RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1442 
1443 	COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
1444 			RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1445 			RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1446 
1447 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,
1448 			RK3399_PMU_CLKSEL_CON(6), 0,
1449 			RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1450 			&rk3399_uart4_pmu_fracmux),
1451 
1452 	DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1453 			RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1454 
1455 	/* pmu clock gates */
1456 	GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1457 	GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1458 
1459 	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1460 
1461 	GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1462 	GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1463 	GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1464 	GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1465 	GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1466 	GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1467 	GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1468 	GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1469 	GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1470 	GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1471 	GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1472 	GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1473 	GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1474 	GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1475 	GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1476 	GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1477 
1478 	GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1479 	GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1480 	GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1481 	GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1482 	GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1483 };
1484 
1485 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1486 	"aclk_cci_pre",
1487 	"aclk_gic",
1488 	"aclk_gic_noc",
1489 	"aclk_hdcp_noc",
1490 	"hclk_hdcp_noc",
1491 	"pclk_hdcp_noc",
1492 	"pclk_perilp0",
1493 	"pclk_perilp0",
1494 	"hclk_perilp0",
1495 	"hclk_perilp0_noc",
1496 	"pclk_perilp1",
1497 	"pclk_perilp1_noc",
1498 	"pclk_perihp",
1499 	"pclk_perihp_noc",
1500 	"hclk_perihp",
1501 	"aclk_perihp",
1502 	"aclk_perihp_noc",
1503 	"aclk_perilp0",
1504 	"aclk_perilp0_noc",
1505 	"hclk_perilp1",
1506 	"hclk_perilp1_noc",
1507 	"aclk_dmac0_perilp",
1508 	"aclk_emmc_noc",
1509 	"gpll_hclk_perilp1_src",
1510 	"gpll_aclk_perilp0_src",
1511 	"gpll_aclk_perihp_src",
1512 	"aclk_vio_noc",
1513 
1514 	/* ddrc */
1515 	"sclk_ddrc"
1516 };
1517 
1518 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1519 	"ppll",
1520 	"pclk_pmu_src",
1521 	"fclk_cm0s_src_pmu",
1522 	"clk_timer_src_pmu",
1523 	"pclk_rkpwm_pmu",
1524 };
1525 
1526 static void __init rk3399_clk_init(struct device_node *np)
1527 {
1528 	struct rockchip_clk_provider *ctx;
1529 	void __iomem *reg_base;
1530 
1531 	reg_base = of_iomap(np, 0);
1532 	if (!reg_base) {
1533 		pr_err("%s: could not map cru region\n", __func__);
1534 		return;
1535 	}
1536 
1537 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1538 	if (IS_ERR(ctx)) {
1539 		pr_err("%s: rockchip clk init failed\n", __func__);
1540 		iounmap(reg_base);
1541 		return;
1542 	}
1543 
1544 	rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1545 				   ARRAY_SIZE(rk3399_pll_clks), -1);
1546 
1547 	rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1548 				  ARRAY_SIZE(rk3399_clk_branches));
1549 
1550 	rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1551 				      ARRAY_SIZE(rk3399_cru_critical_clocks));
1552 
1553 	rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1554 			mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1555 			&rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1556 			ARRAY_SIZE(rk3399_cpuclkl_rates));
1557 
1558 	rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1559 			mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1560 			&rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1561 			ARRAY_SIZE(rk3399_cpuclkb_rates));
1562 
1563 	rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1564 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
1565 
1566 	rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1567 
1568 	rockchip_clk_of_add_provider(np, ctx);
1569 }
1570 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1571 
1572 static void __init rk3399_pmu_clk_init(struct device_node *np)
1573 {
1574 	struct rockchip_clk_provider *ctx;
1575 	void __iomem *reg_base;
1576 
1577 	reg_base = of_iomap(np, 0);
1578 	if (!reg_base) {
1579 		pr_err("%s: could not map cru pmu region\n", __func__);
1580 		return;
1581 	}
1582 
1583 	ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1584 	if (IS_ERR(ctx)) {
1585 		pr_err("%s: rockchip pmu clk init failed\n", __func__);
1586 		iounmap(reg_base);
1587 		return;
1588 	}
1589 
1590 	rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1591 				   ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1592 
1593 	rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1594 				  ARRAY_SIZE(rk3399_clk_pmu_branches));
1595 
1596 	rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1597 				  ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1598 
1599 	rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1600 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
1601 
1602 	rockchip_clk_of_add_provider(np, ctx);
1603 }
1604 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
1605 
1606 struct clk_rk3399_inits {
1607 	void (*inits)(struct device_node *np);
1608 };
1609 
1610 static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
1611 	.inits = rk3399_pmu_clk_init,
1612 };
1613 
1614 static const struct clk_rk3399_inits clk_rk3399_cru_init = {
1615 	.inits = rk3399_clk_init,
1616 };
1617 
1618 static const struct of_device_id clk_rk3399_match_table[] = {
1619 	{
1620 		.compatible = "rockchip,rk3399-cru",
1621 		.data = &clk_rk3399_cru_init,
1622 	},  {
1623 		.compatible = "rockchip,rk3399-pmucru",
1624 		.data = &clk_rk3399_pmucru_init,
1625 	},
1626 	{ }
1627 };
1628 MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
1629 
1630 static int __init clk_rk3399_probe(struct platform_device *pdev)
1631 {
1632 	struct device_node *np = pdev->dev.of_node;
1633 	const struct of_device_id *match;
1634 	const struct clk_rk3399_inits *init_data;
1635 
1636 	match = of_match_device(clk_rk3399_match_table, &pdev->dev);
1637 	if (!match || !match->data)
1638 		return -EINVAL;
1639 
1640 	init_data = match->data;
1641 	if (init_data->inits)
1642 		init_data->inits(np);
1643 
1644 	return 0;
1645 }
1646 
1647 static struct platform_driver clk_rk3399_driver = {
1648 	.driver		= {
1649 		.name	= "clk-rk3399",
1650 		.of_match_table = clk_rk3399_match_table,
1651 		.suppress_bind_attrs = true,
1652 	},
1653 };
1654 builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
1655 
1656 MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
1657 MODULE_LICENSE("GPL");
1658 MODULE_ALIAS("platform:clk-rk3399");
1659