1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Xing Zheng <zhengxing@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 #include "clk.h" 23 24 enum rk3399_plls { 25 lpll, bpll, dpll, cpll, gpll, npll, vpll, 26 }; 27 28 enum rk3399_pmu_plls { 29 ppll, 30 }; 31 32 static struct rockchip_pll_rate_table rk3399_pll_rates[] = { 33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 80 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 90 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 95 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 96 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 97 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 98 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 99 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 100 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), 101 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 102 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), 103 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 104 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), 105 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), 106 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), 107 { /* sentinel */ }, 108 }; 109 110 /* CRU parents */ 111 PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 112 113 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src", 114 "clk_core_l_bpll_src", 115 "clk_core_l_dpll_src", 116 "clk_core_l_gpll_src" }; 117 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", 118 "clk_core_b_bpll_src", 119 "clk_core_b_dpll_src", 120 "clk_core_b_gpll_src" }; 121 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", 122 "gpll_aclk_cci_src", 123 "npll_aclk_cci_src", 124 "vpll_aclk_cci_src" }; 125 PNAME(mux_cci_trace_p) = { "cpll_cci_trace", 126 "gpll_cci_trace" }; 127 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", 128 "npll_cs"}; 129 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", 130 "gpll_aclk_perihp_src" }; 131 132 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 133 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; 134 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" }; 135 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" }; 136 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; 137 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", 138 "ppll" }; 139 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", 140 "xin24m" }; 141 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", 142 "clk_usbphy_480m" }; 143 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", 144 "npll", "upll" }; 145 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", 146 "upll", "xin24m" }; 147 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", 148 "ppll", "upll", "xin24m" }; 149 150 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; 151 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", 152 "npll" }; 153 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", 154 "xin24m" }; 155 156 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", 157 "dclk_vop0_frac" }; 158 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", 159 "dclk_vop1_frac" }; 160 161 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" }; 162 163 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; 164 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; 165 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", 166 "cpll", "gpll" }; 167 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", 168 "clk_pcie_core_phy" }; 169 170 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", 171 "gpll_aclk_emmc_src" }; 172 173 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", 174 "gpll_aclk_perilp0_src" }; 175 176 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", 177 "gpll_fclk_cm0s_src" }; 178 179 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", 180 "gpll_hclk_perilp1_src" }; 181 182 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; 183 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; 184 185 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", 186 "clk_usbphy1_480m_src" }; 187 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", 188 "gpll_aclk_gmac_src" }; 189 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; 190 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", 191 "clkin_i2s", "xin12m" }; 192 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", 193 "clkin_i2s", "xin12m" }; 194 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", 195 "clkin_i2s", "xin12m" }; 196 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", 197 "clkin_i2s", "xin12m" }; 198 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", 199 "clk_i2s2" }; 200 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; 201 202 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 203 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 204 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 205 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 206 207 /* PMU CRU parents */ 208 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; 209 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 210 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; 211 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; 212 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", 213 "xin24m" }; 214 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; 215 216 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { 217 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), 218 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates), 219 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8), 220 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates), 221 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), 222 RK3399_PLL_CON(19), 8, 31, 0, NULL), 223 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), 224 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 225 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), 226 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 227 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), 228 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 229 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), 230 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 231 }; 232 233 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { 234 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0), 235 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 236 }; 237 238 #define MFLAGS CLK_MUX_HIWORD_MASK 239 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 240 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 241 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 242 243 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata = 244 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, 245 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS); 246 247 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata = 248 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, 249 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS); 250 251 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata = 252 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, 253 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS); 254 255 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata = 256 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, 257 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS); 258 259 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata = 260 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 261 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS); 262 263 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata = 264 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 265 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS); 266 267 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata = 268 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 269 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS); 270 271 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata = 272 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, 273 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS); 274 275 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = 276 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT, 277 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); 278 279 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = 280 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, 281 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); 282 283 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = 284 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT, 285 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS); 286 287 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata = 288 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, 289 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS); 290 291 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = { 292 .core_reg = RK3399_CLKSEL_CON(0), 293 .div_core_shift = 0, 294 .div_core_mask = 0x1f, 295 .mux_core_alt = 3, 296 .mux_core_main = 0, 297 .mux_core_shift = 6, 298 .mux_core_mask = 0x3, 299 }; 300 301 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { 302 .core_reg = RK3399_CLKSEL_CON(2), 303 .div_core_shift = 0, 304 .div_core_mask = 0x1f, 305 .mux_core_alt = 3, 306 .mux_core_main = 1, 307 .mux_core_shift = 6, 308 .mux_core_mask = 0x3, 309 }; 310 311 #define RK3399_DIV_ACLKM_MASK 0x1f 312 #define RK3399_DIV_ACLKM_SHIFT 8 313 #define RK3399_DIV_ATCLK_MASK 0x1f 314 #define RK3399_DIV_ATCLK_SHIFT 0 315 #define RK3399_DIV_PCLK_DBG_MASK 0x1f 316 #define RK3399_DIV_PCLK_DBG_SHIFT 8 317 318 #define RK3399_CLKSEL0(_offs, _aclkm) \ 319 { \ 320 .reg = RK3399_CLKSEL_CON(0 + _offs), \ 321 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \ 322 RK3399_DIV_ACLKM_SHIFT), \ 323 } 324 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \ 325 { \ 326 .reg = RK3399_CLKSEL_CON(1 + _offs), \ 327 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \ 328 RK3399_DIV_ATCLK_SHIFT) | \ 329 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \ 330 RK3399_DIV_PCLK_DBG_SHIFT), \ 331 } 332 333 /* cluster_l: aclkm in clksel0, rest in clksel1 */ 334 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \ 335 { \ 336 .prate = _prate##U, \ 337 .divs = { \ 338 RK3399_CLKSEL0(0, _aclkm), \ 339 RK3399_CLKSEL1(0, _atclk, _pdbg), \ 340 }, \ 341 } 342 343 /* cluster_b: aclkm in clksel2, rest in clksel3 */ 344 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \ 345 { \ 346 .prate = _prate##U, \ 347 .divs = { \ 348 RK3399_CLKSEL0(2, _aclkm), \ 349 RK3399_CLKSEL1(2, _atclk, _pdbg), \ 350 }, \ 351 } 352 353 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { 354 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), 355 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), 356 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), 357 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), 358 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), 359 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6), 360 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), 361 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5), 362 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4), 363 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3), 364 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3), 365 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2), 366 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1), 367 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1), 368 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1), 369 }; 370 371 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { 372 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), 373 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), 374 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), 375 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), 376 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), 377 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), 378 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8), 379 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), 380 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7), 381 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), 382 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6), 383 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), 384 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5), 385 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), 386 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4), 387 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3), 388 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3), 389 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2), 390 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1), 391 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1), 392 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1), 393 }; 394 395 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 396 /* 397 * CRU Clock-Architecture 398 */ 399 400 /* usbphy */ 401 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED, 402 RK3399_CLKGATE_CON(6), 5, GFLAGS), 403 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED, 404 RK3399_CLKGATE_CON(6), 6, GFLAGS), 405 406 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED, 407 RK3399_CLKGATE_CON(13), 12, GFLAGS), 408 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED, 409 RK3399_CLKGATE_CON(13), 12, GFLAGS), 410 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED, 411 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS), 412 413 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0, 414 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS), 415 416 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0, 417 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS, 418 RK3399_CLKGATE_CON(6), 4, GFLAGS), 419 420 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0, 421 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, 422 RK3399_CLKGATE_CON(12), 0, GFLAGS), 423 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED, 424 RK3399_CLKGATE_CON(30), 0, GFLAGS), 425 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0, 426 RK3399_CLKGATE_CON(30), 1, GFLAGS), 427 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0, 428 RK3399_CLKGATE_CON(30), 2, GFLAGS), 429 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0, 430 RK3399_CLKGATE_CON(30), 3, GFLAGS), 431 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0, 432 RK3399_CLKGATE_CON(30), 4, GFLAGS), 433 434 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, 435 RK3399_CLKGATE_CON(12), 1, GFLAGS), 436 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, 437 RK3399_CLKGATE_CON(12), 2, GFLAGS), 438 439 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0, 440 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS, 441 RK3399_CLKGATE_CON(12), 3, GFLAGS), 442 443 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0, 444 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS, 445 RK3399_CLKGATE_CON(12), 4, GFLAGS), 446 447 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0, 448 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS, 449 RK3399_CLKGATE_CON(13), 4, GFLAGS), 450 451 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, 452 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS, 453 RK3399_CLKGATE_CON(13), 5, GFLAGS), 454 455 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0, 456 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS, 457 RK3399_CLKGATE_CON(13), 6, GFLAGS), 458 459 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, 460 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS, 461 RK3399_CLKGATE_CON(13), 7, GFLAGS), 462 463 /* little core */ 464 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED, 465 RK3399_CLKGATE_CON(0), 0, GFLAGS), 466 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED, 467 RK3399_CLKGATE_CON(0), 1, GFLAGS), 468 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED, 469 RK3399_CLKGATE_CON(0), 2, GFLAGS), 470 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED, 471 RK3399_CLKGATE_CON(0), 3, GFLAGS), 472 473 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED, 474 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 475 RK3399_CLKGATE_CON(0), 4, GFLAGS), 476 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED, 477 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 478 RK3399_CLKGATE_CON(0), 5, GFLAGS), 479 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED, 480 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 481 RK3399_CLKGATE_CON(0), 6, GFLAGS), 482 483 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED, 484 RK3399_CLKGATE_CON(14), 12, GFLAGS), 485 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, 486 RK3399_CLKGATE_CON(14), 13, GFLAGS), 487 488 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, 489 RK3399_CLKGATE_CON(14), 9, GFLAGS), 490 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED, 491 RK3399_CLKGATE_CON(14), 10, GFLAGS), 492 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED, 493 RK3399_CLKGATE_CON(14), 11, GFLAGS), 494 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED, 495 RK3399_CLKGATE_CON(0), 7, GFLAGS), 496 497 /* big core */ 498 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED, 499 RK3399_CLKGATE_CON(1), 0, GFLAGS), 500 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED, 501 RK3399_CLKGATE_CON(1), 1, GFLAGS), 502 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED, 503 RK3399_CLKGATE_CON(1), 2, GFLAGS), 504 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED, 505 RK3399_CLKGATE_CON(1), 3, GFLAGS), 506 507 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED, 508 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 509 RK3399_CLKGATE_CON(1), 4, GFLAGS), 510 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED, 511 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 512 RK3399_CLKGATE_CON(1), 5, GFLAGS), 513 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED, 514 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 515 RK3399_CLKGATE_CON(1), 6, GFLAGS), 516 517 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED, 518 RK3399_CLKGATE_CON(14), 5, GFLAGS), 519 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, 520 RK3399_CLKGATE_CON(14), 6, GFLAGS), 521 522 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, 523 RK3399_CLKGATE_CON(14), 1, GFLAGS), 524 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED, 525 RK3399_CLKGATE_CON(14), 3, GFLAGS), 526 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED, 527 RK3399_CLKGATE_CON(14), 4, GFLAGS), 528 529 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 530 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY), 531 532 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 533 RK3399_CLKGATE_CON(14), 2, GFLAGS), 534 535 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED, 536 RK3399_CLKGATE_CON(1), 7, GFLAGS), 537 538 /* gmac */ 539 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED, 540 RK3399_CLKGATE_CON(6), 9, GFLAGS), 541 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED, 542 RK3399_CLKGATE_CON(6), 8, GFLAGS), 543 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0, 544 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS, 545 RK3399_CLKGATE_CON(6), 10, GFLAGS), 546 547 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, 548 RK3399_CLKGATE_CON(32), 0, GFLAGS), 549 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 550 RK3399_CLKGATE_CON(32), 1, GFLAGS), 551 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0, 552 RK3399_CLKGATE_CON(32), 4, GFLAGS), 553 554 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, 555 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS, 556 RK3399_CLKGATE_CON(6), 11, GFLAGS), 557 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, 558 RK3399_CLKGATE_CON(32), 2, GFLAGS), 559 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED, 560 RK3399_CLKGATE_CON(32), 3, GFLAGS), 561 562 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0, 563 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, 564 RK3399_CLKGATE_CON(5), 5, GFLAGS), 565 566 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT, 567 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS), 568 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0, 569 RK3399_CLKGATE_CON(5), 6, GFLAGS), 570 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0, 571 RK3399_CLKGATE_CON(5), 7, GFLAGS), 572 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0, 573 RK3399_CLKGATE_CON(5), 8, GFLAGS), 574 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0, 575 RK3399_CLKGATE_CON(5), 9, GFLAGS), 576 577 /* spdif */ 578 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, 579 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, 580 RK3399_CLKGATE_CON(8), 13, GFLAGS), 581 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT, 582 RK3399_CLKSEL_CON(99), 0, 583 RK3399_CLKGATE_CON(8), 14, GFLAGS, 584 &rk3399_spdif_fracmux), 585 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT, 586 RK3399_CLKGATE_CON(8), 15, GFLAGS), 587 588 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, 589 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS, 590 RK3399_CLKGATE_CON(10), 6, GFLAGS), 591 /* i2s */ 592 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, 593 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, 594 RK3399_CLKGATE_CON(8), 3, GFLAGS), 595 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT, 596 RK3399_CLKSEL_CON(96), 0, 597 RK3399_CLKGATE_CON(8), 4, GFLAGS, 598 &rk3399_i2s0_fracmux), 599 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT, 600 RK3399_CLKGATE_CON(8), 5, GFLAGS), 601 602 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, 603 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, 604 RK3399_CLKGATE_CON(8), 6, GFLAGS), 605 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT, 606 RK3399_CLKSEL_CON(97), 0, 607 RK3399_CLKGATE_CON(8), 7, GFLAGS, 608 &rk3399_i2s1_fracmux), 609 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, 610 RK3399_CLKGATE_CON(8), 8, GFLAGS), 611 612 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, 613 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, 614 RK3399_CLKGATE_CON(8), 9, GFLAGS), 615 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT, 616 RK3399_CLKSEL_CON(98), 0, 617 RK3399_CLKGATE_CON(8), 10, GFLAGS, 618 &rk3399_i2s2_fracmux), 619 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, 620 RK3399_CLKGATE_CON(8), 11, GFLAGS), 621 622 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, 623 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), 624 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, 625 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS, 626 RK3399_CLKGATE_CON(8), 12, GFLAGS), 627 628 /* uart */ 629 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0, 630 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS), 631 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, 632 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, 633 RK3399_CLKGATE_CON(9), 0, GFLAGS), 634 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT, 635 RK3399_CLKSEL_CON(100), 0, 636 RK3399_CLKGATE_CON(9), 1, GFLAGS, 637 &rk3399_uart0_fracmux), 638 639 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0, 640 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS), 641 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, 642 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, 643 RK3399_CLKGATE_CON(9), 2, GFLAGS), 644 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT, 645 RK3399_CLKSEL_CON(101), 0, 646 RK3399_CLKGATE_CON(9), 3, GFLAGS, 647 &rk3399_uart1_fracmux), 648 649 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, 650 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, 651 RK3399_CLKGATE_CON(9), 4, GFLAGS), 652 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT, 653 RK3399_CLKSEL_CON(102), 0, 654 RK3399_CLKGATE_CON(9), 5, GFLAGS, 655 &rk3399_uart2_fracmux), 656 657 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, 658 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, 659 RK3399_CLKGATE_CON(9), 6, GFLAGS), 660 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT, 661 RK3399_CLKSEL_CON(103), 0, 662 RK3399_CLKGATE_CON(9), 7, GFLAGS, 663 &rk3399_uart3_fracmux), 664 665 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 666 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, 667 RK3399_CLKGATE_CON(3), 4, GFLAGS), 668 669 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED, 670 RK3399_CLKGATE_CON(18), 10, GFLAGS), 671 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, 672 RK3399_CLKGATE_CON(18), 12, GFLAGS), 673 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED, 674 RK3399_CLKGATE_CON(18), 15, GFLAGS), 675 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED, 676 RK3399_CLKGATE_CON(19), 2, GFLAGS), 677 678 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED, 679 RK3399_CLKGATE_CON(4), 11, GFLAGS), 680 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED, 681 RK3399_CLKGATE_CON(3), 5, GFLAGS), 682 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED, 683 RK3399_CLKGATE_CON(3), 6, GFLAGS), 684 685 /* cci */ 686 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED, 687 RK3399_CLKGATE_CON(2), 0, GFLAGS), 688 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED, 689 RK3399_CLKGATE_CON(2), 1, GFLAGS), 690 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED, 691 RK3399_CLKGATE_CON(2), 2, GFLAGS), 692 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED, 693 RK3399_CLKGATE_CON(2), 3, GFLAGS), 694 695 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED, 696 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, 697 RK3399_CLKGATE_CON(2), 4, GFLAGS), 698 699 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, 700 RK3399_CLKGATE_CON(15), 0, GFLAGS), 701 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, 702 RK3399_CLKGATE_CON(15), 1, GFLAGS), 703 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, 704 RK3399_CLKGATE_CON(15), 2, GFLAGS), 705 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED, 706 RK3399_CLKGATE_CON(15), 3, GFLAGS), 707 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED, 708 RK3399_CLKGATE_CON(15), 4, GFLAGS), 709 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED, 710 RK3399_CLKGATE_CON(15), 7, GFLAGS), 711 712 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED, 713 RK3399_CLKGATE_CON(2), 5, GFLAGS), 714 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED, 715 RK3399_CLKGATE_CON(2), 6, GFLAGS), 716 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED, 717 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS, 718 RK3399_CLKGATE_CON(2), 7, GFLAGS), 719 720 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED, 721 RK3399_CLKGATE_CON(2), 8, GFLAGS), 722 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED, 723 RK3399_CLKGATE_CON(2), 9, GFLAGS), 724 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED, 725 RK3399_CLKGATE_CON(2), 10, GFLAGS), 726 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED, 727 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS), 728 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED, 729 RK3399_CLKGATE_CON(15), 5, GFLAGS), 730 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED, 731 RK3399_CLKGATE_CON(15), 6, GFLAGS), 732 733 /* vcodec */ 734 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 735 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS, 736 RK3399_CLKGATE_CON(4), 0, GFLAGS), 737 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 738 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS, 739 RK3399_CLKGATE_CON(4), 1, GFLAGS), 740 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, 741 RK3399_CLKGATE_CON(17), 2, GFLAGS), 742 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED, 743 RK3399_CLKGATE_CON(17), 3, GFLAGS), 744 745 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, 746 RK3399_CLKGATE_CON(17), 0, GFLAGS), 747 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED, 748 RK3399_CLKGATE_CON(17), 1, GFLAGS), 749 750 /* vdu */ 751 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0, 752 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, 753 RK3399_CLKGATE_CON(4), 4, GFLAGS), 754 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0, 755 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS, 756 RK3399_CLKGATE_CON(4), 5, GFLAGS), 757 758 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 759 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS, 760 RK3399_CLKGATE_CON(4), 2, GFLAGS), 761 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0, 762 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS, 763 RK3399_CLKGATE_CON(4), 3, GFLAGS), 764 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0, 765 RK3399_CLKGATE_CON(17), 10, GFLAGS), 766 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED, 767 RK3399_CLKGATE_CON(17), 11, GFLAGS), 768 769 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0, 770 RK3399_CLKGATE_CON(17), 8, GFLAGS), 771 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED, 772 RK3399_CLKGATE_CON(17), 9, GFLAGS), 773 774 /* iep */ 775 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 776 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, 777 RK3399_CLKGATE_CON(4), 6, GFLAGS), 778 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0, 779 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS, 780 RK3399_CLKGATE_CON(4), 7, GFLAGS), 781 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0, 782 RK3399_CLKGATE_CON(16), 2, GFLAGS), 783 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED, 784 RK3399_CLKGATE_CON(16), 3, GFLAGS), 785 786 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, 787 RK3399_CLKGATE_CON(16), 0, GFLAGS), 788 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, 789 RK3399_CLKGATE_CON(16), 1, GFLAGS), 790 791 /* rga */ 792 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 793 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, 794 RK3399_CLKGATE_CON(4), 10, GFLAGS), 795 796 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 797 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, 798 RK3399_CLKGATE_CON(4), 8, GFLAGS), 799 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0, 800 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS, 801 RK3399_CLKGATE_CON(4), 9, GFLAGS), 802 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, 803 RK3399_CLKGATE_CON(16), 10, GFLAGS), 804 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED, 805 RK3399_CLKGATE_CON(16), 11, GFLAGS), 806 807 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, 808 RK3399_CLKGATE_CON(16), 8, GFLAGS), 809 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, 810 RK3399_CLKGATE_CON(16), 9, GFLAGS), 811 812 /* center */ 813 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 814 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, 815 RK3399_CLKGATE_CON(3), 7, GFLAGS), 816 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED, 817 RK3399_CLKGATE_CON(19), 0, GFLAGS), 818 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED, 819 RK3399_CLKGATE_CON(19), 1, GFLAGS), 820 821 /* gpu */ 822 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 823 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, 824 RK3399_CLKGATE_CON(13), 0, GFLAGS), 825 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, 826 RK3399_CLKGATE_CON(30), 8, GFLAGS), 827 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0, 828 RK3399_CLKGATE_CON(30), 10, GFLAGS), 829 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0, 830 RK3399_CLKGATE_CON(30), 11, GFLAGS), 831 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0, 832 RK3399_CLKGATE_CON(13), 1, GFLAGS), 833 834 /* perihp */ 835 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED, 836 RK3399_CLKGATE_CON(5), 0, GFLAGS), 837 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED, 838 RK3399_CLKGATE_CON(5), 1, GFLAGS), 839 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED, 840 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS, 841 RK3399_CLKGATE_CON(5), 2, GFLAGS), 842 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, 843 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS, 844 RK3399_CLKGATE_CON(5), 3, GFLAGS), 845 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, 846 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS, 847 RK3399_CLKGATE_CON(5), 4, GFLAGS), 848 849 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED, 850 RK3399_CLKGATE_CON(20), 2, GFLAGS), 851 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED, 852 RK3399_CLKGATE_CON(20), 10, GFLAGS), 853 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED, 854 RK3399_CLKGATE_CON(20), 12, GFLAGS), 855 856 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0, 857 RK3399_CLKGATE_CON(20), 5, GFLAGS), 858 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0, 859 RK3399_CLKGATE_CON(20), 6, GFLAGS), 860 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0, 861 RK3399_CLKGATE_CON(20), 7, GFLAGS), 862 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0, 863 RK3399_CLKGATE_CON(20), 8, GFLAGS), 864 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0, 865 RK3399_CLKGATE_CON(20), 9, GFLAGS), 866 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED, 867 RK3399_CLKGATE_CON(20), 13, GFLAGS), 868 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED, 869 RK3399_CLKGATE_CON(20), 15, GFLAGS), 870 871 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED, 872 RK3399_CLKGATE_CON(20), 4, GFLAGS), 873 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0, 874 RK3399_CLKGATE_CON(20), 11, GFLAGS), 875 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED, 876 RK3399_CLKGATE_CON(20), 14, GFLAGS), 877 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0, 878 RK3399_CLKGATE_CON(31), 8, GFLAGS), 879 880 /* sdio & sdmmc */ 881 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, 882 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, 883 RK3399_CLKGATE_CON(12), 13, GFLAGS), 884 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0, 885 RK3399_CLKGATE_CON(33), 8, GFLAGS), 886 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED, 887 RK3399_CLKGATE_CON(33), 9, GFLAGS), 888 889 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, 890 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS, 891 RK3399_CLKGATE_CON(6), 0, GFLAGS), 892 893 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, 894 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS, 895 RK3399_CLKGATE_CON(6), 1, GFLAGS), 896 897 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), 898 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), 899 900 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), 901 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), 902 903 /* pcie */ 904 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0, 905 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS, 906 RK3399_CLKGATE_CON(6), 2, GFLAGS), 907 908 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0, 909 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS, 910 RK3399_CLKGATE_CON(12), 6, GFLAGS), 911 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT, 912 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS), 913 914 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0, 915 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS, 916 RK3399_CLKGATE_CON(6), 3, GFLAGS), 917 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT, 918 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS), 919 920 /* emmc */ 921 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0, 922 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS, 923 RK3399_CLKGATE_CON(6), 14, GFLAGS), 924 925 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED, 926 RK3399_CLKGATE_CON(6), 12, GFLAGS), 927 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED, 928 RK3399_CLKGATE_CON(6), 13, GFLAGS), 929 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED, 930 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS), 931 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED, 932 RK3399_CLKGATE_CON(32), 8, GFLAGS), 933 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED, 934 RK3399_CLKGATE_CON(32), 9, GFLAGS), 935 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED, 936 RK3399_CLKGATE_CON(32), 10, GFLAGS), 937 938 /* perilp0 */ 939 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED, 940 RK3399_CLKGATE_CON(7), 1, GFLAGS), 941 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED, 942 RK3399_CLKGATE_CON(7), 0, GFLAGS), 943 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED, 944 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS, 945 RK3399_CLKGATE_CON(7), 2, GFLAGS), 946 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED, 947 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS, 948 RK3399_CLKGATE_CON(7), 3, GFLAGS), 949 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0, 950 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS, 951 RK3399_CLKGATE_CON(7), 4, GFLAGS), 952 953 /* aclk_perilp0 gates */ 954 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS), 955 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS), 956 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS), 957 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS), 958 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS), 959 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS), 960 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS), 961 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS), 962 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS), 963 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS), 964 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS), 965 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS), 966 967 /* hclk_perilp0 gates */ 968 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS), 969 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS), 970 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS), 971 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS), 972 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS), 973 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS), 974 975 /* pclk_perilp0 gates */ 976 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS), 977 978 /* crypto */ 979 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0, 980 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS, 981 RK3399_CLKGATE_CON(7), 7, GFLAGS), 982 983 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0, 984 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS, 985 RK3399_CLKGATE_CON(7), 8, GFLAGS), 986 987 /* cm0s_perilp */ 988 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0, 989 RK3399_CLKGATE_CON(7), 6, GFLAGS), 990 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0, 991 RK3399_CLKGATE_CON(7), 5, GFLAGS), 992 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0, 993 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS, 994 RK3399_CLKGATE_CON(7), 9, GFLAGS), 995 996 /* fclk_cm0s gates */ 997 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS), 998 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS), 999 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS), 1000 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS), 1001 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS), 1002 1003 /* perilp1 */ 1004 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED, 1005 RK3399_CLKGATE_CON(8), 1, GFLAGS), 1006 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED, 1007 RK3399_CLKGATE_CON(8), 0, GFLAGS), 1008 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED, 1009 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS), 1010 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED, 1011 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS, 1012 RK3399_CLKGATE_CON(8), 2, GFLAGS), 1013 1014 /* hclk_perilp1 gates */ 1015 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS), 1016 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS), 1017 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS), 1018 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS), 1019 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS), 1020 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS), 1021 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS), 1022 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS), 1023 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS), 1024 1025 /* pclk_perilp1 gates */ 1026 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS), 1027 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS), 1028 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS), 1029 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS), 1030 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS), 1031 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS), 1032 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS), 1033 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS), 1034 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS), 1035 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS), 1036 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS), 1037 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS), 1038 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS), 1039 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS), 1040 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS), 1041 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS), 1042 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS), 1043 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), 1044 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS), 1045 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS), 1046 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), 1047 1048 /* saradc */ 1049 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, 1050 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS, 1051 RK3399_CLKGATE_CON(9), 11, GFLAGS), 1052 1053 /* tsadc */ 1054 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0, 1055 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS, 1056 RK3399_CLKGATE_CON(9), 10, GFLAGS), 1057 1058 /* cif_testout */ 1059 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, 1060 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS), 1061 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0, 1062 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, 1063 RK3399_CLKGATE_CON(13), 14, GFLAGS), 1064 1065 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, 1066 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS), 1067 COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0, 1068 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS, 1069 RK3399_CLKGATE_CON(13), 15, GFLAGS), 1070 1071 /* vio */ 1072 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 1073 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, 1074 RK3399_CLKGATE_CON(11), 10, GFLAGS), 1075 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0, 1076 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS, 1077 RK3399_CLKGATE_CON(11), 1, GFLAGS), 1078 1079 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED, 1080 RK3399_CLKGATE_CON(29), 0, GFLAGS), 1081 1082 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0, 1083 RK3399_CLKGATE_CON(29), 1, GFLAGS), 1084 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0, 1085 RK3399_CLKGATE_CON(29), 2, GFLAGS), 1086 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED, 1087 RK3399_CLKGATE_CON(29), 12, GFLAGS), 1088 1089 /* hdcp */ 1090 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0, 1091 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, 1092 RK3399_CLKGATE_CON(11), 12, GFLAGS), 1093 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0, 1094 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS, 1095 RK3399_CLKGATE_CON(11), 3, GFLAGS), 1096 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0, 1097 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS, 1098 RK3399_CLKGATE_CON(11), 10, GFLAGS), 1099 1100 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED, 1101 RK3399_CLKGATE_CON(29), 4, GFLAGS), 1102 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0, 1103 RK3399_CLKGATE_CON(29), 10, GFLAGS), 1104 1105 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED, 1106 RK3399_CLKGATE_CON(29), 5, GFLAGS), 1107 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0, 1108 RK3399_CLKGATE_CON(29), 9, GFLAGS), 1109 1110 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED, 1111 RK3399_CLKGATE_CON(29), 3, GFLAGS), 1112 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0, 1113 RK3399_CLKGATE_CON(29), 6, GFLAGS), 1114 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0, 1115 RK3399_CLKGATE_CON(29), 7, GFLAGS), 1116 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0, 1117 RK3399_CLKGATE_CON(29), 8, GFLAGS), 1118 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0, 1119 RK3399_CLKGATE_CON(29), 11, GFLAGS), 1120 1121 /* edp */ 1122 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0, 1123 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS, 1124 RK3399_CLKGATE_CON(11), 8, GFLAGS), 1125 1126 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0, 1127 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS, 1128 RK3399_CLKGATE_CON(11), 11, GFLAGS), 1129 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED, 1130 RK3399_CLKGATE_CON(32), 12, GFLAGS), 1131 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0, 1132 RK3399_CLKGATE_CON(32), 13, GFLAGS), 1133 1134 /* hdmi */ 1135 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, 1136 RK3399_CLKGATE_CON(11), 6, GFLAGS), 1137 1138 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0, 1139 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS, 1140 RK3399_CLKGATE_CON(11), 7, GFLAGS), 1141 1142 /* vop0 */ 1143 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, 1144 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS, 1145 RK3399_CLKGATE_CON(10), 8, GFLAGS), 1146 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0, 1147 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS, 1148 RK3399_CLKGATE_CON(10), 9, GFLAGS), 1149 1150 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0, 1151 RK3399_CLKGATE_CON(28), 3, GFLAGS), 1152 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED, 1153 RK3399_CLKGATE_CON(28), 1, GFLAGS), 1154 1155 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0, 1156 RK3399_CLKGATE_CON(28), 2, GFLAGS), 1157 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, 1158 RK3399_CLKGATE_CON(28), 0, GFLAGS), 1159 1160 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, 1161 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, 1162 RK3399_CLKGATE_CON(10), 12, GFLAGS), 1163 1164 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT, 1165 RK3399_CLKSEL_CON(106), 0, 1166 &rk3399_dclk_vop0_fracmux), 1167 1168 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0, 1169 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, 1170 RK3399_CLKGATE_CON(10), 14, GFLAGS), 1171 1172 /* vop1 */ 1173 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, 1174 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, 1175 RK3399_CLKGATE_CON(10), 10, GFLAGS), 1176 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0, 1177 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS, 1178 RK3399_CLKGATE_CON(10), 11, GFLAGS), 1179 1180 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0, 1181 RK3399_CLKGATE_CON(28), 7, GFLAGS), 1182 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED, 1183 RK3399_CLKGATE_CON(28), 5, GFLAGS), 1184 1185 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0, 1186 RK3399_CLKGATE_CON(28), 6, GFLAGS), 1187 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED, 1188 RK3399_CLKGATE_CON(28), 4, GFLAGS), 1189 1190 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0, 1191 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, 1192 RK3399_CLKGATE_CON(10), 13, GFLAGS), 1193 1194 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT, 1195 RK3399_CLKSEL_CON(107), 0, 1196 &rk3399_dclk_vop1_fracmux), 1197 1198 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED, 1199 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS, 1200 RK3399_CLKGATE_CON(10), 15, GFLAGS), 1201 1202 /* isp */ 1203 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0, 1204 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS, 1205 RK3399_CLKGATE_CON(12), 8, GFLAGS), 1206 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0, 1207 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS, 1208 RK3399_CLKGATE_CON(12), 9, GFLAGS), 1209 1210 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED, 1211 RK3399_CLKGATE_CON(27), 1, GFLAGS), 1212 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0, 1213 RK3399_CLKGATE_CON(27), 5, GFLAGS), 1214 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0, 1215 RK3399_CLKGATE_CON(27), 7, GFLAGS), 1216 1217 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED, 1218 RK3399_CLKGATE_CON(27), 0, GFLAGS), 1219 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0, 1220 RK3399_CLKGATE_CON(27), 4, GFLAGS), 1221 1222 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0, 1223 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS, 1224 RK3399_CLKGATE_CON(11), 4, GFLAGS), 1225 1226 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0, 1227 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS, 1228 RK3399_CLKGATE_CON(12), 10, GFLAGS), 1229 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0, 1230 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS, 1231 RK3399_CLKGATE_CON(12), 11, GFLAGS), 1232 1233 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED, 1234 RK3399_CLKGATE_CON(27), 3, GFLAGS), 1235 1236 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED, 1237 RK3399_CLKGATE_CON(27), 2, GFLAGS), 1238 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0, 1239 RK3399_CLKGATE_CON(27), 8, GFLAGS), 1240 1241 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0, 1242 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS, 1243 RK3399_CLKGATE_CON(11), 5, GFLAGS), 1244 1245 /* 1246 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system, 1247 * so we ignore the mux and make clocks nodes as following, 1248 * 1249 * pclkin_cifinv --|-------\ 1250 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper 1251 * pclkin_cif --|-------/ 1252 */ 1253 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0, 1254 RK3399_CLKGATE_CON(27), 6, GFLAGS), 1255 1256 /* cif */ 1257 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0, 1258 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 1259 RK3399_CLKGATE_CON(10), 7, GFLAGS), 1260 1261 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, 1262 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), 1263 1264 /* gic */ 1265 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 1266 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS, 1267 RK3399_CLKGATE_CON(12), 12, GFLAGS), 1268 1269 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS), 1270 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS), 1271 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS), 1272 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS), 1273 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS), 1274 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS), 1275 1276 /* alive */ 1277 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */ 1278 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, 1279 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS), 1280 1281 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS), 1282 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS), 1283 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS), 1284 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS), 1285 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS), 1286 1287 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS), 1288 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS), 1289 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS), 1290 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS), 1291 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS), 1292 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS), 1293 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS), 1294 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS), 1295 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS), 1296 1297 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS), 1298 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS), 1299 1300 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS), 1301 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS), 1302 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS), 1303 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS), 1304 1305 /* testout */ 1306 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, 1307 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), 1308 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT, 1309 RK3399_CLKSEL_CON(105), 0, 1310 RK3399_CLKGATE_CON(13), 9, GFLAGS), 1311 1312 DIV(0, "clk_test_24m", "xin24m", 0, 1313 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS), 1314 1315 /* spi */ 1316 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0, 1317 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS, 1318 RK3399_CLKGATE_CON(9), 12, GFLAGS), 1319 1320 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0, 1321 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS, 1322 RK3399_CLKGATE_CON(9), 13, GFLAGS), 1323 1324 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0, 1325 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS, 1326 RK3399_CLKGATE_CON(9), 14, GFLAGS), 1327 1328 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0, 1329 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS, 1330 RK3399_CLKGATE_CON(9), 15, GFLAGS), 1331 1332 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0, 1333 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS, 1334 RK3399_CLKGATE_CON(13), 13, GFLAGS), 1335 1336 /* i2c */ 1337 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0, 1338 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS, 1339 RK3399_CLKGATE_CON(10), 0, GFLAGS), 1340 1341 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0, 1342 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS, 1343 RK3399_CLKGATE_CON(10), 2, GFLAGS), 1344 1345 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0, 1346 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS, 1347 RK3399_CLKGATE_CON(10), 4, GFLAGS), 1348 1349 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0, 1350 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS, 1351 RK3399_CLKGATE_CON(10), 1, GFLAGS), 1352 1353 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0, 1354 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS, 1355 RK3399_CLKGATE_CON(10), 3, GFLAGS), 1356 1357 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0, 1358 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS, 1359 RK3399_CLKGATE_CON(10), 5, GFLAGS), 1360 1361 /* timer */ 1362 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS), 1363 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS), 1364 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS), 1365 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS), 1366 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS), 1367 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS), 1368 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS), 1369 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS), 1370 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS), 1371 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS), 1372 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS), 1373 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS), 1374 1375 /* clk_test */ 1376 /* clk_test_pre is controlled by CRU_MISC_CON[3] */ 1377 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, 1378 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, 1379 RK3368_CLKGATE_CON(13), 11, GFLAGS), 1380 }; 1381 1382 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { 1383 /* 1384 * PMU CRU Clock-Architecture 1385 */ 1386 1387 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0, 1388 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS), 1389 1390 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0, 1391 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS), 1392 1393 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0, 1394 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS, 1395 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS), 1396 1397 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED, 1398 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, 1399 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), 1400 1401 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT, 1402 RK3399_PMU_CLKSEL_CON(7), 0, 1403 &rk3399_pmuclk_wifi_fracmux), 1404 1405 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED, 1406 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS), 1407 1408 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0, 1409 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS, 1410 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS), 1411 1412 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0, 1413 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, 1414 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS), 1415 1416 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0, 1417 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS, 1418 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS), 1419 1420 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED, 1421 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS), 1422 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, 1423 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), 1424 1425 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0, 1426 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, 1427 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), 1428 1429 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT, 1430 RK3399_PMU_CLKSEL_CON(6), 0, 1431 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, 1432 &rk3399_uart4_pmu_fracmux), 1433 1434 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED, 1435 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS), 1436 1437 /* pmu clock gates */ 1438 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS), 1439 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS), 1440 1441 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS), 1442 1443 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS), 1444 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS), 1445 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS), 1446 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS), 1447 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS), 1448 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS), 1449 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS), 1450 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS), 1451 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS), 1452 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS), 1453 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS), 1454 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS), 1455 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS), 1456 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS), 1457 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), 1458 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), 1459 1460 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), 1461 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), 1462 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), 1463 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), 1464 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), 1465 }; 1466 1467 static const char *const rk3399_cru_critical_clocks[] __initconst = { 1468 "aclk_cci_pre", 1469 "aclk_gic", 1470 "aclk_gic_noc", 1471 "pclk_perilp0", 1472 "pclk_perilp0", 1473 "hclk_perilp0", 1474 "hclk_perilp0_noc", 1475 "pclk_perilp1", 1476 "pclk_perilp1_noc", 1477 "pclk_perihp", 1478 "pclk_perihp_noc", 1479 "hclk_perihp", 1480 "aclk_perihp", 1481 "aclk_perihp_noc", 1482 "aclk_perilp0", 1483 "aclk_perilp0_noc", 1484 "hclk_perilp1", 1485 "hclk_perilp1_noc", 1486 "aclk_dmac0_perilp", 1487 "gpll_hclk_perilp1_src", 1488 "gpll_aclk_perilp0_src", 1489 "gpll_aclk_perihp_src", 1490 }; 1491 1492 static const char *const rk3399_pmucru_critical_clocks[] __initconst = { 1493 "ppll", 1494 "pclk_pmu_src", 1495 "fclk_cm0s_src_pmu", 1496 "clk_timer_src_pmu", 1497 }; 1498 1499 static void __init rk3399_clk_init(struct device_node *np) 1500 { 1501 struct rockchip_clk_provider *ctx; 1502 void __iomem *reg_base; 1503 1504 reg_base = of_iomap(np, 0); 1505 if (!reg_base) { 1506 pr_err("%s: could not map cru region\n", __func__); 1507 return; 1508 } 1509 1510 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 1511 if (IS_ERR(ctx)) { 1512 pr_err("%s: rockchip clk init failed\n", __func__); 1513 iounmap(reg_base); 1514 return; 1515 } 1516 1517 rockchip_clk_register_plls(ctx, rk3399_pll_clks, 1518 ARRAY_SIZE(rk3399_pll_clks), -1); 1519 1520 rockchip_clk_register_branches(ctx, rk3399_clk_branches, 1521 ARRAY_SIZE(rk3399_clk_branches)); 1522 1523 rockchip_clk_protect_critical(rk3399_cru_critical_clocks, 1524 ARRAY_SIZE(rk3399_cru_critical_clocks)); 1525 1526 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", 1527 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), 1528 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates, 1529 ARRAY_SIZE(rk3399_cpuclkl_rates)); 1530 1531 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", 1532 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), 1533 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates, 1534 ARRAY_SIZE(rk3399_cpuclkb_rates)); 1535 1536 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), 1537 ROCKCHIP_SOFTRST_HIWORD_MASK); 1538 1539 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL); 1540 1541 rockchip_clk_of_add_provider(np, ctx); 1542 } 1543 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init); 1544 1545 static void __init rk3399_pmu_clk_init(struct device_node *np) 1546 { 1547 struct rockchip_clk_provider *ctx; 1548 void __iomem *reg_base; 1549 1550 reg_base = of_iomap(np, 0); 1551 if (!reg_base) { 1552 pr_err("%s: could not map cru pmu region\n", __func__); 1553 return; 1554 } 1555 1556 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 1557 if (IS_ERR(ctx)) { 1558 pr_err("%s: rockchip pmu clk init failed\n", __func__); 1559 iounmap(reg_base); 1560 return; 1561 } 1562 1563 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks, 1564 ARRAY_SIZE(rk3399_pmu_pll_clks), -1); 1565 1566 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches, 1567 ARRAY_SIZE(rk3399_clk_pmu_branches)); 1568 1569 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks, 1570 ARRAY_SIZE(rk3399_pmucru_critical_clocks)); 1571 1572 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), 1573 ROCKCHIP_SOFTRST_HIWORD_MASK); 1574 1575 rockchip_clk_of_add_provider(np, ctx); 1576 } 1577 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init); 1578