111551005SXing Zheng /* 211551005SXing Zheng * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 311551005SXing Zheng * Author: Xing Zheng <zhengxing@rock-chips.com> 411551005SXing Zheng * 511551005SXing Zheng * This program is free software; you can redistribute it and/or modify 611551005SXing Zheng * it under the terms of the GNU General Public License as published by 711551005SXing Zheng * the Free Software Foundation; either version 2 of the License, or 811551005SXing Zheng * (at your option) any later version. 911551005SXing Zheng * 1011551005SXing Zheng * This program is distributed in the hope that it will be useful, 1111551005SXing Zheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 1211551005SXing Zheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1311551005SXing Zheng * GNU General Public License for more details. 1411551005SXing Zheng */ 1511551005SXing Zheng 1611551005SXing Zheng #include <linux/clk-provider.h> 1762e59c4eSStephen Boyd #include <linux/io.h> 1811551005SXing Zheng #include <linux/of.h> 1911551005SXing Zheng #include <linux/of_address.h> 2011551005SXing Zheng #include <linux/platform_device.h> 2111551005SXing Zheng #include <linux/regmap.h> 2211551005SXing Zheng #include <dt-bindings/clock/rk3399-cru.h> 2311551005SXing Zheng #include "clk.h" 2411551005SXing Zheng 2511551005SXing Zheng enum rk3399_plls { 2611551005SXing Zheng lpll, bpll, dpll, cpll, gpll, npll, vpll, 2711551005SXing Zheng }; 2811551005SXing Zheng 2911551005SXing Zheng enum rk3399_pmu_plls { 3011551005SXing Zheng ppll, 3111551005SXing Zheng }; 3211551005SXing Zheng 3311551005SXing Zheng static struct rockchip_pll_rate_table rk3399_pll_rates[] = { 3411551005SXing Zheng /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 3511551005SXing Zheng RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 3611551005SXing Zheng RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 3711551005SXing Zheng RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 3811551005SXing Zheng RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 3911551005SXing Zheng RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 4011551005SXing Zheng RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 4111551005SXing Zheng RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 4211551005SXing Zheng RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 4311551005SXing Zheng RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 4411551005SXing Zheng RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 4511551005SXing Zheng RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 4611551005SXing Zheng RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 4711551005SXing Zheng RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 4811551005SXing Zheng RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 4911551005SXing Zheng RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 5011551005SXing Zheng RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 5111551005SXing Zheng RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 5211551005SXing Zheng RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 5311551005SXing Zheng RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 5411551005SXing Zheng RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 5511551005SXing Zheng RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 5611551005SXing Zheng RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 5711551005SXing Zheng RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 5811551005SXing Zheng RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 5911551005SXing Zheng RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 6011551005SXing Zheng RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 614ee3fd4aSDerek Basehore RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 6211551005SXing Zheng RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 6311551005SXing Zheng RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 6411551005SXing Zheng RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 6511551005SXing Zheng RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 6611551005SXing Zheng RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 6711551005SXing Zheng RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 6811551005SXing Zheng RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 6911551005SXing Zheng RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 7011551005SXing Zheng RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 7111551005SXing Zheng RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 7211551005SXing Zheng RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 7311551005SXing Zheng RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 7411551005SXing Zheng RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 7511551005SXing Zheng RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 7611551005SXing Zheng RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 7711551005SXing Zheng RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 7811551005SXing Zheng RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 7911551005SXing Zheng RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 8011551005SXing Zheng RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 8111551005SXing Zheng RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 821dfbec39SXing Zheng RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), 8311551005SXing Zheng RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 8411551005SXing Zheng RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 8511551005SXing Zheng RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 8611551005SXing Zheng RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 8711551005SXing Zheng RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 8811551005SXing Zheng RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 8911551005SXing Zheng RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 9011551005SXing Zheng RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 9111551005SXing Zheng RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 921dfbec39SXing Zheng RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), 9311551005SXing Zheng RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 9411551005SXing Zheng RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 9511551005SXing Zheng RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 9611551005SXing Zheng RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 97aa2897ceSXing Zheng RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 985c1c63f6SXing Zheng RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), 9911551005SXing Zheng RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 10011551005SXing Zheng RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 10111551005SXing Zheng RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 10211551005SXing Zheng RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 103aa2897ceSXing Zheng RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), 10411551005SXing Zheng RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 105aa2897ceSXing Zheng RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), 106efc4204cSXing Zheng RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), 10711551005SXing Zheng RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 108aa2897ceSXing Zheng RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), 109efc4204cSXing Zheng RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), 110aa2897ceSXing Zheng RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), 111aa2897ceSXing Zheng RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), 11211551005SXing Zheng { /* sentinel */ }, 11311551005SXing Zheng }; 11411551005SXing Zheng 11511551005SXing Zheng /* CRU parents */ 11611551005SXing Zheng PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 11711551005SXing Zheng 11811551005SXing Zheng PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src", 11911551005SXing Zheng "clk_core_l_bpll_src", 12011551005SXing Zheng "clk_core_l_dpll_src", 12111551005SXing Zheng "clk_core_l_gpll_src" }; 12211551005SXing Zheng PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", 12311551005SXing Zheng "clk_core_b_bpll_src", 12411551005SXing Zheng "clk_core_b_dpll_src", 12511551005SXing Zheng "clk_core_b_gpll_src" }; 126464b9eebSLin Huang PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", 127464b9eebSLin Huang "clk_ddrc_bpll_src", 128464b9eebSLin Huang "clk_ddrc_dpll_src", 129464b9eebSLin Huang "clk_ddrc_gpll_src" }; 13011551005SXing Zheng PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", 13111551005SXing Zheng "gpll_aclk_cci_src", 13211551005SXing Zheng "npll_aclk_cci_src", 13311551005SXing Zheng "vpll_aclk_cci_src" }; 134995d3fdeSHeiko Stuebner PNAME(mux_cci_trace_p) = { "cpll_cci_trace", 135995d3fdeSHeiko Stuebner "gpll_cci_trace" }; 136995d3fdeSHeiko Stuebner PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", 137995d3fdeSHeiko Stuebner "npll_cs"}; 138995d3fdeSHeiko Stuebner PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", 139995d3fdeSHeiko Stuebner "gpll_aclk_perihp_src" }; 14011551005SXing Zheng 14111551005SXing Zheng PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 14211551005SXing Zheng PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; 14311551005SXing Zheng PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" }; 14411551005SXing Zheng PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" }; 14511551005SXing Zheng PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; 146995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", 147995d3fdeSHeiko Stuebner "ppll" }; 148995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", 149995d3fdeSHeiko Stuebner "xin24m" }; 150995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", 151995d3fdeSHeiko Stuebner "clk_usbphy_480m" }; 152995d3fdeSHeiko Stuebner PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", 153995d3fdeSHeiko Stuebner "npll", "upll" }; 154995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", 155995d3fdeSHeiko Stuebner "upll", "xin24m" }; 156995d3fdeSHeiko Stuebner PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", 157995d3fdeSHeiko Stuebner "ppll", "upll", "xin24m" }; 15811551005SXing Zheng 15911551005SXing Zheng PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; 160995d3fdeSHeiko Stuebner PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", 161995d3fdeSHeiko Stuebner "npll" }; 162995d3fdeSHeiko Stuebner PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", 163995d3fdeSHeiko Stuebner "xin24m" }; 16411551005SXing Zheng 165995d3fdeSHeiko Stuebner PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", 166995d3fdeSHeiko Stuebner "dclk_vop0_frac" }; 167995d3fdeSHeiko Stuebner PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", 168995d3fdeSHeiko Stuebner "dclk_vop1_frac" }; 16911551005SXing Zheng 170fd8bc829SXing Zheng PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" }; 17111551005SXing Zheng 17211551005SXing Zheng PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; 17311551005SXing Zheng PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; 174995d3fdeSHeiko Stuebner PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", 175995d3fdeSHeiko Stuebner "cpll", "gpll" }; 176995d3fdeSHeiko Stuebner PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", 177995d3fdeSHeiko Stuebner "clk_pcie_core_phy" }; 17811551005SXing Zheng 179995d3fdeSHeiko Stuebner PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", 180995d3fdeSHeiko Stuebner "gpll_aclk_emmc_src" }; 18111551005SXing Zheng 182995d3fdeSHeiko Stuebner PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", 183995d3fdeSHeiko Stuebner "gpll_aclk_perilp0_src" }; 18411551005SXing Zheng 185995d3fdeSHeiko Stuebner PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", 186995d3fdeSHeiko Stuebner "gpll_fclk_cm0s_src" }; 18711551005SXing Zheng 188995d3fdeSHeiko Stuebner PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", 189995d3fdeSHeiko Stuebner "gpll_hclk_perilp1_src" }; 19011551005SXing Zheng 19111551005SXing Zheng PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; 19211551005SXing Zheng PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; 19311551005SXing Zheng 194995d3fdeSHeiko Stuebner PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", 195995d3fdeSHeiko Stuebner "clk_usbphy1_480m_src" }; 196995d3fdeSHeiko Stuebner PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", 197995d3fdeSHeiko Stuebner "gpll_aclk_gmac_src" }; 19811551005SXing Zheng PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; 19911551005SXing Zheng PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", 20011551005SXing Zheng "clkin_i2s", "xin12m" }; 20111551005SXing Zheng PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", 20211551005SXing Zheng "clkin_i2s", "xin12m" }; 20311551005SXing Zheng PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", 20411551005SXing Zheng "clkin_i2s", "xin12m" }; 20511551005SXing Zheng PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", 20611551005SXing Zheng "clkin_i2s", "xin12m" }; 207995d3fdeSHeiko Stuebner PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", 208995d3fdeSHeiko Stuebner "clk_i2s2" }; 20911551005SXing Zheng PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; 21011551005SXing Zheng 21111551005SXing Zheng PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 21211551005SXing Zheng PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 21311551005SXing Zheng PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 21411551005SXing Zheng PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 21511551005SXing Zheng 21611551005SXing Zheng /* PMU CRU parents */ 21711551005SXing Zheng PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; 21811551005SXing Zheng PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; 21911551005SXing Zheng PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; 22011551005SXing Zheng PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; 221995d3fdeSHeiko Stuebner PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", 222995d3fdeSHeiko Stuebner "xin24m" }; 22311551005SXing Zheng PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; 22411551005SXing Zheng 22511551005SXing Zheng static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { 22611551005SXing Zheng [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), 22711551005SXing Zheng RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates), 22811551005SXing Zheng [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8), 22911551005SXing Zheng RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates), 23011551005SXing Zheng [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), 23111551005SXing Zheng RK3399_PLL_CON(19), 8, 31, 0, NULL), 23211551005SXing Zheng [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), 23311551005SXing Zheng RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 23411551005SXing Zheng [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), 23511551005SXing Zheng RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 23611551005SXing Zheng [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40), 23711551005SXing Zheng RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 23811551005SXing Zheng [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48), 23911551005SXing Zheng RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 24011551005SXing Zheng }; 24111551005SXing Zheng 24211551005SXing Zheng static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = { 24311551005SXing Zheng [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0), 24411551005SXing Zheng RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates), 24511551005SXing Zheng }; 24611551005SXing Zheng 24711551005SXing Zheng #define MFLAGS CLK_MUX_HIWORD_MASK 24811551005SXing Zheng #define DFLAGS CLK_DIVIDER_HIWORD_MASK 24911551005SXing Zheng #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 25011551005SXing Zheng #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 25111551005SXing Zheng 25211551005SXing Zheng static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata = 25311551005SXing Zheng MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, 25411551005SXing Zheng RK3399_CLKSEL_CON(32), 13, 2, MFLAGS); 25511551005SXing Zheng 25611551005SXing Zheng static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata = 25711551005SXing Zheng MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT, 25811551005SXing Zheng RK3399_CLKSEL_CON(28), 8, 2, MFLAGS); 25911551005SXing Zheng 26011551005SXing Zheng static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata = 26111551005SXing Zheng MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, 26211551005SXing Zheng RK3399_CLKSEL_CON(29), 8, 2, MFLAGS); 26311551005SXing Zheng 26411551005SXing Zheng static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata = 26511551005SXing Zheng MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, 26611551005SXing Zheng RK3399_CLKSEL_CON(30), 8, 2, MFLAGS); 26711551005SXing Zheng 26811551005SXing Zheng static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata = 26911551005SXing Zheng MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 27011551005SXing Zheng RK3399_CLKSEL_CON(33), 8, 2, MFLAGS); 27111551005SXing Zheng 27211551005SXing Zheng static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata = 27311551005SXing Zheng MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 27411551005SXing Zheng RK3399_CLKSEL_CON(34), 8, 2, MFLAGS); 27511551005SXing Zheng 27611551005SXing Zheng static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata = 27711551005SXing Zheng MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 27811551005SXing Zheng RK3399_CLKSEL_CON(35), 8, 2, MFLAGS); 27911551005SXing Zheng 28011551005SXing Zheng static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata = 28111551005SXing Zheng MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, 28211551005SXing Zheng RK3399_CLKSEL_CON(36), 8, 2, MFLAGS); 28311551005SXing Zheng 28411551005SXing Zheng static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata = 28511551005SXing Zheng MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT, 28611551005SXing Zheng RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS); 28711551005SXing Zheng 28811551005SXing Zheng static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata = 28911551005SXing Zheng MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT, 29011551005SXing Zheng RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); 29111551005SXing Zheng 29211551005SXing Zheng static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = 29311551005SXing Zheng MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT, 29411551005SXing Zheng RK3399_CLKSEL_CON(50), 11, 1, MFLAGS); 29511551005SXing Zheng 29611551005SXing Zheng static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata = 29711551005SXing Zheng MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, 29811551005SXing Zheng RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS); 29911551005SXing Zheng 30011551005SXing Zheng static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = { 30111551005SXing Zheng .core_reg = RK3399_CLKSEL_CON(0), 30211551005SXing Zheng .div_core_shift = 0, 30311551005SXing Zheng .div_core_mask = 0x1f, 30411551005SXing Zheng .mux_core_alt = 3, 30511551005SXing Zheng .mux_core_main = 0, 30611551005SXing Zheng .mux_core_shift = 6, 30711551005SXing Zheng .mux_core_mask = 0x3, 30811551005SXing Zheng }; 30911551005SXing Zheng 31011551005SXing Zheng static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = { 31111551005SXing Zheng .core_reg = RK3399_CLKSEL_CON(2), 31211551005SXing Zheng .div_core_shift = 0, 31311551005SXing Zheng .div_core_mask = 0x1f, 31411551005SXing Zheng .mux_core_alt = 3, 31511551005SXing Zheng .mux_core_main = 1, 31611551005SXing Zheng .mux_core_shift = 6, 31711551005SXing Zheng .mux_core_mask = 0x3, 31811551005SXing Zheng }; 31911551005SXing Zheng 32011551005SXing Zheng #define RK3399_DIV_ACLKM_MASK 0x1f 32111551005SXing Zheng #define RK3399_DIV_ACLKM_SHIFT 8 32211551005SXing Zheng #define RK3399_DIV_ATCLK_MASK 0x1f 32311551005SXing Zheng #define RK3399_DIV_ATCLK_SHIFT 0 32411551005SXing Zheng #define RK3399_DIV_PCLK_DBG_MASK 0x1f 32511551005SXing Zheng #define RK3399_DIV_PCLK_DBG_SHIFT 8 32611551005SXing Zheng 32711551005SXing Zheng #define RK3399_CLKSEL0(_offs, _aclkm) \ 32811551005SXing Zheng { \ 32911551005SXing Zheng .reg = RK3399_CLKSEL_CON(0 + _offs), \ 33011551005SXing Zheng .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \ 33111551005SXing Zheng RK3399_DIV_ACLKM_SHIFT), \ 33211551005SXing Zheng } 33311551005SXing Zheng #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \ 33411551005SXing Zheng { \ 33511551005SXing Zheng .reg = RK3399_CLKSEL_CON(1 + _offs), \ 33611551005SXing Zheng .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \ 33711551005SXing Zheng RK3399_DIV_ATCLK_SHIFT) | \ 33811551005SXing Zheng HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \ 33911551005SXing Zheng RK3399_DIV_PCLK_DBG_SHIFT), \ 34011551005SXing Zheng } 34111551005SXing Zheng 34211551005SXing Zheng /* cluster_l: aclkm in clksel0, rest in clksel1 */ 34311551005SXing Zheng #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \ 34411551005SXing Zheng { \ 34511551005SXing Zheng .prate = _prate##U, \ 34611551005SXing Zheng .divs = { \ 34711551005SXing Zheng RK3399_CLKSEL0(0, _aclkm), \ 34811551005SXing Zheng RK3399_CLKSEL1(0, _atclk, _pdbg), \ 34911551005SXing Zheng }, \ 35011551005SXing Zheng } 35111551005SXing Zheng 35211551005SXing Zheng /* cluster_b: aclkm in clksel2, rest in clksel3 */ 35311551005SXing Zheng #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \ 35411551005SXing Zheng { \ 35511551005SXing Zheng .prate = _prate##U, \ 35611551005SXing Zheng .divs = { \ 35711551005SXing Zheng RK3399_CLKSEL0(2, _aclkm), \ 35811551005SXing Zheng RK3399_CLKSEL1(2, _atclk, _pdbg), \ 35911551005SXing Zheng }, \ 36011551005SXing Zheng } 36111551005SXing Zheng 36211551005SXing Zheng static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = { 36311551005SXing Zheng RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8), 36411551005SXing Zheng RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8), 36511551005SXing Zheng RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7), 36611551005SXing Zheng RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7), 36711551005SXing Zheng RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6), 36811551005SXing Zheng RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6), 36911551005SXing Zheng RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5), 37011551005SXing Zheng RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5), 37111551005SXing Zheng RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4), 37211551005SXing Zheng RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3), 37311551005SXing Zheng RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3), 37411551005SXing Zheng RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2), 37511551005SXing Zheng RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1), 376aa2897ceSXing Zheng RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1), 377aa2897ceSXing Zheng RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1), 37811551005SXing Zheng }; 37911551005SXing Zheng 38011551005SXing Zheng static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = { 38111551005SXing Zheng RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11), 38211551005SXing Zheng RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11), 38311551005SXing Zheng RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10), 38411551005SXing Zheng RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10), 385fd75b345SShunqian Zheng RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9), 38611551005SXing Zheng RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9), 38711551005SXing Zheng RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9), 38811551005SXing Zheng RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8), 38911551005SXing Zheng RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8), 39011551005SXing Zheng RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7), 39111551005SXing Zheng RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7), 39211551005SXing Zheng RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6), 39311551005SXing Zheng RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6), 39411551005SXing Zheng RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5), 39511551005SXing Zheng RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5), 39611551005SXing Zheng RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4), 39711551005SXing Zheng RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3), 39811551005SXing Zheng RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3), 39911551005SXing Zheng RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2), 40011551005SXing Zheng RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1), 401aa2897ceSXing Zheng RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1), 402aa2897ceSXing Zheng RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1), 40311551005SXing Zheng }; 40411551005SXing Zheng 40511551005SXing Zheng static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 40611551005SXing Zheng /* 40711551005SXing Zheng * CRU Clock-Architecture 40811551005SXing Zheng */ 40911551005SXing Zheng 41011551005SXing Zheng /* usbphy */ 41111551005SXing Zheng GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED, 41211551005SXing Zheng RK3399_CLKGATE_CON(6), 5, GFLAGS), 41311551005SXing Zheng GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED, 41411551005SXing Zheng RK3399_CLKGATE_CON(6), 6, GFLAGS), 41511551005SXing Zheng 416161baaeaSJianqun Xu GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0, 41711551005SXing Zheng RK3399_CLKGATE_CON(13), 12, GFLAGS), 418161baaeaSJianqun Xu GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0, 41911551005SXing Zheng RK3399_CLKGATE_CON(13), 12, GFLAGS), 420161baaeaSJianqun Xu MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0, 42111551005SXing Zheng RK3399_CLKSEL_CON(14), 6, 1, MFLAGS), 42211551005SXing Zheng 42311551005SXing Zheng MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0, 42411551005SXing Zheng RK3399_CLKSEL_CON(14), 15, 1, MFLAGS), 42511551005SXing Zheng 42650961e83SXing Zheng COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0, 42711551005SXing Zheng RK3399_CLKSEL_CON(19), 0, 2, MFLAGS, 42811551005SXing Zheng RK3399_CLKGATE_CON(6), 4, GFLAGS), 42911551005SXing Zheng 43050961e83SXing Zheng COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0, 43111551005SXing Zheng RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, 43211551005SXing Zheng RK3399_CLKGATE_CON(12), 0, GFLAGS), 43311551005SXing Zheng GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED, 43411551005SXing Zheng RK3399_CLKGATE_CON(30), 0, GFLAGS), 43550961e83SXing Zheng GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0, 43611551005SXing Zheng RK3399_CLKGATE_CON(30), 1, GFLAGS), 43750961e83SXing Zheng GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0, 43811551005SXing Zheng RK3399_CLKGATE_CON(30), 2, GFLAGS), 43950961e83SXing Zheng GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0, 44011551005SXing Zheng RK3399_CLKGATE_CON(30), 3, GFLAGS), 44150961e83SXing Zheng GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0, 44211551005SXing Zheng RK3399_CLKGATE_CON(30), 4, GFLAGS), 44311551005SXing Zheng 44450961e83SXing Zheng GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0, 44511551005SXing Zheng RK3399_CLKGATE_CON(12), 1, GFLAGS), 44650961e83SXing Zheng GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0, 44711551005SXing Zheng RK3399_CLKGATE_CON(12), 2, GFLAGS), 44811551005SXing Zheng 44950961e83SXing Zheng COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0, 45011551005SXing Zheng RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS, 45111551005SXing Zheng RK3399_CLKGATE_CON(12), 3, GFLAGS), 45211551005SXing Zheng 45350961e83SXing Zheng COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0, 45411551005SXing Zheng RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS, 45511551005SXing Zheng RK3399_CLKGATE_CON(12), 4, GFLAGS), 45611551005SXing Zheng 45750961e83SXing Zheng COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0, 45811551005SXing Zheng RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS, 45911551005SXing Zheng RK3399_CLKGATE_CON(13), 4, GFLAGS), 46011551005SXing Zheng 46150961e83SXing Zheng COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, 46211551005SXing Zheng RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS, 46311551005SXing Zheng RK3399_CLKGATE_CON(13), 5, GFLAGS), 46411551005SXing Zheng 46550961e83SXing Zheng COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0, 46611551005SXing Zheng RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS, 46711551005SXing Zheng RK3399_CLKGATE_CON(13), 6, GFLAGS), 46811551005SXing Zheng 46950961e83SXing Zheng COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0, 47011551005SXing Zheng RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS, 47111551005SXing Zheng RK3399_CLKGATE_CON(13), 7, GFLAGS), 47211551005SXing Zheng 47311551005SXing Zheng /* little core */ 47411551005SXing Zheng GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED, 47511551005SXing Zheng RK3399_CLKGATE_CON(0), 0, GFLAGS), 47611551005SXing Zheng GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED, 47711551005SXing Zheng RK3399_CLKGATE_CON(0), 1, GFLAGS), 47811551005SXing Zheng GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED, 47911551005SXing Zheng RK3399_CLKGATE_CON(0), 2, GFLAGS), 48011551005SXing Zheng GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED, 48111551005SXing Zheng RK3399_CLKGATE_CON(0), 3, GFLAGS), 48211551005SXing Zheng 48311551005SXing Zheng COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED, 48411551005SXing Zheng RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 48511551005SXing Zheng RK3399_CLKGATE_CON(0), 4, GFLAGS), 48611551005SXing Zheng COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED, 48711551005SXing Zheng RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 48811551005SXing Zheng RK3399_CLKGATE_CON(0), 5, GFLAGS), 48911551005SXing Zheng COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED, 49011551005SXing Zheng RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 49111551005SXing Zheng RK3399_CLKGATE_CON(0), 6, GFLAGS), 49211551005SXing Zheng 49311551005SXing Zheng GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED, 49411551005SXing Zheng RK3399_CLKGATE_CON(14), 12, GFLAGS), 49511551005SXing Zheng GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, 49611551005SXing Zheng RK3399_CLKGATE_CON(14), 13, GFLAGS), 49711551005SXing Zheng 49811551005SXing Zheng GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, 49911551005SXing Zheng RK3399_CLKGATE_CON(14), 9, GFLAGS), 50011551005SXing Zheng GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED, 50111551005SXing Zheng RK3399_CLKGATE_CON(14), 10, GFLAGS), 50211551005SXing Zheng GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED, 50311551005SXing Zheng RK3399_CLKGATE_CON(14), 11, GFLAGS), 504161baaeaSJianqun Xu GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 50511551005SXing Zheng RK3399_CLKGATE_CON(0), 7, GFLAGS), 50611551005SXing Zheng 50711551005SXing Zheng /* big core */ 50811551005SXing Zheng GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED, 50911551005SXing Zheng RK3399_CLKGATE_CON(1), 0, GFLAGS), 51011551005SXing Zheng GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED, 51111551005SXing Zheng RK3399_CLKGATE_CON(1), 1, GFLAGS), 51211551005SXing Zheng GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED, 51311551005SXing Zheng RK3399_CLKGATE_CON(1), 2, GFLAGS), 51411551005SXing Zheng GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED, 51511551005SXing Zheng RK3399_CLKGATE_CON(1), 3, GFLAGS), 51611551005SXing Zheng 51711551005SXing Zheng COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED, 51811551005SXing Zheng RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 51911551005SXing Zheng RK3399_CLKGATE_CON(1), 4, GFLAGS), 52011551005SXing Zheng COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED, 52111551005SXing Zheng RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 52211551005SXing Zheng RK3399_CLKGATE_CON(1), 5, GFLAGS), 52311551005SXing Zheng COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED, 52411551005SXing Zheng RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 52511551005SXing Zheng RK3399_CLKGATE_CON(1), 6, GFLAGS), 52611551005SXing Zheng 52711551005SXing Zheng GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED, 52811551005SXing Zheng RK3399_CLKGATE_CON(14), 5, GFLAGS), 52911551005SXing Zheng GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, 53011551005SXing Zheng RK3399_CLKGATE_CON(14), 6, GFLAGS), 53111551005SXing Zheng 53211551005SXing Zheng GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, 53311551005SXing Zheng RK3399_CLKGATE_CON(14), 1, GFLAGS), 53411551005SXing Zheng GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED, 53511551005SXing Zheng RK3399_CLKGATE_CON(14), 3, GFLAGS), 53611551005SXing Zheng GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED, 53711551005SXing Zheng RK3399_CLKGATE_CON(14), 4, GFLAGS), 53811551005SXing Zheng 53911551005SXing Zheng DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 54011551005SXing Zheng RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY), 54111551005SXing Zheng 54211551005SXing Zheng GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, 54311551005SXing Zheng RK3399_CLKGATE_CON(14), 2, GFLAGS), 54411551005SXing Zheng 545161baaeaSJianqun Xu GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0, 54611551005SXing Zheng RK3399_CLKGATE_CON(1), 7, GFLAGS), 54711551005SXing Zheng 54811551005SXing Zheng /* gmac */ 54911551005SXing Zheng GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED, 55011551005SXing Zheng RK3399_CLKGATE_CON(6), 9, GFLAGS), 55111551005SXing Zheng GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED, 55211551005SXing Zheng RK3399_CLKGATE_CON(6), 8, GFLAGS), 55350961e83SXing Zheng COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0, 55411551005SXing Zheng RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS, 55511551005SXing Zheng RK3399_CLKGATE_CON(6), 10, GFLAGS), 55611551005SXing Zheng 55750961e83SXing Zheng GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, 55811551005SXing Zheng RK3399_CLKGATE_CON(32), 0, GFLAGS), 55911551005SXing Zheng GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 56011551005SXing Zheng RK3399_CLKGATE_CON(32), 1, GFLAGS), 56150961e83SXing Zheng GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0, 56211551005SXing Zheng RK3399_CLKGATE_CON(32), 4, GFLAGS), 56311551005SXing Zheng 56411551005SXing Zheng COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, 56511551005SXing Zheng RK3399_CLKSEL_CON(19), 8, 3, DFLAGS, 56611551005SXing Zheng RK3399_CLKGATE_CON(6), 11, GFLAGS), 56750961e83SXing Zheng GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, 56811551005SXing Zheng RK3399_CLKGATE_CON(32), 2, GFLAGS), 56911551005SXing Zheng GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED, 57011551005SXing Zheng RK3399_CLKGATE_CON(32), 3, GFLAGS), 57111551005SXing Zheng 57250961e83SXing Zheng COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0, 57311551005SXing Zheng RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, 57411551005SXing Zheng RK3399_CLKGATE_CON(5), 5, GFLAGS), 57511551005SXing Zheng 5763f92a054SXing Zheng MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT, 57711551005SXing Zheng RK3399_CLKSEL_CON(19), 4, 1, MFLAGS), 57850961e83SXing Zheng GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0, 57911551005SXing Zheng RK3399_CLKGATE_CON(5), 6, GFLAGS), 58050961e83SXing Zheng GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0, 58111551005SXing Zheng RK3399_CLKGATE_CON(5), 7, GFLAGS), 58250961e83SXing Zheng GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0, 58311551005SXing Zheng RK3399_CLKGATE_CON(5), 8, GFLAGS), 58450961e83SXing Zheng GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0, 58511551005SXing Zheng RK3399_CLKGATE_CON(5), 9, GFLAGS), 58611551005SXing Zheng 58711551005SXing Zheng /* spdif */ 58850961e83SXing Zheng COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0, 58911551005SXing Zheng RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS, 59011551005SXing Zheng RK3399_CLKGATE_CON(8), 13, GFLAGS), 59129edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0, 59211551005SXing Zheng RK3399_CLKSEL_CON(99), 0, 59311551005SXing Zheng RK3399_CLKGATE_CON(8), 14, GFLAGS, 59411551005SXing Zheng &rk3399_spdif_fracmux), 59511551005SXing Zheng GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT, 59611551005SXing Zheng RK3399_CLKGATE_CON(8), 15, GFLAGS), 59711551005SXing Zheng 59850961e83SXing Zheng COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, 5993770821fSXing Zheng RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, 60011551005SXing Zheng RK3399_CLKGATE_CON(10), 6, GFLAGS), 60111551005SXing Zheng /* i2s */ 60250961e83SXing Zheng COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, 60311551005SXing Zheng RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS, 60411551005SXing Zheng RK3399_CLKGATE_CON(8), 3, GFLAGS), 60529edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0, 60611551005SXing Zheng RK3399_CLKSEL_CON(96), 0, 60711551005SXing Zheng RK3399_CLKGATE_CON(8), 4, GFLAGS, 60811551005SXing Zheng &rk3399_i2s0_fracmux), 60911551005SXing Zheng GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT, 61011551005SXing Zheng RK3399_CLKGATE_CON(8), 5, GFLAGS), 61111551005SXing Zheng 61250961e83SXing Zheng COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0, 61311551005SXing Zheng RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS, 61411551005SXing Zheng RK3399_CLKGATE_CON(8), 6, GFLAGS), 61529edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0, 61611551005SXing Zheng RK3399_CLKSEL_CON(97), 0, 61711551005SXing Zheng RK3399_CLKGATE_CON(8), 7, GFLAGS, 61811551005SXing Zheng &rk3399_i2s1_fracmux), 61911551005SXing Zheng GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, 62011551005SXing Zheng RK3399_CLKGATE_CON(8), 8, GFLAGS), 62111551005SXing Zheng 62250961e83SXing Zheng COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0, 62311551005SXing Zheng RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS, 62411551005SXing Zheng RK3399_CLKGATE_CON(8), 9, GFLAGS), 62529edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0, 62611551005SXing Zheng RK3399_CLKSEL_CON(98), 0, 62711551005SXing Zheng RK3399_CLKGATE_CON(8), 10, GFLAGS, 62811551005SXing Zheng &rk3399_i2s2_fracmux), 62911551005SXing Zheng GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, 63011551005SXing Zheng RK3399_CLKGATE_CON(8), 11, GFLAGS), 63111551005SXing Zheng 63211551005SXing Zheng MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, 63311551005SXing Zheng RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), 63411551005SXing Zheng COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, 635a64ad008SAlberto Panizzo RK3399_CLKSEL_CON(31), 2, 1, MFLAGS, 63611551005SXing Zheng RK3399_CLKGATE_CON(8), 12, GFLAGS), 63711551005SXing Zheng 63811551005SXing Zheng /* uart */ 63911551005SXing Zheng MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0, 64011551005SXing Zheng RK3399_CLKSEL_CON(33), 12, 2, MFLAGS), 64111551005SXing Zheng COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0, 64211551005SXing Zheng RK3399_CLKSEL_CON(33), 0, 7, DFLAGS, 64311551005SXing Zheng RK3399_CLKGATE_CON(9), 0, GFLAGS), 64429edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0, 64511551005SXing Zheng RK3399_CLKSEL_CON(100), 0, 64611551005SXing Zheng RK3399_CLKGATE_CON(9), 1, GFLAGS, 64711551005SXing Zheng &rk3399_uart0_fracmux), 64811551005SXing Zheng 64911551005SXing Zheng MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0, 65011551005SXing Zheng RK3399_CLKSEL_CON(33), 15, 1, MFLAGS), 65111551005SXing Zheng COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0, 65211551005SXing Zheng RK3399_CLKSEL_CON(34), 0, 7, DFLAGS, 65311551005SXing Zheng RK3399_CLKGATE_CON(9), 2, GFLAGS), 65429edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0, 65511551005SXing Zheng RK3399_CLKSEL_CON(101), 0, 65611551005SXing Zheng RK3399_CLKGATE_CON(9), 3, GFLAGS, 65711551005SXing Zheng &rk3399_uart1_fracmux), 65811551005SXing Zheng 65911551005SXing Zheng COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0, 66011551005SXing Zheng RK3399_CLKSEL_CON(35), 0, 7, DFLAGS, 66111551005SXing Zheng RK3399_CLKGATE_CON(9), 4, GFLAGS), 66229edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0, 66311551005SXing Zheng RK3399_CLKSEL_CON(102), 0, 66411551005SXing Zheng RK3399_CLKGATE_CON(9), 5, GFLAGS, 66511551005SXing Zheng &rk3399_uart2_fracmux), 66611551005SXing Zheng 66711551005SXing Zheng COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0, 66811551005SXing Zheng RK3399_CLKSEL_CON(36), 0, 7, DFLAGS, 66911551005SXing Zheng RK3399_CLKGATE_CON(9), 6, GFLAGS), 67029edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0, 67111551005SXing Zheng RK3399_CLKSEL_CON(103), 0, 67211551005SXing Zheng RK3399_CLKGATE_CON(9), 7, GFLAGS, 67311551005SXing Zheng &rk3399_uart3_fracmux), 67411551005SXing Zheng 6759dc486fdSLin Huang COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 67611551005SXing Zheng RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS, 67711551005SXing Zheng RK3399_CLKGATE_CON(3), 4, GFLAGS), 67811551005SXing Zheng 67911551005SXing Zheng GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED, 68011551005SXing Zheng RK3399_CLKGATE_CON(18), 10, GFLAGS), 681161baaeaSJianqun Xu GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0, 68211551005SXing Zheng RK3399_CLKGATE_CON(18), 12, GFLAGS), 68311551005SXing Zheng GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED, 68411551005SXing Zheng RK3399_CLKGATE_CON(18), 15, GFLAGS), 68511551005SXing Zheng GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED, 68611551005SXing Zheng RK3399_CLKGATE_CON(19), 2, GFLAGS), 68711551005SXing Zheng 688161baaeaSJianqun Xu GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0, 68911551005SXing Zheng RK3399_CLKGATE_CON(4), 11, GFLAGS), 690161baaeaSJianqun Xu GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0, 69111551005SXing Zheng RK3399_CLKGATE_CON(3), 5, GFLAGS), 692161baaeaSJianqun Xu GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0, 69311551005SXing Zheng RK3399_CLKGATE_CON(3), 6, GFLAGS), 69411551005SXing Zheng 69511551005SXing Zheng /* cci */ 69611551005SXing Zheng GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED, 69711551005SXing Zheng RK3399_CLKGATE_CON(2), 0, GFLAGS), 69811551005SXing Zheng GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED, 69911551005SXing Zheng RK3399_CLKGATE_CON(2), 1, GFLAGS), 70011551005SXing Zheng GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED, 70111551005SXing Zheng RK3399_CLKGATE_CON(2), 2, GFLAGS), 70211551005SXing Zheng GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED, 70311551005SXing Zheng RK3399_CLKGATE_CON(2), 3, GFLAGS), 70411551005SXing Zheng 70511551005SXing Zheng COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED, 70611551005SXing Zheng RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, 70711551005SXing Zheng RK3399_CLKGATE_CON(2), 4, GFLAGS), 70811551005SXing Zheng 70911551005SXing Zheng GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, 71011551005SXing Zheng RK3399_CLKGATE_CON(15), 0, GFLAGS), 71111551005SXing Zheng GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, 71211551005SXing Zheng RK3399_CLKGATE_CON(15), 1, GFLAGS), 71311551005SXing Zheng GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, 71411551005SXing Zheng RK3399_CLKGATE_CON(15), 2, GFLAGS), 71511551005SXing Zheng GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED, 71611551005SXing Zheng RK3399_CLKGATE_CON(15), 3, GFLAGS), 71711551005SXing Zheng GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED, 71811551005SXing Zheng RK3399_CLKGATE_CON(15), 4, GFLAGS), 71911551005SXing Zheng GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED, 72011551005SXing Zheng RK3399_CLKGATE_CON(15), 7, GFLAGS), 72111551005SXing Zheng 72211551005SXing Zheng GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED, 72311551005SXing Zheng RK3399_CLKGATE_CON(2), 5, GFLAGS), 72411551005SXing Zheng GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED, 72511551005SXing Zheng RK3399_CLKGATE_CON(2), 6, GFLAGS), 72611551005SXing Zheng COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED, 72711551005SXing Zheng RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS, 72811551005SXing Zheng RK3399_CLKGATE_CON(2), 7, GFLAGS), 72911551005SXing Zheng 73011551005SXing Zheng GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED, 73111551005SXing Zheng RK3399_CLKGATE_CON(2), 8, GFLAGS), 73211551005SXing Zheng GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED, 73311551005SXing Zheng RK3399_CLKGATE_CON(2), 9, GFLAGS), 73411551005SXing Zheng GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED, 73511551005SXing Zheng RK3399_CLKGATE_CON(2), 10, GFLAGS), 73611551005SXing Zheng COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED, 73711551005SXing Zheng RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS), 73811551005SXing Zheng GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED, 73911551005SXing Zheng RK3399_CLKGATE_CON(15), 5, GFLAGS), 74011551005SXing Zheng GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED, 74111551005SXing Zheng RK3399_CLKGATE_CON(15), 6, GFLAGS), 74211551005SXing Zheng 74311551005SXing Zheng /* vcodec */ 74411551005SXing Zheng COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 74511551005SXing Zheng RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS, 74611551005SXing Zheng RK3399_CLKGATE_CON(4), 0, GFLAGS), 74711551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 74811551005SXing Zheng RK3399_CLKSEL_CON(7), 8, 5, DFLAGS, 74911551005SXing Zheng RK3399_CLKGATE_CON(4), 1, GFLAGS), 75050961e83SXing Zheng GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, 75111551005SXing Zheng RK3399_CLKGATE_CON(17), 2, GFLAGS), 75211551005SXing Zheng GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED, 75311551005SXing Zheng RK3399_CLKGATE_CON(17), 3, GFLAGS), 75411551005SXing Zheng 75550961e83SXing Zheng GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, 75611551005SXing Zheng RK3399_CLKGATE_CON(17), 0, GFLAGS), 75711551005SXing Zheng GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED, 75811551005SXing Zheng RK3399_CLKGATE_CON(17), 1, GFLAGS), 75911551005SXing Zheng 76011551005SXing Zheng /* vdu */ 76150961e83SXing Zheng COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0, 76211551005SXing Zheng RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS, 76311551005SXing Zheng RK3399_CLKGATE_CON(4), 4, GFLAGS), 76450961e83SXing Zheng COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0, 76511551005SXing Zheng RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS, 76611551005SXing Zheng RK3399_CLKGATE_CON(4), 5, GFLAGS), 76711551005SXing Zheng 76811551005SXing Zheng COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 76911551005SXing Zheng RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS, 77011551005SXing Zheng RK3399_CLKGATE_CON(4), 2, GFLAGS), 77111551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0, 77211551005SXing Zheng RK3399_CLKSEL_CON(8), 8, 5, DFLAGS, 77311551005SXing Zheng RK3399_CLKGATE_CON(4), 3, GFLAGS), 77450961e83SXing Zheng GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0, 77511551005SXing Zheng RK3399_CLKGATE_CON(17), 10, GFLAGS), 77611551005SXing Zheng GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED, 77711551005SXing Zheng RK3399_CLKGATE_CON(17), 11, GFLAGS), 77811551005SXing Zheng 77950961e83SXing Zheng GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0, 78011551005SXing Zheng RK3399_CLKGATE_CON(17), 8, GFLAGS), 78111551005SXing Zheng GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED, 78211551005SXing Zheng RK3399_CLKGATE_CON(17), 9, GFLAGS), 78311551005SXing Zheng 78411551005SXing Zheng /* iep */ 78550961e83SXing Zheng COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 78611551005SXing Zheng RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, 78711551005SXing Zheng RK3399_CLKGATE_CON(4), 6, GFLAGS), 78811551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0, 78911551005SXing Zheng RK3399_CLKSEL_CON(10), 8, 5, DFLAGS, 79011551005SXing Zheng RK3399_CLKGATE_CON(4), 7, GFLAGS), 79150961e83SXing Zheng GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0, 79211551005SXing Zheng RK3399_CLKGATE_CON(16), 2, GFLAGS), 79311551005SXing Zheng GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED, 79411551005SXing Zheng RK3399_CLKGATE_CON(16), 3, GFLAGS), 79511551005SXing Zheng 79650961e83SXing Zheng GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, 79711551005SXing Zheng RK3399_CLKGATE_CON(16), 0, GFLAGS), 79811551005SXing Zheng GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, 79911551005SXing Zheng RK3399_CLKGATE_CON(16), 1, GFLAGS), 80011551005SXing Zheng 80111551005SXing Zheng /* rga */ 80250961e83SXing Zheng COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 80311551005SXing Zheng RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, 80411551005SXing Zheng RK3399_CLKGATE_CON(4), 10, GFLAGS), 80511551005SXing Zheng 80650961e83SXing Zheng COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0, 80711551005SXing Zheng RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, 80811551005SXing Zheng RK3399_CLKGATE_CON(4), 8, GFLAGS), 80911551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0, 81011551005SXing Zheng RK3399_CLKSEL_CON(11), 8, 5, DFLAGS, 81111551005SXing Zheng RK3399_CLKGATE_CON(4), 9, GFLAGS), 81250961e83SXing Zheng GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, 81311551005SXing Zheng RK3399_CLKGATE_CON(16), 10, GFLAGS), 81411551005SXing Zheng GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED, 81511551005SXing Zheng RK3399_CLKGATE_CON(16), 11, GFLAGS), 81611551005SXing Zheng 81750961e83SXing Zheng GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, 81811551005SXing Zheng RK3399_CLKGATE_CON(16), 8, GFLAGS), 81911551005SXing Zheng GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, 82011551005SXing Zheng RK3399_CLKGATE_CON(16), 9, GFLAGS), 82111551005SXing Zheng 82211551005SXing Zheng /* center */ 82311551005SXing Zheng COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 82411551005SXing Zheng RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, 82511551005SXing Zheng RK3399_CLKGATE_CON(3), 7, GFLAGS), 82611551005SXing Zheng GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED, 82711551005SXing Zheng RK3399_CLKGATE_CON(19), 0, GFLAGS), 82811551005SXing Zheng GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED, 82911551005SXing Zheng RK3399_CLKGATE_CON(19), 1, GFLAGS), 83011551005SXing Zheng 83111551005SXing Zheng /* gpu */ 83211551005SXing Zheng COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED, 83311551005SXing Zheng RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS, 83411551005SXing Zheng RK3399_CLKGATE_CON(13), 0, GFLAGS), 83550961e83SXing Zheng GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, 83611551005SXing Zheng RK3399_CLKGATE_CON(30), 8, GFLAGS), 83750961e83SXing Zheng GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0, 83811551005SXing Zheng RK3399_CLKGATE_CON(30), 10, GFLAGS), 83950961e83SXing Zheng GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0, 84011551005SXing Zheng RK3399_CLKGATE_CON(30), 11, GFLAGS), 84150961e83SXing Zheng GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0, 84211551005SXing Zheng RK3399_CLKGATE_CON(13), 1, GFLAGS), 84311551005SXing Zheng 84411551005SXing Zheng /* perihp */ 8453bd14ae9SXing Zheng GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED, 84611551005SXing Zheng RK3399_CLKGATE_CON(5), 1, GFLAGS), 8474608d96fSXing Zheng GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED, 8484608d96fSXing Zheng RK3399_CLKGATE_CON(5), 0, GFLAGS), 84911551005SXing Zheng COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED, 85011551005SXing Zheng RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS, 85111551005SXing Zheng RK3399_CLKGATE_CON(5), 2, GFLAGS), 85211551005SXing Zheng COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, 85311551005SXing Zheng RK3399_CLKSEL_CON(14), 8, 2, DFLAGS, 85411551005SXing Zheng RK3399_CLKGATE_CON(5), 3, GFLAGS), 85511551005SXing Zheng COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED, 85611551005SXing Zheng RK3399_CLKSEL_CON(14), 12, 2, DFLAGS, 85711551005SXing Zheng RK3399_CLKGATE_CON(5), 4, GFLAGS), 85811551005SXing Zheng 8594f4e0491SElaine Zhang GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0, 86011551005SXing Zheng RK3399_CLKGATE_CON(20), 2, GFLAGS), 8614f4e0491SElaine Zhang GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0, 86211551005SXing Zheng RK3399_CLKGATE_CON(20), 10, GFLAGS), 86311551005SXing Zheng GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED, 86411551005SXing Zheng RK3399_CLKGATE_CON(20), 12, GFLAGS), 86511551005SXing Zheng 86650961e83SXing Zheng GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0, 86711551005SXing Zheng RK3399_CLKGATE_CON(20), 5, GFLAGS), 86850961e83SXing Zheng GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0, 86911551005SXing Zheng RK3399_CLKGATE_CON(20), 6, GFLAGS), 87050961e83SXing Zheng GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0, 87111551005SXing Zheng RK3399_CLKGATE_CON(20), 7, GFLAGS), 87250961e83SXing Zheng GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0, 87311551005SXing Zheng RK3399_CLKGATE_CON(20), 8, GFLAGS), 87450961e83SXing Zheng GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0, 87511551005SXing Zheng RK3399_CLKGATE_CON(20), 9, GFLAGS), 87611551005SXing Zheng GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED, 87711551005SXing Zheng RK3399_CLKGATE_CON(20), 13, GFLAGS), 87811551005SXing Zheng GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED, 87911551005SXing Zheng RK3399_CLKGATE_CON(20), 15, GFLAGS), 88011551005SXing Zheng 88111551005SXing Zheng GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED, 88211551005SXing Zheng RK3399_CLKGATE_CON(20), 4, GFLAGS), 88350961e83SXing Zheng GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0, 88411551005SXing Zheng RK3399_CLKGATE_CON(20), 11, GFLAGS), 88511551005SXing Zheng GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED, 88611551005SXing Zheng RK3399_CLKGATE_CON(20), 14, GFLAGS), 88750961e83SXing Zheng GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0, 88811551005SXing Zheng RK3399_CLKGATE_CON(31), 8, GFLAGS), 88911551005SXing Zheng 89011551005SXing Zheng /* sdio & sdmmc */ 8919dc486fdSLin Huang COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0, 89211551005SXing Zheng RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS, 89311551005SXing Zheng RK3399_CLKGATE_CON(12), 13, GFLAGS), 89450961e83SXing Zheng GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0, 89511551005SXing Zheng RK3399_CLKGATE_CON(33), 8, GFLAGS), 89611551005SXing Zheng GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED, 89711551005SXing Zheng RK3399_CLKGATE_CON(33), 9, GFLAGS), 89811551005SXing Zheng 89950961e83SXing Zheng COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, 90011551005SXing Zheng RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS, 90111551005SXing Zheng RK3399_CLKGATE_CON(6), 0, GFLAGS), 90211551005SXing Zheng 90350961e83SXing Zheng COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, 90411551005SXing Zheng RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS, 90511551005SXing Zheng RK3399_CLKGATE_CON(6), 1, GFLAGS), 90611551005SXing Zheng 90784752e8dSDouglas Anderson MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), 90884752e8dSDouglas Anderson MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), 90911551005SXing Zheng 91011551005SXing Zheng MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), 91111551005SXing Zheng MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), 91211551005SXing Zheng 91311551005SXing Zheng /* pcie */ 91450961e83SXing Zheng COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0, 91511551005SXing Zheng RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS, 91611551005SXing Zheng RK3399_CLKGATE_CON(6), 2, GFLAGS), 91711551005SXing Zheng 91850961e83SXing Zheng COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0, 91911551005SXing Zheng RK3399_CLKSEL_CON(18), 11, 5, DFLAGS, 92011551005SXing Zheng RK3399_CLKGATE_CON(12), 6, GFLAGS), 92111551005SXing Zheng MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT, 92211551005SXing Zheng RK3399_CLKSEL_CON(18), 10, 1, MFLAGS), 92311551005SXing Zheng 92450961e83SXing Zheng COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0, 92511551005SXing Zheng RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS, 92611551005SXing Zheng RK3399_CLKGATE_CON(6), 3, GFLAGS), 92711551005SXing Zheng MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT, 92811551005SXing Zheng RK3399_CLKSEL_CON(18), 7, 1, MFLAGS), 92911551005SXing Zheng 93011551005SXing Zheng /* emmc */ 93150961e83SXing Zheng COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0, 93211551005SXing Zheng RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS, 93311551005SXing Zheng RK3399_CLKGATE_CON(6), 14, GFLAGS), 93411551005SXing Zheng 93511551005SXing Zheng GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED, 93611551005SXing Zheng RK3399_CLKGATE_CON(6), 13, GFLAGS), 93720c389e6SXing Zheng GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED, 93820c389e6SXing Zheng RK3399_CLKGATE_CON(6), 12, GFLAGS), 93911551005SXing Zheng COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED, 94011551005SXing Zheng RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS), 94111551005SXing Zheng GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED, 94211551005SXing Zheng RK3399_CLKGATE_CON(32), 8, GFLAGS), 94311551005SXing Zheng GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED, 94411551005SXing Zheng RK3399_CLKGATE_CON(32), 9, GFLAGS), 94511551005SXing Zheng GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED, 94611551005SXing Zheng RK3399_CLKGATE_CON(32), 10, GFLAGS), 94711551005SXing Zheng 94811551005SXing Zheng /* perilp0 */ 94911551005SXing Zheng GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED, 95011551005SXing Zheng RK3399_CLKGATE_CON(7), 1, GFLAGS), 95111551005SXing Zheng GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED, 95211551005SXing Zheng RK3399_CLKGATE_CON(7), 0, GFLAGS), 95311551005SXing Zheng COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED, 95411551005SXing Zheng RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS, 95511551005SXing Zheng RK3399_CLKGATE_CON(7), 2, GFLAGS), 95611551005SXing Zheng COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED, 95711551005SXing Zheng RK3399_CLKSEL_CON(23), 8, 2, DFLAGS, 95811551005SXing Zheng RK3399_CLKGATE_CON(7), 3, GFLAGS), 95911551005SXing Zheng COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0, 96011551005SXing Zheng RK3399_CLKSEL_CON(23), 12, 3, DFLAGS, 96111551005SXing Zheng RK3399_CLKGATE_CON(7), 4, GFLAGS), 96211551005SXing Zheng 96311551005SXing Zheng /* aclk_perilp0 gates */ 96411551005SXing Zheng GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS), 96511551005SXing Zheng GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS), 96611551005SXing Zheng GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS), 96711551005SXing Zheng GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS), 96811551005SXing Zheng GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS), 96911551005SXing Zheng GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS), 97011551005SXing Zheng GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS), 97111551005SXing Zheng GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS), 972161baaeaSJianqun Xu GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS), 97311551005SXing Zheng GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS), 97411551005SXing Zheng GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS), 97550961e83SXing Zheng GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS), 97611551005SXing Zheng 97711551005SXing Zheng /* hclk_perilp0 gates */ 97811551005SXing Zheng GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS), 97950961e83SXing Zheng GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS), 98050961e83SXing Zheng GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS), 98150961e83SXing Zheng GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS), 98250961e83SXing Zheng GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS), 98311551005SXing Zheng GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS), 98411551005SXing Zheng 98511551005SXing Zheng /* pclk_perilp0 gates */ 986161baaeaSJianqun Xu GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS), 98711551005SXing Zheng 98811551005SXing Zheng /* crypto */ 98950961e83SXing Zheng COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0, 99011551005SXing Zheng RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS, 99111551005SXing Zheng RK3399_CLKGATE_CON(7), 7, GFLAGS), 99211551005SXing Zheng 99350961e83SXing Zheng COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0, 99411551005SXing Zheng RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS, 99511551005SXing Zheng RK3399_CLKGATE_CON(7), 8, GFLAGS), 99611551005SXing Zheng 99711551005SXing Zheng /* cm0s_perilp */ 99850961e83SXing Zheng GATE(0, "cpll_fclk_cm0s_src", "cpll", 0, 99911551005SXing Zheng RK3399_CLKGATE_CON(7), 6, GFLAGS), 100050961e83SXing Zheng GATE(0, "gpll_fclk_cm0s_src", "gpll", 0, 100111551005SXing Zheng RK3399_CLKGATE_CON(7), 5, GFLAGS), 100250961e83SXing Zheng COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0, 100311551005SXing Zheng RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS, 100411551005SXing Zheng RK3399_CLKGATE_CON(7), 9, GFLAGS), 100511551005SXing Zheng 100611551005SXing Zheng /* fclk_cm0s gates */ 100750961e83SXing Zheng GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS), 100850961e83SXing Zheng GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS), 100950961e83SXing Zheng GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS), 101050961e83SXing Zheng GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS), 101111551005SXing Zheng GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS), 101211551005SXing Zheng 101311551005SXing Zheng /* perilp1 */ 101411551005SXing Zheng GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED, 101511551005SXing Zheng RK3399_CLKGATE_CON(8), 1, GFLAGS), 101611551005SXing Zheng GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED, 101711551005SXing Zheng RK3399_CLKGATE_CON(8), 0, GFLAGS), 101811551005SXing Zheng COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED, 101911551005SXing Zheng RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS), 102011551005SXing Zheng COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED, 102111551005SXing Zheng RK3399_CLKSEL_CON(25), 8, 3, DFLAGS, 102211551005SXing Zheng RK3399_CLKGATE_CON(8), 2, GFLAGS), 102311551005SXing Zheng 102411551005SXing Zheng /* hclk_perilp1 gates */ 102511551005SXing Zheng GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS), 102611551005SXing Zheng GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS), 102750961e83SXing Zheng GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS), 102850961e83SXing Zheng GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS), 102950961e83SXing Zheng GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS), 103050961e83SXing Zheng GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS), 103150961e83SXing Zheng GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS), 103250961e83SXing Zheng GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS), 103311551005SXing Zheng GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS), 103411551005SXing Zheng 103511551005SXing Zheng /* pclk_perilp1 gates */ 103611551005SXing Zheng GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS), 103711551005SXing Zheng GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS), 103811551005SXing Zheng GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS), 103911551005SXing Zheng GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS), 104011551005SXing Zheng GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS), 104111551005SXing Zheng GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS), 104211551005SXing Zheng GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS), 104311551005SXing Zheng GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS), 104411551005SXing Zheng GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS), 104511551005SXing Zheng GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS), 104611551005SXing Zheng GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS), 104711551005SXing Zheng GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS), 104811551005SXing Zheng GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS), 104911551005SXing Zheng GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS), 105011551005SXing Zheng GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS), 105111551005SXing Zheng GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS), 105211551005SXing Zheng GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS), 105311551005SXing Zheng GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS), 105411551005SXing Zheng GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS), 105511551005SXing Zheng GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS), 105611551005SXing Zheng GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS), 105711551005SXing Zheng 105811551005SXing Zheng /* saradc */ 105911551005SXing Zheng COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, 106011551005SXing Zheng RK3399_CLKSEL_CON(26), 8, 8, DFLAGS, 106111551005SXing Zheng RK3399_CLKGATE_CON(9), 11, GFLAGS), 106211551005SXing Zheng 106311551005SXing Zheng /* tsadc */ 106450961e83SXing Zheng COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0, 106511551005SXing Zheng RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS, 106611551005SXing Zheng RK3399_CLKGATE_CON(9), 10, GFLAGS), 106711551005SXing Zheng 106811551005SXing Zheng /* cif_testout */ 106911551005SXing Zheng MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, 107011551005SXing Zheng RK3399_CLKSEL_CON(38), 6, 2, MFLAGS), 107125fb42b1SEddie Cai COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0, 107211551005SXing Zheng RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS, 107311551005SXing Zheng RK3399_CLKGATE_CON(13), 14, GFLAGS), 107411551005SXing Zheng 107511551005SXing Zheng MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0, 107611551005SXing Zheng RK3399_CLKSEL_CON(38), 14, 2, MFLAGS), 107725fb42b1SEddie Cai COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0, 107811551005SXing Zheng RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS, 107911551005SXing Zheng RK3399_CLKGATE_CON(13), 15, GFLAGS), 108011551005SXing Zheng 108111551005SXing Zheng /* vio */ 108211551005SXing Zheng COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED, 108311551005SXing Zheng RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, 1084a3f457d9SChris Zhong RK3399_CLKGATE_CON(11), 0, GFLAGS), 108511551005SXing Zheng COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0, 108611551005SXing Zheng RK3399_CLKSEL_CON(43), 0, 5, DFLAGS, 108711551005SXing Zheng RK3399_CLKGATE_CON(11), 1, GFLAGS), 108811551005SXing Zheng 108911551005SXing Zheng GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED, 109011551005SXing Zheng RK3399_CLKGATE_CON(29), 0, GFLAGS), 109111551005SXing Zheng 109250961e83SXing Zheng GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0, 109311551005SXing Zheng RK3399_CLKGATE_CON(29), 1, GFLAGS), 109450961e83SXing Zheng GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0, 109511551005SXing Zheng RK3399_CLKGATE_CON(29), 2, GFLAGS), 109611551005SXing Zheng GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED, 109711551005SXing Zheng RK3399_CLKGATE_CON(29), 12, GFLAGS), 109811551005SXing Zheng 109911551005SXing Zheng /* hdcp */ 110050961e83SXing Zheng COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0, 110111551005SXing Zheng RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, 110211551005SXing Zheng RK3399_CLKGATE_CON(11), 12, GFLAGS), 110350961e83SXing Zheng COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0, 110411551005SXing Zheng RK3399_CLKSEL_CON(43), 5, 5, DFLAGS, 110511551005SXing Zheng RK3399_CLKGATE_CON(11), 3, GFLAGS), 110650961e83SXing Zheng COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0, 110711551005SXing Zheng RK3399_CLKSEL_CON(43), 10, 5, DFLAGS, 110811551005SXing Zheng RK3399_CLKGATE_CON(11), 10, GFLAGS), 110911551005SXing Zheng 111011551005SXing Zheng GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED, 111111551005SXing Zheng RK3399_CLKGATE_CON(29), 4, GFLAGS), 111250961e83SXing Zheng GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0, 111311551005SXing Zheng RK3399_CLKGATE_CON(29), 10, GFLAGS), 111411551005SXing Zheng 111511551005SXing Zheng GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED, 111611551005SXing Zheng RK3399_CLKGATE_CON(29), 5, GFLAGS), 111750961e83SXing Zheng GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0, 111811551005SXing Zheng RK3399_CLKGATE_CON(29), 9, GFLAGS), 111911551005SXing Zheng 112011551005SXing Zheng GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED, 112111551005SXing Zheng RK3399_CLKGATE_CON(29), 3, GFLAGS), 112250961e83SXing Zheng GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0, 112311551005SXing Zheng RK3399_CLKGATE_CON(29), 6, GFLAGS), 112450961e83SXing Zheng GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0, 112511551005SXing Zheng RK3399_CLKGATE_CON(29), 7, GFLAGS), 112650961e83SXing Zheng GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0, 112711551005SXing Zheng RK3399_CLKGATE_CON(29), 8, GFLAGS), 112850961e83SXing Zheng GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0, 112911551005SXing Zheng RK3399_CLKGATE_CON(29), 11, GFLAGS), 113011551005SXing Zheng 113111551005SXing Zheng /* edp */ 113250961e83SXing Zheng COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0, 113311551005SXing Zheng RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS, 113411551005SXing Zheng RK3399_CLKGATE_CON(11), 8, GFLAGS), 113511551005SXing Zheng 113650961e83SXing Zheng COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0, 11373e1531dbSXing Zheng RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS, 113811551005SXing Zheng RK3399_CLKGATE_CON(11), 11, GFLAGS), 113911551005SXing Zheng GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED, 114011551005SXing Zheng RK3399_CLKGATE_CON(32), 12, GFLAGS), 114150961e83SXing Zheng GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0, 114211551005SXing Zheng RK3399_CLKGATE_CON(32), 13, GFLAGS), 114311551005SXing Zheng 114411551005SXing Zheng /* hdmi */ 114550961e83SXing Zheng GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0, 114611551005SXing Zheng RK3399_CLKGATE_CON(11), 6, GFLAGS), 114711551005SXing Zheng 114850961e83SXing Zheng COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0, 114911551005SXing Zheng RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS, 115011551005SXing Zheng RK3399_CLKGATE_CON(11), 7, GFLAGS), 115111551005SXing Zheng 115211551005SXing Zheng /* vop0 */ 115350961e83SXing Zheng COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, 115411551005SXing Zheng RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS, 115511551005SXing Zheng RK3399_CLKGATE_CON(10), 8, GFLAGS), 115611551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0, 115711551005SXing Zheng RK3399_CLKSEL_CON(47), 8, 5, DFLAGS, 115811551005SXing Zheng RK3399_CLKGATE_CON(10), 9, GFLAGS), 115911551005SXing Zheng 116050961e83SXing Zheng GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0, 116111551005SXing Zheng RK3399_CLKGATE_CON(28), 3, GFLAGS), 116211551005SXing Zheng GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED, 116311551005SXing Zheng RK3399_CLKGATE_CON(28), 1, GFLAGS), 116411551005SXing Zheng 116550961e83SXing Zheng GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0, 116611551005SXing Zheng RK3399_CLKGATE_CON(28), 2, GFLAGS), 116711551005SXing Zheng GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, 116811551005SXing Zheng RK3399_CLKGATE_CON(28), 0, GFLAGS), 116911551005SXing Zheng 117050961e83SXing Zheng COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0, 117111551005SXing Zheng RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS, 117211551005SXing Zheng RK3399_CLKGATE_CON(10), 12, GFLAGS), 117311551005SXing Zheng 11747b0f9e35SYakir Yang COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0, 117511551005SXing Zheng RK3399_CLKSEL_CON(106), 0, 117611551005SXing Zheng &rk3399_dclk_vop0_fracmux), 117711551005SXing Zheng 117850961e83SXing Zheng COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0, 117911551005SXing Zheng RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, 118011551005SXing Zheng RK3399_CLKGATE_CON(10), 14, GFLAGS), 118111551005SXing Zheng 118211551005SXing Zheng /* vop1 */ 118350961e83SXing Zheng COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0, 118411551005SXing Zheng RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, 118511551005SXing Zheng RK3399_CLKGATE_CON(10), 10, GFLAGS), 118611551005SXing Zheng COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0, 118711551005SXing Zheng RK3399_CLKSEL_CON(48), 8, 5, DFLAGS, 118811551005SXing Zheng RK3399_CLKGATE_CON(10), 11, GFLAGS), 118911551005SXing Zheng 119050961e83SXing Zheng GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0, 119111551005SXing Zheng RK3399_CLKGATE_CON(28), 7, GFLAGS), 119211551005SXing Zheng GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED, 119311551005SXing Zheng RK3399_CLKGATE_CON(28), 5, GFLAGS), 119411551005SXing Zheng 119550961e83SXing Zheng GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0, 119611551005SXing Zheng RK3399_CLKGATE_CON(28), 6, GFLAGS), 119711551005SXing Zheng GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED, 119811551005SXing Zheng RK3399_CLKGATE_CON(28), 4, GFLAGS), 119911551005SXing Zheng 120050961e83SXing Zheng COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0, 120111551005SXing Zheng RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS, 120211551005SXing Zheng RK3399_CLKGATE_CON(10), 13, GFLAGS), 120311551005SXing Zheng 12047b0f9e35SYakir Yang COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0, 120511551005SXing Zheng RK3399_CLKSEL_CON(107), 0, 120611551005SXing Zheng &rk3399_dclk_vop1_fracmux), 120711551005SXing Zheng 120811551005SXing Zheng COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED, 120911551005SXing Zheng RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS, 121011551005SXing Zheng RK3399_CLKGATE_CON(10), 15, GFLAGS), 121111551005SXing Zheng 121211551005SXing Zheng /* isp */ 121350961e83SXing Zheng COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0, 121411551005SXing Zheng RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS, 121511551005SXing Zheng RK3399_CLKGATE_CON(12), 8, GFLAGS), 12163f92a054SXing Zheng COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0, 121711551005SXing Zheng RK3399_CLKSEL_CON(53), 8, 5, DFLAGS, 121811551005SXing Zheng RK3399_CLKGATE_CON(12), 9, GFLAGS), 121911551005SXing Zheng 122011551005SXing Zheng GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED, 122111551005SXing Zheng RK3399_CLKGATE_CON(27), 1, GFLAGS), 122250961e83SXing Zheng GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0, 122311551005SXing Zheng RK3399_CLKGATE_CON(27), 5, GFLAGS), 122450961e83SXing Zheng GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0, 122511551005SXing Zheng RK3399_CLKGATE_CON(27), 7, GFLAGS), 122611551005SXing Zheng 122711551005SXing Zheng GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED, 122811551005SXing Zheng RK3399_CLKGATE_CON(27), 0, GFLAGS), 122950961e83SXing Zheng GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0, 123011551005SXing Zheng RK3399_CLKGATE_CON(27), 4, GFLAGS), 123111551005SXing Zheng 123250961e83SXing Zheng COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0, 123311551005SXing Zheng RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS, 123411551005SXing Zheng RK3399_CLKGATE_CON(11), 4, GFLAGS), 123511551005SXing Zheng 123650961e83SXing Zheng COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0, 123711551005SXing Zheng RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS, 123811551005SXing Zheng RK3399_CLKGATE_CON(12), 10, GFLAGS), 12393f92a054SXing Zheng COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0, 124011551005SXing Zheng RK3399_CLKSEL_CON(54), 8, 5, DFLAGS, 124111551005SXing Zheng RK3399_CLKGATE_CON(12), 11, GFLAGS), 124211551005SXing Zheng 124311551005SXing Zheng GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED, 124411551005SXing Zheng RK3399_CLKGATE_CON(27), 3, GFLAGS), 124511551005SXing Zheng 124611551005SXing Zheng GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED, 124711551005SXing Zheng RK3399_CLKGATE_CON(27), 2, GFLAGS), 124850961e83SXing Zheng GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0, 124911551005SXing Zheng RK3399_CLKGATE_CON(27), 8, GFLAGS), 125011551005SXing Zheng 125150961e83SXing Zheng COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0, 125211551005SXing Zheng RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS, 125311551005SXing Zheng RK3399_CLKGATE_CON(11), 5, GFLAGS), 125411551005SXing Zheng 125511551005SXing Zheng /* 125611551005SXing Zheng * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system, 125711551005SXing Zheng * so we ignore the mux and make clocks nodes as following, 125811551005SXing Zheng * 125911551005SXing Zheng * pclkin_cifinv --|-------\ 126011551005SXing Zheng * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper 126111551005SXing Zheng * pclkin_cif --|-------/ 126211551005SXing Zheng */ 126350961e83SXing Zheng GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0, 126411551005SXing Zheng RK3399_CLKGATE_CON(27), 6, GFLAGS), 126511551005SXing Zheng 126611551005SXing Zheng /* cif */ 1267fd8bc829SXing Zheng COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0, 1268fd8bc829SXing Zheng RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 126911551005SXing Zheng RK3399_CLKGATE_CON(10), 7, GFLAGS), 1270fd8bc829SXing Zheng 1271fd8bc829SXing Zheng COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, 1272fd8bc829SXing Zheng RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), 127311551005SXing Zheng 127411551005SXing Zheng /* gic */ 127511551005SXing Zheng COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 127611551005SXing Zheng RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS, 127711551005SXing Zheng RK3399_CLKGATE_CON(12), 12, GFLAGS), 127811551005SXing Zheng 127911551005SXing Zheng GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS), 128011551005SXing Zheng GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS), 128111551005SXing Zheng GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS), 128211551005SXing Zheng GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS), 128311551005SXing Zheng GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS), 128411551005SXing Zheng GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS), 128511551005SXing Zheng 128611551005SXing Zheng /* alive */ 128711551005SXing Zheng /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */ 128811551005SXing Zheng DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, 128911551005SXing Zheng RK3399_CLKSEL_CON(57), 0, 5, DFLAGS), 129011551005SXing Zheng 129111551005SXing Zheng GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS), 129211551005SXing Zheng GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS), 129311551005SXing Zheng GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS), 129411551005SXing Zheng GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS), 129511551005SXing Zheng GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS), 129611551005SXing Zheng 129711551005SXing Zheng GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS), 129811551005SXing Zheng GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS), 129950961e83SXing Zheng GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS), 130050961e83SXing Zheng GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS), 130150961e83SXing Zheng GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS), 130250961e83SXing Zheng GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS), 130350961e83SXing Zheng GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS), 130411551005SXing Zheng GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS), 130511551005SXing Zheng GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS), 130611551005SXing Zheng 1307e4488e45SHeiko Stuebner /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ 1308e4488e45SHeiko Stuebner SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"), 1309e4488e45SHeiko Stuebner 131050961e83SXing Zheng GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS), 131111551005SXing Zheng GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS), 131211551005SXing Zheng 131350961e83SXing Zheng GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS), 131411551005SXing Zheng GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS), 131511551005SXing Zheng GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS), 131611551005SXing Zheng GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS), 131711551005SXing Zheng 131811551005SXing Zheng /* testout */ 131911551005SXing Zheng MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT, 132011551005SXing Zheng RK3399_CLKSEL_CON(58), 7, 1, MFLAGS), 132129edeccbSDouglas Anderson COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0, 132211551005SXing Zheng RK3399_CLKSEL_CON(105), 0, 132311551005SXing Zheng RK3399_CLKGATE_CON(13), 9, GFLAGS), 132411551005SXing Zheng 132511551005SXing Zheng DIV(0, "clk_test_24m", "xin24m", 0, 132611551005SXing Zheng RK3399_CLKSEL_CON(57), 6, 10, DFLAGS), 132711551005SXing Zheng 132811551005SXing Zheng /* spi */ 132911551005SXing Zheng COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0, 133011551005SXing Zheng RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS, 133111551005SXing Zheng RK3399_CLKGATE_CON(9), 12, GFLAGS), 133211551005SXing Zheng 133311551005SXing Zheng COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0, 133411551005SXing Zheng RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS, 133511551005SXing Zheng RK3399_CLKGATE_CON(9), 13, GFLAGS), 133611551005SXing Zheng 133711551005SXing Zheng COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0, 133811551005SXing Zheng RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS, 133911551005SXing Zheng RK3399_CLKGATE_CON(9), 14, GFLAGS), 134011551005SXing Zheng 134111551005SXing Zheng COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0, 134211551005SXing Zheng RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS, 134311551005SXing Zheng RK3399_CLKGATE_CON(9), 15, GFLAGS), 134411551005SXing Zheng 134511551005SXing Zheng COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0, 134611551005SXing Zheng RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS, 134711551005SXing Zheng RK3399_CLKGATE_CON(13), 13, GFLAGS), 134811551005SXing Zheng 134911551005SXing Zheng /* i2c */ 135011551005SXing Zheng COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0, 135111551005SXing Zheng RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS, 135211551005SXing Zheng RK3399_CLKGATE_CON(10), 0, GFLAGS), 135311551005SXing Zheng 135411551005SXing Zheng COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0, 135511551005SXing Zheng RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS, 135611551005SXing Zheng RK3399_CLKGATE_CON(10), 2, GFLAGS), 135711551005SXing Zheng 135811551005SXing Zheng COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0, 135911551005SXing Zheng RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS, 136011551005SXing Zheng RK3399_CLKGATE_CON(10), 4, GFLAGS), 136111551005SXing Zheng 136211551005SXing Zheng COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0, 136311551005SXing Zheng RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS, 136411551005SXing Zheng RK3399_CLKGATE_CON(10), 1, GFLAGS), 136511551005SXing Zheng 136611551005SXing Zheng COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0, 136711551005SXing Zheng RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS, 136811551005SXing Zheng RK3399_CLKGATE_CON(10), 3, GFLAGS), 136911551005SXing Zheng 137011551005SXing Zheng COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0, 137111551005SXing Zheng RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS, 137211551005SXing Zheng RK3399_CLKGATE_CON(10), 5, GFLAGS), 137311551005SXing Zheng 137411551005SXing Zheng /* timer */ 137550961e83SXing Zheng GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS), 137650961e83SXing Zheng GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS), 137750961e83SXing Zheng GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS), 137850961e83SXing Zheng GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS), 137950961e83SXing Zheng GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS), 138050961e83SXing Zheng GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS), 138150961e83SXing Zheng GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS), 138250961e83SXing Zheng GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS), 138350961e83SXing Zheng GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS), 138450961e83SXing Zheng GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS), 138550961e83SXing Zheng GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS), 138650961e83SXing Zheng GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS), 138711551005SXing Zheng 138811551005SXing Zheng /* clk_test */ 138911551005SXing Zheng /* clk_test_pre is controlled by CRU_MISC_CON[3] */ 139011551005SXing Zheng COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, 13919c496033SJianqun Xu RK3399_CLKSEL_CON(58), 0, 5, DFLAGS, 13929c496033SJianqun Xu RK3399_CLKGATE_CON(13), 11, GFLAGS), 1393464b9eebSLin Huang 1394464b9eebSLin Huang /* ddrc */ 1395464b9eebSLin Huang GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), 1396464b9eebSLin Huang 0, GFLAGS), 1397464b9eebSLin Huang GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), 1398464b9eebSLin Huang 1, GFLAGS), 1399464b9eebSLin Huang GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), 1400464b9eebSLin Huang 2, GFLAGS), 1401464b9eebSLin Huang GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), 1402464b9eebSLin Huang 3, GFLAGS), 1403464b9eebSLin Huang COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0, 1404464b9eebSLin Huang RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP), 140511551005SXing Zheng }; 140611551005SXing Zheng 140711551005SXing Zheng static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { 140811551005SXing Zheng /* 140911551005SXing Zheng * PMU CRU Clock-Architecture 141011551005SXing Zheng */ 141111551005SXing Zheng 141250961e83SXing Zheng GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0, 141311551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS), 141411551005SXing Zheng 141550961e83SXing Zheng COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0, 141611551005SXing Zheng RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS), 141711551005SXing Zheng 141850961e83SXing Zheng COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0, 141911551005SXing Zheng RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS, 142011551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS), 142111551005SXing Zheng 142211551005SXing Zheng COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED, 142311551005SXing Zheng RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS, 142411551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS), 142511551005SXing Zheng 142629edeccbSDouglas Anderson COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0, 142711551005SXing Zheng RK3399_PMU_CLKSEL_CON(7), 0, 142811551005SXing Zheng &rk3399_pmuclk_wifi_fracmux), 142911551005SXing Zheng 143011551005SXing Zheng MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED, 143111551005SXing Zheng RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS), 143211551005SXing Zheng 143311551005SXing Zheng COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0, 143411551005SXing Zheng RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS, 143511551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS), 143611551005SXing Zheng 143711551005SXing Zheng COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0, 143811551005SXing Zheng RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS, 1439f3d40914SXing Zheng RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS), 144011551005SXing Zheng 144111551005SXing Zheng COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0, 144211551005SXing Zheng RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS, 1443f3d40914SXing Zheng RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS), 144411551005SXing Zheng 144511551005SXing Zheng DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED, 144611551005SXing Zheng RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS), 144711551005SXing Zheng MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, 144811551005SXing Zheng RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), 144911551005SXing Zheng 145050961e83SXing Zheng COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0, 145111551005SXing Zheng RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, 145211551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), 145311551005SXing Zheng 145429edeccbSDouglas Anderson COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0, 145511551005SXing Zheng RK3399_PMU_CLKSEL_CON(6), 0, 145611551005SXing Zheng RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS, 145711551005SXing Zheng &rk3399_uart4_pmu_fracmux), 145811551005SXing Zheng 145911551005SXing Zheng DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED, 146011551005SXing Zheng RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS), 146111551005SXing Zheng 146211551005SXing Zheng /* pmu clock gates */ 146350961e83SXing Zheng GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS), 146450961e83SXing Zheng GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS), 146511551005SXing Zheng 146611551005SXing Zheng GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS), 146711551005SXing Zheng 146811551005SXing Zheng GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS), 146911551005SXing Zheng GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS), 147011551005SXing Zheng GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS), 147150961e83SXing Zheng GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS), 147250961e83SXing Zheng GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS), 147311551005SXing Zheng GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS), 147411551005SXing Zheng GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS), 147550961e83SXing Zheng GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS), 147650961e83SXing Zheng GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS), 147750961e83SXing Zheng GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS), 147850961e83SXing Zheng GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS), 147950961e83SXing Zheng GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS), 148050961e83SXing Zheng GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS), 148150961e83SXing Zheng GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS), 148250961e83SXing Zheng GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), 148350961e83SXing Zheng GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), 148411551005SXing Zheng 148560aadea5SDouglas Anderson GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), 148660aadea5SDouglas Anderson GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), 148760aadea5SDouglas Anderson GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), 148860aadea5SDouglas Anderson GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), 148911551005SXing Zheng GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), 149011551005SXing Zheng }; 149111551005SXing Zheng 149211551005SXing Zheng static const char *const rk3399_cru_critical_clocks[] __initconst = { 149311551005SXing Zheng "aclk_cci_pre", 1494176df69cSBrian Norris "aclk_gic", 1495176df69cSBrian Norris "aclk_gic_noc", 149654479449SChris Zhong "aclk_hdcp_noc", 149754479449SChris Zhong "hclk_hdcp_noc", 149854479449SChris Zhong "pclk_hdcp_noc", 149911551005SXing Zheng "pclk_perilp0", 150011551005SXing Zheng "pclk_perilp0", 150111551005SXing Zheng "hclk_perilp0", 150211551005SXing Zheng "hclk_perilp0_noc", 150311551005SXing Zheng "pclk_perilp1", 150411551005SXing Zheng "pclk_perilp1_noc", 150511551005SXing Zheng "pclk_perihp", 150611551005SXing Zheng "pclk_perihp_noc", 150711551005SXing Zheng "hclk_perihp", 150811551005SXing Zheng "aclk_perihp", 150911551005SXing Zheng "aclk_perihp_noc", 151011551005SXing Zheng "aclk_perilp0", 151111551005SXing Zheng "aclk_perilp0_noc", 151211551005SXing Zheng "hclk_perilp1", 151311551005SXing Zheng "hclk_perilp1_noc", 151411551005SXing Zheng "aclk_dmac0_perilp", 1515a45f9d41SXing Zheng "aclk_emmc_noc", 151611551005SXing Zheng "gpll_hclk_perilp1_src", 151711551005SXing Zheng "gpll_aclk_perilp0_src", 151811551005SXing Zheng "gpll_aclk_perihp_src", 151954479449SChris Zhong "aclk_vio_noc", 1520464b9eebSLin Huang 1521464b9eebSLin Huang /* ddrc */ 1522464b9eebSLin Huang "sclk_ddrc" 152311551005SXing Zheng }; 152411551005SXing Zheng 152511551005SXing Zheng static const char *const rk3399_pmucru_critical_clocks[] __initconst = { 152611551005SXing Zheng "ppll", 152711551005SXing Zheng "pclk_pmu_src", 152811551005SXing Zheng "fclk_cm0s_src_pmu", 152911551005SXing Zheng "clk_timer_src_pmu", 1530640332d1SLevin Du "pclk_rkpwm_pmu", 153111551005SXing Zheng }; 153211551005SXing Zheng 153311551005SXing Zheng static void __init rk3399_clk_init(struct device_node *np) 153411551005SXing Zheng { 153511551005SXing Zheng struct rockchip_clk_provider *ctx; 153611551005SXing Zheng void __iomem *reg_base; 153711551005SXing Zheng 153811551005SXing Zheng reg_base = of_iomap(np, 0); 153911551005SXing Zheng if (!reg_base) { 154011551005SXing Zheng pr_err("%s: could not map cru region\n", __func__); 154111551005SXing Zheng return; 154211551005SXing Zheng } 154311551005SXing Zheng 154411551005SXing Zheng ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 154511551005SXing Zheng if (IS_ERR(ctx)) { 154611551005SXing Zheng pr_err("%s: rockchip clk init failed\n", __func__); 154762d0e71dSShawn Lin iounmap(reg_base); 154811551005SXing Zheng return; 154911551005SXing Zheng } 155011551005SXing Zheng 155111551005SXing Zheng rockchip_clk_register_plls(ctx, rk3399_pll_clks, 155211551005SXing Zheng ARRAY_SIZE(rk3399_pll_clks), -1); 155311551005SXing Zheng 155411551005SXing Zheng rockchip_clk_register_branches(ctx, rk3399_clk_branches, 155511551005SXing Zheng ARRAY_SIZE(rk3399_clk_branches)); 155611551005SXing Zheng 155711551005SXing Zheng rockchip_clk_protect_critical(rk3399_cru_critical_clocks, 155811551005SXing Zheng ARRAY_SIZE(rk3399_cru_critical_clocks)); 155911551005SXing Zheng 156011551005SXing Zheng rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", 156111551005SXing Zheng mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), 156211551005SXing Zheng &rk3399_cpuclkl_data, rk3399_cpuclkl_rates, 156311551005SXing Zheng ARRAY_SIZE(rk3399_cpuclkl_rates)); 156411551005SXing Zheng 156511551005SXing Zheng rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", 156611551005SXing Zheng mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), 156711551005SXing Zheng &rk3399_cpuclkb_data, rk3399_cpuclkb_rates, 156811551005SXing Zheng ARRAY_SIZE(rk3399_cpuclkb_rates)); 156911551005SXing Zheng 157011551005SXing Zheng rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0), 157111551005SXing Zheng ROCKCHIP_SOFTRST_HIWORD_MASK); 157211551005SXing Zheng 157311551005SXing Zheng rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL); 157411551005SXing Zheng 157511551005SXing Zheng rockchip_clk_of_add_provider(np, ctx); 157611551005SXing Zheng } 157711551005SXing Zheng CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init); 157811551005SXing Zheng 157911551005SXing Zheng static void __init rk3399_pmu_clk_init(struct device_node *np) 158011551005SXing Zheng { 158111551005SXing Zheng struct rockchip_clk_provider *ctx; 158211551005SXing Zheng void __iomem *reg_base; 158311551005SXing Zheng 158411551005SXing Zheng reg_base = of_iomap(np, 0); 158511551005SXing Zheng if (!reg_base) { 158611551005SXing Zheng pr_err("%s: could not map cru pmu region\n", __func__); 158711551005SXing Zheng return; 158811551005SXing Zheng } 158911551005SXing Zheng 159011551005SXing Zheng ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 159111551005SXing Zheng if (IS_ERR(ctx)) { 159211551005SXing Zheng pr_err("%s: rockchip pmu clk init failed\n", __func__); 159362d0e71dSShawn Lin iounmap(reg_base); 159411551005SXing Zheng return; 159511551005SXing Zheng } 159611551005SXing Zheng 159711551005SXing Zheng rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks, 159811551005SXing Zheng ARRAY_SIZE(rk3399_pmu_pll_clks), -1); 159911551005SXing Zheng 160011551005SXing Zheng rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches, 160111551005SXing Zheng ARRAY_SIZE(rk3399_clk_pmu_branches)); 160211551005SXing Zheng 160311551005SXing Zheng rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks, 160411551005SXing Zheng ARRAY_SIZE(rk3399_pmucru_critical_clocks)); 160511551005SXing Zheng 160611551005SXing Zheng rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), 160711551005SXing Zheng ROCKCHIP_SOFTRST_HIWORD_MASK); 160811551005SXing Zheng 160911551005SXing Zheng rockchip_clk_of_add_provider(np, ctx); 161011551005SXing Zheng } 161111551005SXing Zheng CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init); 1612