1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Elaine <zhangqing@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/syscore_ops.h> 20 #include <dt-bindings/clock/rk3328-cru.h> 21 #include "clk.h" 22 23 #define RK3328_GRF_SOC_CON4 0x410 24 #define RK3328_GRF_SOC_STATUS0 0x480 25 #define RK3328_GRF_MAC_CON1 0x904 26 #define RK3328_GRF_MAC_CON2 0x908 27 28 enum rk3328_plls { 29 apll, dpll, cpll, gpll, npll, 30 }; 31 32 static struct rockchip_pll_rate_table rk3328_pll_rates[] = { 33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 34 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 49 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 52 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 53 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 54 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 55 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 56 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), 57 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), 58 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), 59 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 60 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), 61 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), 62 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), 63 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), 64 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 65 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), 66 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), 67 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), 68 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 69 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 70 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), 71 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), 72 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 73 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), 74 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 75 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), 76 { /* sentinel */ }, 77 }; 78 79 static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = { 80 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 81 RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), 82 /* vco = 1016064000 */ 83 RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088), 84 /* vco = 983040000 */ 85 RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088), 86 /* vco = 983040000 */ 87 RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088), 88 /* vco = 860156000 */ 89 RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894), 90 /* vco = 903168000 */ 91 RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329), 92 /* vco = 819200000 */ 93 { /* sentinel */ }, 94 }; 95 96 #define RK3328_DIV_ACLKM_MASK 0x7 97 #define RK3328_DIV_ACLKM_SHIFT 4 98 #define RK3328_DIV_PCLK_DBG_MASK 0xf 99 #define RK3328_DIV_PCLK_DBG_SHIFT 0 100 101 #define RK3328_CLKSEL1(_aclk_core, _pclk_dbg) \ 102 { \ 103 .reg = RK3328_CLKSEL_CON(1), \ 104 .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \ 105 RK3328_DIV_ACLKM_SHIFT) | \ 106 HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \ 107 RK3328_DIV_PCLK_DBG_SHIFT), \ 108 } 109 110 #define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ 111 { \ 112 .prate = _prate, \ 113 .divs = { \ 114 RK3328_CLKSEL1(_aclk_core, _pclk_dbg), \ 115 }, \ 116 } 117 118 static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = { 119 RK3328_CPUCLK_RATE(1800000000, 1, 7), 120 RK3328_CPUCLK_RATE(1704000000, 1, 7), 121 RK3328_CPUCLK_RATE(1608000000, 1, 7), 122 RK3328_CPUCLK_RATE(1512000000, 1, 7), 123 RK3328_CPUCLK_RATE(1488000000, 1, 5), 124 RK3328_CPUCLK_RATE(1416000000, 1, 5), 125 RK3328_CPUCLK_RATE(1392000000, 1, 5), 126 RK3328_CPUCLK_RATE(1296000000, 1, 5), 127 RK3328_CPUCLK_RATE(1200000000, 1, 5), 128 RK3328_CPUCLK_RATE(1104000000, 1, 5), 129 RK3328_CPUCLK_RATE(1008000000, 1, 5), 130 RK3328_CPUCLK_RATE(912000000, 1, 5), 131 RK3328_CPUCLK_RATE(816000000, 1, 3), 132 RK3328_CPUCLK_RATE(696000000, 1, 3), 133 RK3328_CPUCLK_RATE(600000000, 1, 3), 134 RK3328_CPUCLK_RATE(408000000, 1, 1), 135 RK3328_CPUCLK_RATE(312000000, 1, 1), 136 RK3328_CPUCLK_RATE(216000000, 1, 1), 137 RK3328_CPUCLK_RATE(96000000, 1, 1), 138 }; 139 140 static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = { 141 .core_reg = RK3328_CLKSEL_CON(0), 142 .div_core_shift = 0, 143 .div_core_mask = 0x1f, 144 .mux_core_alt = 1, 145 .mux_core_main = 3, 146 .mux_core_shift = 6, 147 .mux_core_mask = 0x3, 148 }; 149 150 PNAME(mux_pll_p) = { "xin24m" }; 151 152 PNAME(mux_2plls_p) = { "cpll", "gpll" }; 153 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; 154 PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" }; 155 PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" }; 156 PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll", 157 "dummy_hdmiphy" }; 158 PNAME(mux_4plls_p) = { "cpll", "gpll", 159 "dummy_hdmiphy", 160 "usb480m" }; 161 PNAME(mux_2plls_u480m_p) = { "cpll", "gpll", 162 "usb480m" }; 163 PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll", 164 "xin24m", "usb480m" }; 165 166 PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" }; 167 PNAME(mux_armclk_p) = { "apll_core", 168 "gpll_core", 169 "dpll_core", 170 "npll_core"}; 171 PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" }; 172 PNAME(mux_usb480m_p) = { "usb480m_phy", 173 "xin24m" }; 174 175 PNAME(mux_i2s0_p) = { "clk_i2s0_div", 176 "clk_i2s0_frac", 177 "xin12m", 178 "xin12m" }; 179 PNAME(mux_i2s1_p) = { "clk_i2s1_div", 180 "clk_i2s1_frac", 181 "clkin_i2s1", 182 "xin12m" }; 183 PNAME(mux_i2s2_p) = { "clk_i2s2_div", 184 "clk_i2s2_frac", 185 "clkin_i2s2", 186 "xin12m" }; 187 PNAME(mux_i2s1out_p) = { "clk_i2s1", "xin12m"}; 188 PNAME(mux_i2s2out_p) = { "clk_i2s2", "xin12m" }; 189 PNAME(mux_spdif_p) = { "clk_spdif_div", 190 "clk_spdif_frac", 191 "xin12m", 192 "xin12m" }; 193 PNAME(mux_uart0_p) = { "clk_uart0_div", 194 "clk_uart0_frac", 195 "xin24m" }; 196 PNAME(mux_uart1_p) = { "clk_uart1_div", 197 "clk_uart1_frac", 198 "xin24m" }; 199 PNAME(mux_uart2_p) = { "clk_uart2_div", 200 "clk_uart2_frac", 201 "xin24m" }; 202 203 PNAME(mux_sclk_cif_p) = { "clk_cif_src", 204 "xin24m" }; 205 PNAME(mux_dclk_lcdc_p) = { "hdmiphy", 206 "dclk_lcdc_src" }; 207 PNAME(mux_aclk_peri_pre_p) = { "cpll_peri", 208 "gpll_peri", 209 "hdmiphy_peri" }; 210 PNAME(mux_ref_usb3otg_src_p) = { "xin24m", 211 "clk_usb3otg_ref" }; 212 PNAME(mux_xin24m_32k_p) = { "xin24m", 213 "clk_rtc32k" }; 214 PNAME(mux_mac2io_src_p) = { "clk_mac2io_src", 215 "gmac_clkin" }; 216 PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src", 217 "phy_50m_out" }; 218 PNAME(mux_mac2io_ext_p) = { "clk_mac2io", 219 "gmac_clkin" }; 220 221 static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = { 222 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 223 0, RK3328_PLL_CON(0), 224 RK3328_MODE_CON, 0, 4, 0, rk3328_pll_frac_rates), 225 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 226 0, RK3328_PLL_CON(8), 227 RK3328_MODE_CON, 4, 3, 0, NULL), 228 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 229 0, RK3328_PLL_CON(16), 230 RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates), 231 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 232 0, RK3328_PLL_CON(24), 233 RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates), 234 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 235 0, RK3328_PLL_CON(40), 236 RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates), 237 }; 238 239 #define MFLAGS CLK_MUX_HIWORD_MASK 240 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 241 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 242 243 static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata = 244 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, 245 RK3328_CLKSEL_CON(6), 8, 2, MFLAGS); 246 247 static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata = 248 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, 249 RK3328_CLKSEL_CON(8), 8, 2, MFLAGS); 250 251 static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata = 252 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, 253 RK3328_CLKSEL_CON(10), 8, 2, MFLAGS); 254 255 static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata = 256 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT, 257 RK3328_CLKSEL_CON(12), 8, 2, MFLAGS); 258 259 static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata = 260 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 261 RK3328_CLKSEL_CON(14), 8, 2, MFLAGS); 262 263 static struct rockchip_clk_branch rk3328_uart1_fracmux __initdata = 264 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 265 RK3328_CLKSEL_CON(16), 8, 2, MFLAGS); 266 267 static struct rockchip_clk_branch rk3328_uart2_fracmux __initdata = 268 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 269 RK3328_CLKSEL_CON(18), 8, 2, MFLAGS); 270 271 static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 272 /* 273 * Clock-Architecture Diagram 1 274 */ 275 276 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, 277 RK3328_CLKSEL_CON(2), 8, 5, DFLAGS), 278 COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0, 279 RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS, 280 RK3328_CLKGATE_CON(0), 11, GFLAGS), 281 282 /* PD_MISC */ 283 MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, 284 RK3328_MISC_CON, 13, 1, MFLAGS), 285 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 286 RK3328_MISC_CON, 15, 1, MFLAGS), 287 288 /* 289 * Clock-Architecture Diagram 2 290 */ 291 292 /* PD_CORE */ 293 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 294 RK3328_CLKGATE_CON(0), 0, GFLAGS), 295 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 296 RK3328_CLKGATE_CON(0), 2, GFLAGS), 297 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, 298 RK3328_CLKGATE_CON(0), 1, GFLAGS), 299 GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED, 300 RK3328_CLKGATE_CON(0), 12, GFLAGS), 301 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, 302 RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 303 RK3328_CLKGATE_CON(7), 0, GFLAGS), 304 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, 305 RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 306 RK3328_CLKGATE_CON(7), 1, GFLAGS), 307 GATE(0, "aclk_core_niu", "aclk_core", 0, 308 RK3328_CLKGATE_CON(13), 0, GFLAGS), 309 GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED, 310 RK3328_CLKGATE_CON(13), 1, GFLAGS), 311 312 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED, 313 RK3328_CLKGATE_CON(7), 2, GFLAGS), 314 315 /* PD_GPU */ 316 COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0, 317 RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS, 318 RK3328_CLKGATE_CON(6), 6, GFLAGS), 319 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT, 320 RK3328_CLKGATE_CON(14), 0, GFLAGS), 321 GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0, 322 RK3328_CLKGATE_CON(14), 1, GFLAGS), 323 324 /* PD_DDR */ 325 COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED, 326 RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 327 RK3328_CLKGATE_CON(0), 4, GFLAGS), 328 GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED, 329 RK3328_CLKGATE_CON(18), 6, GFLAGS), 330 GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, 331 RK3328_CLKGATE_CON(18), 5, GFLAGS), 332 GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, 333 RK3328_CLKGATE_CON(18), 4, GFLAGS), 334 GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED, 335 RK3328_CLKGATE_CON(0), 6, GFLAGS), 336 337 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0, 338 RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS, 339 RK3328_CLKGATE_CON(7), 4, GFLAGS), 340 GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED, 341 RK3328_CLKGATE_CON(18), 1, GFLAGS), 342 GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IGNORE_UNUSED, 343 RK3328_CLKGATE_CON(18), 2, GFLAGS), 344 GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, 345 RK3328_CLKGATE_CON(18), 3, GFLAGS), 346 GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED, 347 RK3328_CLKGATE_CON(18), 7, GFLAGS), 348 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, 349 RK3328_CLKGATE_CON(18), 9, GFLAGS), 350 351 /* 352 * Clock-Architecture Diagram 3 353 */ 354 355 /* PD_BUS */ 356 COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0, 357 RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS, 358 RK3328_CLKGATE_CON(8), 0, GFLAGS), 359 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", 0, 360 RK3328_CLKSEL_CON(1), 8, 2, DFLAGS, 361 RK3328_CLKGATE_CON(8), 1, GFLAGS), 362 COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", 0, 363 RK3328_CLKSEL_CON(1), 12, 3, DFLAGS, 364 RK3328_CLKGATE_CON(8), 2, GFLAGS), 365 GATE(0, "pclk_bus", "pclk_bus_pre", 0, 366 RK3328_CLKGATE_CON(8), 3, GFLAGS), 367 GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0, 368 RK3328_CLKGATE_CON(8), 4, GFLAGS), 369 370 COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0, 371 RK3328_CLKSEL_CON(21), 15, 1, MFLAGS, 8, 5, DFLAGS, 372 RK3328_CLKGATE_CON(2), 5, GFLAGS), 373 GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0, 374 RK3328_CLKGATE_CON(17), 13, GFLAGS), 375 376 /* PD_I2S */ 377 COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0, 378 RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, 379 RK3328_CLKGATE_CON(1), 1, GFLAGS), 380 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT, 381 RK3328_CLKSEL_CON(7), 0, 382 RK3328_CLKGATE_CON(1), 2, GFLAGS, 383 &rk3328_i2s0_fracmux), 384 GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, 385 RK3328_CLKGATE_CON(1), 3, GFLAGS), 386 387 COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0, 388 RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS, 389 RK3328_CLKGATE_CON(1), 4, GFLAGS), 390 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT, 391 RK3328_CLKSEL_CON(9), 0, 392 RK3328_CLKGATE_CON(1), 5, GFLAGS, 393 &rk3328_i2s1_fracmux), 394 GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 395 RK3328_CLKGATE_CON(1), 6, GFLAGS), 396 COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0, 397 RK3328_CLKSEL_CON(8), 12, 1, MFLAGS, 398 RK3328_CLKGATE_CON(1), 7, GFLAGS), 399 400 COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0, 401 RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS, 402 RK3328_CLKGATE_CON(1), 8, GFLAGS), 403 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT, 404 RK3328_CLKSEL_CON(11), 0, 405 RK3328_CLKGATE_CON(1), 9, GFLAGS, 406 &rk3328_i2s2_fracmux), 407 GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, 408 RK3328_CLKGATE_CON(1), 10, GFLAGS), 409 COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0, 410 RK3328_CLKSEL_CON(10), 12, 1, MFLAGS, 411 RK3328_CLKGATE_CON(1), 11, GFLAGS), 412 413 COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0, 414 RK3328_CLKSEL_CON(12), 15, 1, MFLAGS, 0, 7, DFLAGS, 415 RK3328_CLKGATE_CON(1), 12, GFLAGS), 416 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT, 417 RK3328_CLKSEL_CON(13), 0, 418 RK3328_CLKGATE_CON(1), 13, GFLAGS, 419 &rk3328_spdif_fracmux), 420 421 /* PD_UART */ 422 COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0, 423 RK3328_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 424 RK3328_CLKGATE_CON(1), 14, GFLAGS), 425 COMPOSITE(0, "clk_uart1_div", mux_2plls_u480m_p, 0, 426 RK3328_CLKSEL_CON(16), 12, 2, MFLAGS, 0, 7, DFLAGS, 427 RK3328_CLKGATE_CON(2), 0, GFLAGS), 428 COMPOSITE(0, "clk_uart2_div", mux_2plls_u480m_p, 0, 429 RK3328_CLKSEL_CON(18), 12, 2, MFLAGS, 0, 7, DFLAGS, 430 RK3328_CLKGATE_CON(2), 2, GFLAGS), 431 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT, 432 RK3328_CLKSEL_CON(15), 0, 433 RK3328_CLKGATE_CON(1), 15, GFLAGS, 434 &rk3328_uart0_fracmux), 435 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT, 436 RK3328_CLKSEL_CON(17), 0, 437 RK3328_CLKGATE_CON(2), 1, GFLAGS, 438 &rk3328_uart1_fracmux), 439 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT, 440 RK3328_CLKSEL_CON(19), 0, 441 RK3328_CLKGATE_CON(2), 3, GFLAGS, 442 &rk3328_uart2_fracmux), 443 444 /* 445 * Clock-Architecture Diagram 4 446 */ 447 448 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0, 449 RK3328_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 7, DFLAGS, 450 RK3328_CLKGATE_CON(2), 9, GFLAGS), 451 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0, 452 RK3328_CLKSEL_CON(34), 15, 1, MFLAGS, 8, 7, DFLAGS, 453 RK3328_CLKGATE_CON(2), 10, GFLAGS), 454 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_2plls_p, 0, 455 RK3328_CLKSEL_CON(35), 7, 1, MFLAGS, 0, 7, DFLAGS, 456 RK3328_CLKGATE_CON(2), 11, GFLAGS), 457 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_2plls_p, 0, 458 RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS, 459 RK3328_CLKGATE_CON(2), 12, GFLAGS), 460 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0, 461 RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS, 462 RK3328_CLKGATE_CON(2), 4, GFLAGS), 463 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0, 464 RK3328_CLKSEL_CON(22), 0, 10, DFLAGS, 465 RK3328_CLKGATE_CON(2), 6, GFLAGS), 466 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "clk_24m", 0, 467 RK3328_CLKSEL_CON(23), 0, 10, DFLAGS, 468 RK3328_CLKGATE_CON(2), 14, GFLAGS), 469 COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0, 470 RK3328_CLKSEL_CON(24), 7, 1, MFLAGS, 0, 7, DFLAGS, 471 RK3328_CLKGATE_CON(2), 7, GFLAGS), 472 COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0, 473 RK3328_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 7, DFLAGS, 474 RK3328_CLKGATE_CON(2), 8, GFLAGS), 475 COMPOSITE(SCLK_OTP, "clk_otp", mux_2plls_xin24m_p, 0, 476 RK3328_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 6, DFLAGS, 477 RK3328_CLKGATE_CON(3), 8, GFLAGS), 478 COMPOSITE(SCLK_EFUSE, "clk_efuse", mux_2plls_xin24m_p, 0, 479 RK3328_CLKSEL_CON(5), 14, 2, MFLAGS, 8, 5, DFLAGS, 480 RK3328_CLKGATE_CON(2), 13, GFLAGS), 481 COMPOSITE(SCLK_PDM, "clk_pdm", mux_cpll_gpll_apll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, 482 RK3328_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, 483 RK3328_CLKGATE_CON(2), 15, GFLAGS), 484 485 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, 486 RK3328_CLKGATE_CON(8), 5, GFLAGS), 487 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, 488 RK3328_CLKGATE_CON(8), 6, GFLAGS), 489 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, 490 RK3328_CLKGATE_CON(8), 7, GFLAGS), 491 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, 492 RK3328_CLKGATE_CON(8), 8, GFLAGS), 493 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, 494 RK3328_CLKGATE_CON(8), 9, GFLAGS), 495 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, 496 RK3328_CLKGATE_CON(8), 10, GFLAGS), 497 498 COMPOSITE(SCLK_WIFI, "clk_wifi", mux_2plls_u480m_p, 0, 499 RK3328_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 6, DFLAGS, 500 RK3328_CLKGATE_CON(0), 10, GFLAGS), 501 502 /* 503 * Clock-Architecture Diagram 5 504 */ 505 506 /* PD_VIDEO */ 507 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_4plls_p, 0, 508 RK3328_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS, 509 RK3328_CLKGATE_CON(6), 0, GFLAGS), 510 FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4, 511 RK3328_CLKGATE_CON(11), 0, GFLAGS), 512 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", CLK_SET_RATE_PARENT, 513 RK3328_CLKGATE_CON(24), 0, GFLAGS), 514 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT, 515 RK3328_CLKGATE_CON(24), 1, GFLAGS), 516 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0, 517 RK3328_CLKGATE_CON(24), 2, GFLAGS), 518 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0, 519 RK3328_CLKGATE_CON(24), 3, GFLAGS), 520 521 COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0, 522 RK3328_CLKSEL_CON(48), 14, 2, MFLAGS, 8, 5, DFLAGS, 523 RK3328_CLKGATE_CON(6), 1, GFLAGS), 524 525 COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_4plls_p, 0, 526 RK3328_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS, 527 RK3328_CLKGATE_CON(6), 2, GFLAGS), 528 529 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_4plls_p, 0, 530 RK3328_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS, 531 RK3328_CLKGATE_CON(6), 5, GFLAGS), 532 FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4, 533 RK3328_CLKGATE_CON(11), 8, GFLAGS), 534 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", CLK_SET_RATE_PARENT, 535 RK3328_CLKGATE_CON(23), 0, GFLAGS), 536 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT, 537 RK3328_CLKGATE_CON(23), 1, GFLAGS), 538 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0, 539 RK3328_CLKGATE_CON(23), 2, GFLAGS), 540 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0, 541 RK3328_CLKGATE_CON(23), 3, GFLAGS), 542 543 COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0, 544 RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS, 545 RK3328_CLKGATE_CON(6), 3, GFLAGS), 546 FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4, 547 RK3328_CLKGATE_CON(11), 4, GFLAGS), 548 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0, 549 RK3328_CLKGATE_CON(25), 0, GFLAGS), 550 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0, 551 RK3328_CLKGATE_CON(25), 1, GFLAGS), 552 GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0, 553 RK3328_CLKGATE_CON(25), 0, GFLAGS), 554 GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0, 555 RK3328_CLKGATE_CON(25), 1, GFLAGS), 556 GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0, 557 RK3328_CLKGATE_CON(25), 0, GFLAGS), 558 GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0, 559 RK3328_CLKGATE_CON(25), 1, GFLAGS), 560 GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED, 561 RK3328_CLKGATE_CON(25), 0, GFLAGS), 562 563 COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0, 564 RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS, 565 RK3328_CLKGATE_CON(6), 4, GFLAGS), 566 567 COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0, 568 RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS, 569 RK3328_CLKGATE_CON(6), 7, GFLAGS), 570 571 /* 572 * Clock-Architecture Diagram 6 573 */ 574 575 /* PD_VIO */ 576 COMPOSITE(ACLK_VIO_PRE, "aclk_vio_pre", mux_4plls_p, 0, 577 RK3328_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS, 578 RK3328_CLKGATE_CON(5), 2, GFLAGS), 579 DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0, 580 RK3328_CLKSEL_CON(37), 8, 5, DFLAGS), 581 582 COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0, 583 RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS, 584 RK3328_CLKGATE_CON(5), 0, GFLAGS), 585 COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0, 586 RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS, 587 RK3328_CLKGATE_CON(5), 1, GFLAGS), 588 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0, 589 RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS, 590 RK3328_CLKGATE_CON(5), 5, GFLAGS), 591 GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0, 592 RK3328_CLKGATE_CON(5), 4, GFLAGS), 593 594 COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0, 595 RK3328_CLKSEL_CON(42), 7, 1, MFLAGS, 596 RK3328_CLKGATE_CON(5), 3, GFLAGS), 597 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT, 598 RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS), 599 600 COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0, 601 RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS, 602 RK3328_CLKGATE_CON(5), 6, GFLAGS), 603 DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0, 604 RK3328_CLKSEL_CON(40), 3, 3, DFLAGS), 605 MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 606 RK3328_CLKSEL_CON(40), 1, 1, MFLAGS), 607 608 /* 609 * Clock-Architecture Diagram 7 610 */ 611 612 /* PD_PERI */ 613 GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, 614 RK3328_CLKGATE_CON(4), 0, GFLAGS), 615 GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, 616 RK3328_CLKGATE_CON(4), 1, GFLAGS), 617 GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, 618 RK3328_CLKGATE_CON(4), 2, GFLAGS), 619 COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, 0, 620 RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS), 621 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED, 622 RK3328_CLKSEL_CON(29), 0, 2, DFLAGS, 623 RK3328_CLKGATE_CON(10), 2, GFLAGS), 624 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED, 625 RK3328_CLKSEL_CON(29), 4, 3, DFLAGS, 626 RK3328_CLKGATE_CON(10), 1, GFLAGS), 627 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 628 RK3328_CLKGATE_CON(10), 0, GFLAGS), 629 630 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0, 631 RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS, 632 RK3328_CLKGATE_CON(4), 3, GFLAGS), 633 634 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_2plls_24m_u480m_p, 0, 635 RK3328_CLKSEL_CON(31), 8, 2, MFLAGS, 0, 8, DFLAGS, 636 RK3328_CLKGATE_CON(4), 4, GFLAGS), 637 638 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0, 639 RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS, 640 RK3328_CLKGATE_CON(4), 5, GFLAGS), 641 642 COMPOSITE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", mux_2plls_24m_u480m_p, 0, 643 RK3328_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS, 644 RK3328_CLKGATE_CON(4), 10, GFLAGS), 645 646 COMPOSITE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", mux_2plls_p, 0, 647 RK3328_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS, 648 RK3328_CLKGATE_CON(4), 9, GFLAGS), 649 650 MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_src_p, CLK_SET_RATE_PARENT, 651 RK3328_CLKSEL_CON(45), 8, 1, MFLAGS), 652 653 GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0, 654 RK3328_CLKGATE_CON(4), 7, GFLAGS), 655 656 COMPOSITE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0, 657 RK3328_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 10, DFLAGS, 658 RK3328_CLKGATE_CON(4), 8, GFLAGS), 659 660 /* 661 * Clock-Architecture Diagram 8 662 */ 663 664 /* PD_GMAC */ 665 COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0, 666 RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 667 RK3328_CLKGATE_CON(3), 2, GFLAGS), 668 COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0, 669 RK3328_CLKSEL_CON(25), 8, 3, DFLAGS, 670 RK3328_CLKGATE_CON(9), 0, GFLAGS), 671 672 COMPOSITE(SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_p, 0, 673 RK3328_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 5, DFLAGS, 674 RK3328_CLKGATE_CON(3), 1, GFLAGS), 675 GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0, 676 RK3328_CLKGATE_CON(9), 7, GFLAGS), 677 GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0, 678 RK3328_CLKGATE_CON(9), 4, GFLAGS), 679 GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0, 680 RK3328_CLKGATE_CON(9), 5, GFLAGS), 681 GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0, 682 RK3328_CLKGATE_CON(9), 6, GFLAGS), 683 COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0, 684 RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS, 685 RK3328_CLKGATE_CON(3), 5, GFLAGS), 686 MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT, 687 RK3328_GRF_MAC_CON1, 10, 1, MFLAGS), 688 MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT, 689 RK3328_GRF_SOC_CON4, 14, 1, MFLAGS), 690 691 COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0, 692 RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS, 693 RK3328_CLKGATE_CON(3), 0, GFLAGS), 694 GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0, 695 RK3328_CLKGATE_CON(9), 3, GFLAGS), 696 GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0, 697 RK3328_CLKGATE_CON(9), 1, GFLAGS), 698 COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0, 699 RK3328_CLKSEL_CON(26), 8, 2, DFLAGS, 700 RK3328_CLKGATE_CON(9), 2, GFLAGS), 701 MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT, 702 RK3328_GRF_MAC_CON2, 10, 1, MFLAGS), 703 704 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 705 706 /* 707 * Clock-Architecture Diagram 9 708 */ 709 710 /* PD_VOP */ 711 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS), 712 GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS), 713 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS), 714 GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS), 715 716 GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS), 717 GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS), 718 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS), 719 GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS), 720 721 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS), 722 GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS), 723 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS), 724 GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS), 725 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS), 726 GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS), 727 GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS), 728 GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS), 729 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS), 730 GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS), 731 GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS), 732 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS), 733 734 /* PD_PERI */ 735 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS), 736 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS), 737 738 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS), 739 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS), 740 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 2, GFLAGS), 741 GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 15, GFLAGS), 742 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS), 743 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS), 744 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS), 745 GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS), 746 GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS), 747 GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS), 748 749 /* PD_GMAC */ 750 GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS), 751 GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS), 752 GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS), 753 GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS), 754 GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS), 755 GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS), 756 757 /* PD_BUS */ 758 GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS), 759 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS), 760 GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS), 761 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS), 762 GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS), 763 764 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 2, GFLAGS), 765 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS), 766 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS), 767 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS), 768 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 6, GFLAGS), 769 GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS), 770 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS), 771 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS), 772 GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS), 773 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS), 774 775 GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS), 776 GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS), 777 GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS), 778 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS), 779 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS), 780 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS), 781 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS), 782 GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 3, GFLAGS), 783 GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS), 784 GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS), 785 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS), 786 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS), 787 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS), 788 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 9, GFLAGS), 789 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS), 790 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS), 791 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS), 792 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS), 793 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS), 794 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS), 795 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS), 796 GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS), 797 GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS), 798 GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS), 799 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS), 800 GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS), 801 802 GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS), 803 GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS), 804 GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS), 805 GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS), 806 GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS), 807 GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 5, GFLAGS), 808 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS), 809 GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS), 810 GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS), 811 812 /* PD_MMC */ 813 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", 814 RK3328_SDMMC_CON0, 1), 815 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", 816 RK3328_SDMMC_CON1, 0), 817 818 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", 819 RK3328_SDIO_CON0, 1), 820 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", 821 RK3328_SDIO_CON1, 0), 822 823 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", 824 RK3328_EMMC_CON0, 1), 825 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", 826 RK3328_EMMC_CON1, 0), 827 828 MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext", 829 RK3328_SDMMC_EXT_CON0, 1), 830 MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext", 831 RK3328_SDMMC_EXT_CON1, 0), 832 }; 833 834 static const char *const rk3328_critical_clocks[] __initconst = { 835 "aclk_bus", 836 "aclk_bus_niu", 837 "pclk_bus", 838 "pclk_bus_niu", 839 "hclk_bus", 840 "hclk_bus_niu", 841 "aclk_peri", 842 "hclk_peri", 843 "hclk_peri_niu", 844 "pclk_peri", 845 "pclk_peri_niu", 846 "pclk_dbg", 847 "aclk_core_niu", 848 "aclk_gic400", 849 "aclk_intmem", 850 "hclk_rom", 851 "pclk_grf", 852 "pclk_cru", 853 "pclk_sgrf", 854 "pclk_timer0", 855 "clk_timer0", 856 "pclk_ddr_msch", 857 "pclk_ddr_mon", 858 "pclk_ddr_grf", 859 "clk_ddrupctl", 860 "clk_ddrmsch", 861 "hclk_ahb1tom", 862 "clk_jtag", 863 "pclk_ddrphy", 864 "pclk_pmu", 865 "hclk_otg_pmu", 866 "aclk_rga_niu", 867 "pclk_vio_h2p", 868 "hclk_vio_h2p", 869 "aclk_vio_niu", 870 "hclk_vio_niu", 871 "aclk_vop_niu", 872 "hclk_vop_niu", 873 "aclk_gpu_niu", 874 "aclk_rkvdec_niu", 875 "hclk_rkvdec_niu", 876 "aclk_vpu_niu", 877 "hclk_vpu_niu", 878 "aclk_rkvenc_niu", 879 "hclk_rkvenc_niu", 880 "aclk_gmac_niu", 881 "pclk_gmac_niu", 882 "pclk_phy_niu", 883 }; 884 885 static void __init rk3328_clk_init(struct device_node *np) 886 { 887 struct rockchip_clk_provider *ctx; 888 void __iomem *reg_base; 889 890 reg_base = of_iomap(np, 0); 891 if (!reg_base) { 892 pr_err("%s: could not map cru region\n", __func__); 893 return; 894 } 895 896 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 897 if (IS_ERR(ctx)) { 898 pr_err("%s: rockchip clk init failed\n", __func__); 899 iounmap(reg_base); 900 return; 901 } 902 903 rockchip_clk_register_plls(ctx, rk3328_pll_clks, 904 ARRAY_SIZE(rk3328_pll_clks), 905 RK3328_GRF_SOC_STATUS0); 906 rockchip_clk_register_branches(ctx, rk3328_clk_branches, 907 ARRAY_SIZE(rk3328_clk_branches)); 908 rockchip_clk_protect_critical(rk3328_critical_clocks, 909 ARRAY_SIZE(rk3328_critical_clocks)); 910 911 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 912 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 913 &rk3328_cpuclk_data, rk3328_cpuclk_rates, 914 ARRAY_SIZE(rk3328_cpuclk_rates)); 915 916 rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0), 917 ROCKCHIP_SOFTRST_HIWORD_MASK); 918 919 rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL); 920 921 rockchip_clk_of_add_provider(np, ctx); 922 } 923 CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init); 924