1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/syscore_ops.h> 21 #include <dt-bindings/clock/rk3288-cru.h> 22 #include "clk.h" 23 24 #define RK3288_GRF_SOC_CON(x) (0x244 + x * 4) 25 #define RK3288_GRF_SOC_STATUS1 0x284 26 27 enum rk3288_plls { 28 apll, dpll, cpll, gpll, npll, 29 }; 30 31 static struct rockchip_pll_rate_table rk3288_pll_rates[] = { 32 RK3066_PLL_RATE(2208000000, 1, 92, 1), 33 RK3066_PLL_RATE(2184000000, 1, 91, 1), 34 RK3066_PLL_RATE(2160000000, 1, 90, 1), 35 RK3066_PLL_RATE(2136000000, 1, 89, 1), 36 RK3066_PLL_RATE(2112000000, 1, 88, 1), 37 RK3066_PLL_RATE(2088000000, 1, 87, 1), 38 RK3066_PLL_RATE(2064000000, 1, 86, 1), 39 RK3066_PLL_RATE(2040000000, 1, 85, 1), 40 RK3066_PLL_RATE(2016000000, 1, 84, 1), 41 RK3066_PLL_RATE(1992000000, 1, 83, 1), 42 RK3066_PLL_RATE(1968000000, 1, 82, 1), 43 RK3066_PLL_RATE(1944000000, 1, 81, 1), 44 RK3066_PLL_RATE(1920000000, 1, 80, 1), 45 RK3066_PLL_RATE(1896000000, 1, 79, 1), 46 RK3066_PLL_RATE(1872000000, 1, 78, 1), 47 RK3066_PLL_RATE(1848000000, 1, 77, 1), 48 RK3066_PLL_RATE(1824000000, 1, 76, 1), 49 RK3066_PLL_RATE(1800000000, 1, 75, 1), 50 RK3066_PLL_RATE(1776000000, 1, 74, 1), 51 RK3066_PLL_RATE(1752000000, 1, 73, 1), 52 RK3066_PLL_RATE(1728000000, 1, 72, 1), 53 RK3066_PLL_RATE(1704000000, 1, 71, 1), 54 RK3066_PLL_RATE(1680000000, 1, 70, 1), 55 RK3066_PLL_RATE(1656000000, 1, 69, 1), 56 RK3066_PLL_RATE(1632000000, 1, 68, 1), 57 RK3066_PLL_RATE(1608000000, 1, 67, 1), 58 RK3066_PLL_RATE(1560000000, 1, 65, 1), 59 RK3066_PLL_RATE(1512000000, 1, 63, 1), 60 RK3066_PLL_RATE(1488000000, 1, 62, 1), 61 RK3066_PLL_RATE(1464000000, 1, 61, 1), 62 RK3066_PLL_RATE(1440000000, 1, 60, 1), 63 RK3066_PLL_RATE(1416000000, 1, 59, 1), 64 RK3066_PLL_RATE(1392000000, 1, 58, 1), 65 RK3066_PLL_RATE(1368000000, 1, 57, 1), 66 RK3066_PLL_RATE(1344000000, 1, 56, 1), 67 RK3066_PLL_RATE(1320000000, 1, 55, 1), 68 RK3066_PLL_RATE(1296000000, 1, 54, 1), 69 RK3066_PLL_RATE(1272000000, 1, 53, 1), 70 RK3066_PLL_RATE(1248000000, 1, 52, 1), 71 RK3066_PLL_RATE(1224000000, 1, 51, 1), 72 RK3066_PLL_RATE(1200000000, 1, 50, 1), 73 RK3066_PLL_RATE(1188000000, 2, 99, 1), 74 RK3066_PLL_RATE(1176000000, 1, 49, 1), 75 RK3066_PLL_RATE(1128000000, 1, 47, 1), 76 RK3066_PLL_RATE(1104000000, 1, 46, 1), 77 RK3066_PLL_RATE(1008000000, 1, 84, 2), 78 RK3066_PLL_RATE( 912000000, 1, 76, 2), 79 RK3066_PLL_RATE( 891000000, 8, 594, 2), 80 RK3066_PLL_RATE( 888000000, 1, 74, 2), 81 RK3066_PLL_RATE( 816000000, 1, 68, 2), 82 RK3066_PLL_RATE( 798000000, 2, 133, 2), 83 RK3066_PLL_RATE( 792000000, 1, 66, 2), 84 RK3066_PLL_RATE( 768000000, 1, 64, 2), 85 RK3066_PLL_RATE( 742500000, 8, 495, 2), 86 RK3066_PLL_RATE( 696000000, 1, 58, 2), 87 RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1), 88 RK3066_PLL_RATE( 600000000, 1, 50, 2), 89 RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1), 90 RK3066_PLL_RATE( 552000000, 1, 46, 2), 91 RK3066_PLL_RATE( 504000000, 1, 84, 4), 92 RK3066_PLL_RATE( 500000000, 3, 125, 2), 93 RK3066_PLL_RATE( 456000000, 1, 76, 4), 94 RK3066_PLL_RATE( 428000000, 1, 107, 6), 95 RK3066_PLL_RATE( 408000000, 1, 68, 4), 96 RK3066_PLL_RATE( 400000000, 3, 100, 2), 97 RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1), 98 RK3066_PLL_RATE( 384000000, 2, 128, 4), 99 RK3066_PLL_RATE( 360000000, 1, 60, 4), 100 RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1), 101 RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1), 102 RK3066_PLL_RATE( 312000000, 1, 52, 4), 103 RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1), 104 RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1), 105 RK3066_PLL_RATE( 300000000, 1, 75, 6), 106 RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1), 107 RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1), 108 RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1), 109 RK3066_PLL_RATE( 273600000, 1, 114, 10), 110 RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1), 111 RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1), 112 RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1), 113 RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1), 114 RK3066_PLL_RATE( 252000000, 1, 84, 8), 115 RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1), 116 RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1), 117 RK3066_PLL_RATE( 238000000, 1, 119, 12), 118 RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1), 119 RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1), 120 RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1), 121 RK3066_PLL_RATE( 195428571, 1, 114, 14), 122 RK3066_PLL_RATE( 160000000, 1, 80, 12), 123 RK3066_PLL_RATE( 157500000, 1, 105, 16), 124 RK3066_PLL_RATE( 126000000, 1, 84, 16), 125 RK3066_PLL_RATE( 48000000, 1, 64, 32), 126 { /* sentinel */ }, 127 }; 128 129 #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf 130 #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 131 #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf 132 #define RK3288_DIV_ACLK_CORE_MP_SHIFT 4 133 #define RK3288_DIV_L2RAM_MASK 0x7 134 #define RK3288_DIV_L2RAM_SHIFT 0 135 #define RK3288_DIV_ATCLK_MASK 0x1f 136 #define RK3288_DIV_ATCLK_SHIFT 4 137 #define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f 138 #define RK3288_DIV_PCLK_DBGPRE_SHIFT 9 139 140 #define RK3288_CLKSEL0(_core_m0, _core_mp) \ 141 { \ 142 .reg = RK3288_CLKSEL_CON(0), \ 143 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \ 144 RK3288_DIV_ACLK_CORE_M0_SHIFT) | \ 145 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \ 146 RK3288_DIV_ACLK_CORE_MP_SHIFT), \ 147 } 148 #define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \ 149 { \ 150 .reg = RK3288_CLKSEL_CON(37), \ 151 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \ 152 RK3288_DIV_L2RAM_SHIFT) | \ 153 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \ 154 RK3288_DIV_ATCLK_SHIFT) | \ 155 HIWORD_UPDATE(_pclk_dbg_pre, \ 156 RK3288_DIV_PCLK_DBGPRE_MASK, \ 157 RK3288_DIV_PCLK_DBGPRE_SHIFT), \ 158 } 159 160 #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \ 161 { \ 162 .prate = _prate, \ 163 .divs = { \ 164 RK3288_CLKSEL0(_core_m0, _core_mp), \ 165 RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \ 166 }, \ 167 } 168 169 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = { 170 RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3), 171 RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3), 172 RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3), 173 RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3), 174 RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3), 175 RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3), 176 RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3), 177 RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3), 178 RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3), 179 RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3), 180 RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3), 181 RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3), 182 RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3), 183 RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3), 184 }; 185 186 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = { 187 .core_reg = RK3288_CLKSEL_CON(0), 188 .div_core_shift = 8, 189 .div_core_mask = 0x1f, 190 .mux_core_alt = 1, 191 .mux_core_main = 0, 192 .mux_core_shift = 15, 193 .mux_core_mask = 0x1, 194 }; 195 196 PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 197 PNAME(mux_armclk_p) = { "apll_core", "gpll_core" }; 198 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; 199 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; 200 201 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 202 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; 203 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; 204 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" }; 205 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" }; 206 207 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" }; 208 PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; 209 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" }; 210 PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" }; 211 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" }; 212 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 213 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 214 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 215 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" }; 216 PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" }; 217 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" }; 218 PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" }; 219 PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" }; 220 PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" }; 221 PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" }; 222 223 PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" }; 224 PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m", 225 "sclk_otgphy0_480m" }; 226 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" }; 227 PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" }; 228 229 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { 230 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0), 231 RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates), 232 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4), 233 RK3288_MODE_CON, 4, 5, 0, NULL), 234 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8), 235 RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), 236 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), 237 RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), 238 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), 239 RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), 240 }; 241 242 static struct clk_div_table div_hclk_cpu_t[] = { 243 { .val = 0, .div = 1 }, 244 { .val = 1, .div = 2 }, 245 { .val = 3, .div = 4 }, 246 { /* sentinel */}, 247 }; 248 249 #define MFLAGS CLK_MUX_HIWORD_MASK 250 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 251 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 252 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 253 254 static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata = 255 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, 256 RK3288_CLKSEL_CON(4), 8, 2, MFLAGS); 257 258 static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata = 259 MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT, 260 RK3288_CLKSEL_CON(5), 8, 2, MFLAGS); 261 262 static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata = 263 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT, 264 RK3288_CLKSEL_CON(40), 8, 2, MFLAGS); 265 266 static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata = 267 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 268 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS); 269 270 static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata = 271 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 272 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS); 273 274 static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata = 275 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 276 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS); 277 278 static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata = 279 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, 280 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS); 281 282 static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata = 283 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT, 284 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS); 285 286 static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 287 /* 288 * Clock-Architecture Diagram 1 289 */ 290 291 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 292 RK3288_CLKGATE_CON(0), 1, GFLAGS), 293 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 294 RK3288_CLKGATE_CON(0), 2, GFLAGS), 295 296 COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED, 297 RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 298 RK3288_CLKGATE_CON(12), 0, GFLAGS), 299 COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED, 300 RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 301 RK3288_CLKGATE_CON(12), 1, GFLAGS), 302 COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED, 303 RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 304 RK3288_CLKGATE_CON(12), 2, GFLAGS), 305 COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED, 306 RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 307 RK3288_CLKGATE_CON(12), 3, GFLAGS), 308 COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED, 309 RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 310 RK3288_CLKGATE_CON(12), 4, GFLAGS), 311 COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED, 312 RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 313 RK3288_CLKGATE_CON(12), 5, GFLAGS), 314 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED, 315 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 316 RK3288_CLKGATE_CON(12), 6, GFLAGS), 317 COMPOSITE_NOMUX(0, "atclk", "armclk", 0, 318 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 319 RK3288_CLKGATE_CON(12), 7, GFLAGS), 320 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED, 321 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 322 RK3288_CLKGATE_CON(12), 8, GFLAGS), 323 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0, 324 RK3288_CLKGATE_CON(12), 9, GFLAGS), 325 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED, 326 RK3288_CLKGATE_CON(12), 10, GFLAGS), 327 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0, 328 RK3288_CLKGATE_CON(12), 11, GFLAGS), 329 330 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 331 RK3288_CLKGATE_CON(0), 8, GFLAGS), 332 GATE(0, "gpll_ddr", "gpll", 0, 333 RK3288_CLKGATE_CON(0), 9, GFLAGS), 334 COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, 335 RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2, 336 DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 337 338 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, 339 RK3288_CLKGATE_CON(0), 10, GFLAGS), 340 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, 341 RK3288_CLKGATE_CON(0), 11, GFLAGS), 342 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED, 343 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS), 344 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT, 345 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS), 346 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, 347 RK3288_CLKGATE_CON(0), 3, GFLAGS), 348 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, 349 RK3288_CLKSEL_CON(1), 12, 3, DFLAGS, 350 RK3288_CLKGATE_CON(0), 5, GFLAGS), 351 COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, 352 RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t, 353 RK3288_CLKGATE_CON(0), 4, GFLAGS), 354 GATE(0, "c2c_host", "aclk_cpu_src", 0, 355 RK3288_CLKGATE_CON(13), 8, GFLAGS), 356 COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0, 357 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS, 358 RK3288_CLKGATE_CON(5), 4, GFLAGS), 359 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, 360 RK3288_CLKGATE_CON(0), 7, GFLAGS), 361 362 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 363 364 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0, 365 RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, 366 RK3288_CLKGATE_CON(4), 1, GFLAGS), 367 COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, 368 RK3288_CLKSEL_CON(8), 0, 369 RK3288_CLKGATE_CON(4), 2, GFLAGS, 370 &rk3288_i2s_fracmux), 371 COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0, 372 RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, 373 RK3288_CLKGATE_CON(4), 0, GFLAGS), 374 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT, 375 RK3288_CLKGATE_CON(4), 3, GFLAGS), 376 377 MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0, 378 RK3288_CLKSEL_CON(5), 15, 1, MFLAGS), 379 COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT, 380 RK3288_CLKSEL_CON(5), 0, 7, DFLAGS, 381 RK3288_CLKGATE_CON(4), 4, GFLAGS), 382 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT, 383 RK3288_CLKSEL_CON(9), 0, 384 RK3288_CLKGATE_CON(4), 5, GFLAGS, 385 &rk3288_spdif_fracmux), 386 GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT, 387 RK3288_CLKGATE_CON(4), 6, GFLAGS), 388 COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT, 389 RK3288_CLKSEL_CON(40), 0, 7, DFLAGS, 390 RK3288_CLKGATE_CON(4), 7, GFLAGS), 391 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT, 392 RK3288_CLKSEL_CON(41), 0, 393 RK3288_CLKGATE_CON(4), 8, GFLAGS, 394 &rk3288_spdif_8ch_fracmux), 395 GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT, 396 RK3288_CLKGATE_CON(4), 9, GFLAGS), 397 398 GATE(0, "sclk_acc_efuse", "xin24m", 0, 399 RK3288_CLKGATE_CON(0), 12, GFLAGS), 400 401 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, 402 RK3288_CLKGATE_CON(1), 0, GFLAGS), 403 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, 404 RK3288_CLKGATE_CON(1), 1, GFLAGS), 405 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, 406 RK3288_CLKGATE_CON(1), 2, GFLAGS), 407 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, 408 RK3288_CLKGATE_CON(1), 3, GFLAGS), 409 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, 410 RK3288_CLKGATE_CON(1), 4, GFLAGS), 411 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, 412 RK3288_CLKGATE_CON(1), 5, GFLAGS), 413 414 /* 415 * Clock-Architecture Diagram 2 416 */ 417 418 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0, 419 RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS, 420 RK3288_CLKGATE_CON(3), 9, GFLAGS), 421 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, 422 RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, 423 RK3288_CLKGATE_CON(3), 11, GFLAGS), 424 MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT, 425 RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS), 426 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0, 427 RK3288_CLKGATE_CON(9), 0, GFLAGS), 428 429 FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4, 430 RK3288_CLKGATE_CON(3), 10, GFLAGS), 431 432 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, 433 RK3288_CLKGATE_CON(9), 1, GFLAGS), 434 435 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 436 RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS, 437 RK3288_CLKGATE_CON(3), 0, GFLAGS), 438 DIV(0, "hclk_vio", "aclk_vio0", 0, 439 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS), 440 COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 441 RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, 442 RK3288_CLKGATE_CON(3), 2, GFLAGS), 443 444 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0, 445 RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS, 446 RK3288_CLKGATE_CON(3), 5, GFLAGS), 447 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0, 448 RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, 449 RK3288_CLKGATE_CON(3), 4, GFLAGS), 450 451 COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0, 452 RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, 453 RK3288_CLKGATE_CON(3), 1, GFLAGS), 454 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0, 455 RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS, 456 RK3288_CLKGATE_CON(3), 3, GFLAGS), 457 458 COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0, 459 RK3288_CLKSEL_CON(28), 15, 1, MFLAGS, 460 RK3288_CLKGATE_CON(3), 12, GFLAGS), 461 COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0, 462 RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS, 463 RK3288_CLKGATE_CON(3), 13, GFLAGS), 464 465 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0, 466 RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, 467 RK3288_CLKGATE_CON(3), 14, GFLAGS), 468 COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0, 469 RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, 470 RK3288_CLKGATE_CON(3), 15, GFLAGS), 471 472 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, 473 RK3288_CLKGATE_CON(5), 12, GFLAGS), 474 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, 475 RK3288_CLKGATE_CON(5), 11, GFLAGS), 476 477 COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0, 478 RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS, 479 RK3288_CLKGATE_CON(13), 13, GFLAGS), 480 DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0, 481 RK3288_CLKSEL_CON(40), 12, 2, DFLAGS), 482 483 COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0, 484 RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS, 485 RK3288_CLKGATE_CON(13), 14, GFLAGS), 486 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0, 487 RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS, 488 RK3288_CLKGATE_CON(13), 15, GFLAGS), 489 490 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0, 491 RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, 492 RK3288_CLKGATE_CON(3), 7, GFLAGS), 493 COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0, 494 RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS), 495 496 DIV(0, "pclk_pd_alive", "gpll", 0, 497 RK3288_CLKSEL_CON(33), 8, 5, DFLAGS), 498 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED, 499 RK3288_CLKSEL_CON(33), 0, 5, DFLAGS, 500 RK3288_CLKGATE_CON(5), 8, GFLAGS), 501 502 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0, 503 RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS, 504 RK3288_CLKGATE_CON(5), 7, GFLAGS), 505 506 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 507 RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, 508 RK3288_CLKGATE_CON(2), 0, GFLAGS), 509 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, 510 RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 511 RK3288_CLKGATE_CON(2), 3, GFLAGS), 512 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED, 513 RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 514 RK3288_CLKGATE_CON(2), 2, GFLAGS), 515 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED, 516 RK3288_CLKGATE_CON(2), 1, GFLAGS), 517 518 /* 519 * Clock-Architecture Diagram 3 520 */ 521 522 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0, 523 RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS, 524 RK3288_CLKGATE_CON(2), 9, GFLAGS), 525 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0, 526 RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS, 527 RK3288_CLKGATE_CON(2), 10, GFLAGS), 528 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0, 529 RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS, 530 RK3288_CLKGATE_CON(2), 11, GFLAGS), 531 532 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, 533 RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS, 534 RK3288_CLKGATE_CON(13), 0, GFLAGS), 535 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0, 536 RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS, 537 RK3288_CLKGATE_CON(13), 1, GFLAGS), 538 COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0, 539 RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS, 540 RK3288_CLKGATE_CON(13), 2, GFLAGS), 541 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, 542 RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS, 543 RK3288_CLKGATE_CON(13), 3, GFLAGS), 544 545 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0, 1), 546 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0), 547 548 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1), 549 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0), 550 551 MMC(SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1), 552 MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0), 553 554 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1), 555 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0), 556 557 COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0, 558 RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS, 559 RK3288_CLKGATE_CON(4), 11, GFLAGS), 560 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0, 561 RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, 562 RK3288_CLKGATE_CON(4), 10, GFLAGS), 563 564 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, 565 RK3288_CLKGATE_CON(13), 4, GFLAGS), 566 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, 567 RK3288_CLKGATE_CON(13), 5, GFLAGS), 568 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED, 569 RK3288_CLKGATE_CON(13), 6, GFLAGS), 570 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED, 571 RK3288_CLKGATE_CON(13), 7, GFLAGS), 572 573 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0, 574 RK3288_CLKSEL_CON(2), 0, 6, DFLAGS, 575 RK3288_CLKGATE_CON(2), 7, GFLAGS), 576 577 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, 578 RK3288_CLKSEL_CON(24), 8, 8, DFLAGS, 579 RK3288_CLKGATE_CON(2), 8, GFLAGS), 580 581 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0, 582 RK3288_CLKGATE_CON(5), 13, GFLAGS), 583 584 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0, 585 RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS, 586 RK3288_CLKGATE_CON(5), 5, GFLAGS), 587 COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0, 588 RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS, 589 RK3288_CLKGATE_CON(5), 6, GFLAGS), 590 591 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0, 592 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS, 593 RK3288_CLKGATE_CON(1), 8, GFLAGS), 594 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 595 RK3288_CLKSEL_CON(17), 0, 596 RK3288_CLKGATE_CON(1), 9, GFLAGS, 597 &rk3288_uart0_fracmux), 598 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0, 599 RK3288_CLKSEL_CON(13), 15, 1, MFLAGS), 600 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0, 601 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS, 602 RK3288_CLKGATE_CON(1), 10, GFLAGS), 603 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 604 RK3288_CLKSEL_CON(18), 0, 605 RK3288_CLKGATE_CON(1), 11, GFLAGS, 606 &rk3288_uart1_fracmux), 607 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0, 608 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS, 609 RK3288_CLKGATE_CON(1), 12, GFLAGS), 610 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 611 RK3288_CLKSEL_CON(19), 0, 612 RK3288_CLKGATE_CON(1), 13, GFLAGS, 613 &rk3288_uart2_fracmux), 614 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0, 615 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS, 616 RK3288_CLKGATE_CON(1), 14, GFLAGS), 617 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT, 618 RK3288_CLKSEL_CON(20), 0, 619 RK3288_CLKGATE_CON(1), 15, GFLAGS, 620 &rk3288_uart3_fracmux), 621 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0, 622 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS, 623 RK3288_CLKGATE_CON(2), 12, GFLAGS), 624 COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT, 625 RK3288_CLKSEL_CON(7), 0, 626 RK3288_CLKGATE_CON(2), 13, GFLAGS, 627 &rk3288_uart4_fracmux), 628 629 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0, 630 RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS, 631 RK3288_CLKGATE_CON(2), 5, GFLAGS), 632 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT, 633 RK3288_CLKSEL_CON(21), 4, 1, MFLAGS), 634 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0, 635 RK3288_CLKGATE_CON(5), 3, GFLAGS), 636 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0, 637 RK3288_CLKGATE_CON(5), 2, GFLAGS), 638 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0, 639 RK3288_CLKGATE_CON(5), 0, GFLAGS), 640 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0, 641 RK3288_CLKGATE_CON(5), 1, GFLAGS), 642 643 COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0, 644 RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, 645 RK3288_CLKGATE_CON(2), 6, GFLAGS), 646 MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0, 647 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS), 648 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", 649 RK3288_CLKSEL_CON(22), 7, IFLAGS), 650 651 GATE(0, "jtag", "ext_jtag", 0, 652 RK3288_CLKGATE_CON(4), 14, GFLAGS), 653 654 COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0, 655 RK3288_CLKSEL_CON(13), 11, 2, MFLAGS, 656 RK3288_CLKGATE_CON(5), 14, GFLAGS), 657 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0, 658 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS, 659 RK3288_CLKGATE_CON(3), 6, GFLAGS), 660 GATE(0, "hsicphy12m_xin12m", "xin12m", 0, 661 RK3288_CLKGATE_CON(13), 9, GFLAGS), 662 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0, 663 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS), 664 MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0, 665 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS), 666 667 /* 668 * Clock-Architecture Diagram 4 669 */ 670 671 /* aclk_cpu gates */ 672 GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS), 673 GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS), 674 GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS), 675 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS), 676 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS), 677 GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS), 678 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS), 679 GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS), 680 681 /* hclk_cpu gates */ 682 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS), 683 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS), 684 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS), 685 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS), 686 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS), 687 688 /* pclk_cpu gates */ 689 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS), 690 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS), 691 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS), 692 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS), 693 GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS), 694 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS), 695 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS), 696 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS), 697 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS), 698 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), 699 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), 700 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), 701 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS), 702 703 /* ddrctrl [DDR Controller PHY clock] gates */ 704 GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS), 705 GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS), 706 707 /* ddrphy gates */ 708 GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS), 709 GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS), 710 711 /* aclk_peri gates */ 712 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS), 713 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS), 714 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS), 715 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS), 716 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS), 717 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS), 718 719 /* hclk_peri gates */ 720 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS), 721 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS), 722 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS), 723 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS), 724 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS), 725 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS), 726 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS), 727 GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS), 728 GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS), 729 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS), 730 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS), 731 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS), 732 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS), 733 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS), 734 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS), 735 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS), 736 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS), 737 GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS), 738 739 /* pclk_peri gates */ 740 GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS), 741 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS), 742 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS), 743 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS), 744 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS), 745 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS), 746 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS), 747 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS), 748 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS), 749 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS), 750 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS), 751 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS), 752 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS), 753 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS), 754 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS), 755 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS), 756 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS), 757 758 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS), 759 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS), 760 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS), 761 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS), 762 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), 763 764 /* sclk_gpu gates */ 765 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS), 766 767 /* pclk_pd_alive gates */ 768 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS), 769 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS), 770 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS), 771 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS), 772 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS), 773 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS), 774 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS), 775 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS), 776 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS), 777 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS), 778 779 /* pclk_pd_pmu gates */ 780 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS), 781 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS), 782 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS), 783 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS), 784 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS), 785 786 /* hclk_vio gates */ 787 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS), 788 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS), 789 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS), 790 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS), 791 GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS), 792 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS), 793 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS), 794 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS), 795 GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS), 796 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS), 797 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS), 798 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS), 799 GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS), 800 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS), 801 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS), 802 GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS), 803 804 /* aclk_vio0 gates */ 805 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS), 806 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS), 807 GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS), 808 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS), 809 810 /* aclk_vio1 gates */ 811 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS), 812 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS), 813 GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS), 814 815 /* aclk_rga_pre gates */ 816 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS), 817 GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS), 818 819 /* 820 * Other ungrouped clocks. 821 */ 822 823 GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS), 824 INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS), 825 GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS), 826 INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS), 827 }; 828 829 static const char *const rk3288_critical_clocks[] __initconst = { 830 "aclk_cpu", 831 "aclk_peri", 832 "aclk_peri_niu", 833 "aclk_vio0_niu", 834 "aclk_vio1_niu", 835 "aclk_rga_niu", 836 "hclk_peri", 837 "hclk_vio_niu", 838 "pclk_alive_niu", 839 "pclk_pd_pmu", 840 "pclk_pmu_niu", 841 "pmu_hclk_otg0", 842 /* pwm-regulators on some boards, so handoff-critical later */ 843 "pclk_rkpwm", 844 }; 845 846 static void __iomem *rk3288_cru_base; 847 848 /* 849 * Some CRU registers will be reset in maskrom when the system 850 * wakes up from fastboot. 851 * So save them before suspend, restore them after resume. 852 */ 853 static const int rk3288_saved_cru_reg_ids[] = { 854 RK3288_MODE_CON, 855 RK3288_CLKSEL_CON(0), 856 RK3288_CLKSEL_CON(1), 857 RK3288_CLKSEL_CON(10), 858 RK3288_CLKSEL_CON(33), 859 RK3288_CLKSEL_CON(37), 860 861 /* We turn aclk_dmac1 on for suspend; this will restore it */ 862 RK3288_CLKGATE_CON(10), 863 }; 864 865 static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)]; 866 867 static int rk3288_clk_suspend(void) 868 { 869 int i, reg_id; 870 871 for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) { 872 reg_id = rk3288_saved_cru_reg_ids[i]; 873 874 rk3288_saved_cru_regs[i] = 875 readl_relaxed(rk3288_cru_base + reg_id); 876 } 877 878 /* 879 * Going into deep sleep (specifically setting PMU_CLR_DMA in 880 * RK3288_PMU_PWRMODE_CON1) appears to fail unless 881 * "aclk_dmac1" is on. 882 */ 883 writel_relaxed(1 << (12 + 16), 884 rk3288_cru_base + RK3288_CLKGATE_CON(10)); 885 886 /* 887 * Switch PLLs other than DPLL (for SDRAM) to slow mode to 888 * avoid crashes on resume. The Mask ROM on the system will 889 * put APLL, CPLL, and GPLL into slow mode at resume time 890 * anyway (which is why we restore them), but we might not 891 * even make it to the Mask ROM if this isn't done at suspend 892 * time. 893 * 894 * NOTE: only APLL truly matters here, but we'll do them all. 895 */ 896 897 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON); 898 899 return 0; 900 } 901 902 static void rk3288_clk_resume(void) 903 { 904 int i, reg_id; 905 906 for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) { 907 reg_id = rk3288_saved_cru_reg_ids[i]; 908 909 writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000, 910 rk3288_cru_base + reg_id); 911 } 912 } 913 914 static void rk3288_clk_shutdown(void) 915 { 916 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON); 917 } 918 919 static struct syscore_ops rk3288_clk_syscore_ops = { 920 .suspend = rk3288_clk_suspend, 921 .resume = rk3288_clk_resume, 922 }; 923 924 static void __init rk3288_clk_init(struct device_node *np) 925 { 926 struct rockchip_clk_provider *ctx; 927 struct clk *clk; 928 929 rk3288_cru_base = of_iomap(np, 0); 930 if (!rk3288_cru_base) { 931 pr_err("%s: could not map cru region\n", __func__); 932 return; 933 } 934 935 ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS); 936 if (IS_ERR(ctx)) { 937 pr_err("%s: rockchip clk init failed\n", __func__); 938 iounmap(rk3288_cru_base); 939 return; 940 } 941 942 /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ 943 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1); 944 if (IS_ERR(clk)) 945 pr_warn("%s: could not register clock pclk_wdt: %ld\n", 946 __func__, PTR_ERR(clk)); 947 else 948 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); 949 950 rockchip_clk_register_plls(ctx, rk3288_pll_clks, 951 ARRAY_SIZE(rk3288_pll_clks), 952 RK3288_GRF_SOC_STATUS1); 953 rockchip_clk_register_branches(ctx, rk3288_clk_branches, 954 ARRAY_SIZE(rk3288_clk_branches)); 955 rockchip_clk_protect_critical(rk3288_critical_clocks, 956 ARRAY_SIZE(rk3288_critical_clocks)); 957 958 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 959 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 960 &rk3288_cpuclk_data, rk3288_cpuclk_rates, 961 ARRAY_SIZE(rk3288_cpuclk_rates)); 962 963 rockchip_register_softrst(np, 12, 964 rk3288_cru_base + RK3288_SOFTRST_CON(0), 965 ROCKCHIP_SOFTRST_HIWORD_MASK); 966 967 rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST, 968 rk3288_clk_shutdown); 969 register_syscore_ops(&rk3288_clk_syscore_ops); 970 971 rockchip_clk_of_add_provider(np, ctx); 972 } 973 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init); 974