1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <dt-bindings/clock/rk3188-cru-common.h> 21 #include "clk.h" 22 23 #define RK3066_GRF_SOC_STATUS 0x15c 24 #define RK3188_GRF_SOC_STATUS 0xac 25 26 enum rk3188_plls { 27 apll, cpll, dpll, gpll, 28 }; 29 30 static struct rockchip_pll_rate_table rk3188_pll_rates[] = { 31 RK3066_PLL_RATE(2208000000, 1, 92, 1), 32 RK3066_PLL_RATE(2184000000, 1, 91, 1), 33 RK3066_PLL_RATE(2160000000, 1, 90, 1), 34 RK3066_PLL_RATE(2136000000, 1, 89, 1), 35 RK3066_PLL_RATE(2112000000, 1, 88, 1), 36 RK3066_PLL_RATE(2088000000, 1, 87, 1), 37 RK3066_PLL_RATE(2064000000, 1, 86, 1), 38 RK3066_PLL_RATE(2040000000, 1, 85, 1), 39 RK3066_PLL_RATE(2016000000, 1, 84, 1), 40 RK3066_PLL_RATE(1992000000, 1, 83, 1), 41 RK3066_PLL_RATE(1968000000, 1, 82, 1), 42 RK3066_PLL_RATE(1944000000, 1, 81, 1), 43 RK3066_PLL_RATE(1920000000, 1, 80, 1), 44 RK3066_PLL_RATE(1896000000, 1, 79, 1), 45 RK3066_PLL_RATE(1872000000, 1, 78, 1), 46 RK3066_PLL_RATE(1848000000, 1, 77, 1), 47 RK3066_PLL_RATE(1824000000, 1, 76, 1), 48 RK3066_PLL_RATE(1800000000, 1, 75, 1), 49 RK3066_PLL_RATE(1776000000, 1, 74, 1), 50 RK3066_PLL_RATE(1752000000, 1, 73, 1), 51 RK3066_PLL_RATE(1728000000, 1, 72, 1), 52 RK3066_PLL_RATE(1704000000, 1, 71, 1), 53 RK3066_PLL_RATE(1680000000, 1, 70, 1), 54 RK3066_PLL_RATE(1656000000, 1, 69, 1), 55 RK3066_PLL_RATE(1632000000, 1, 68, 1), 56 RK3066_PLL_RATE(1608000000, 1, 67, 1), 57 RK3066_PLL_RATE(1560000000, 1, 65, 1), 58 RK3066_PLL_RATE(1512000000, 1, 63, 1), 59 RK3066_PLL_RATE(1488000000, 1, 62, 1), 60 RK3066_PLL_RATE(1464000000, 1, 61, 1), 61 RK3066_PLL_RATE(1440000000, 1, 60, 1), 62 RK3066_PLL_RATE(1416000000, 1, 59, 1), 63 RK3066_PLL_RATE(1392000000, 1, 58, 1), 64 RK3066_PLL_RATE(1368000000, 1, 57, 1), 65 RK3066_PLL_RATE(1344000000, 1, 56, 1), 66 RK3066_PLL_RATE(1320000000, 1, 55, 1), 67 RK3066_PLL_RATE(1296000000, 1, 54, 1), 68 RK3066_PLL_RATE(1272000000, 1, 53, 1), 69 RK3066_PLL_RATE(1248000000, 1, 52, 1), 70 RK3066_PLL_RATE(1224000000, 1, 51, 1), 71 RK3066_PLL_RATE(1200000000, 1, 50, 1), 72 RK3066_PLL_RATE(1188000000, 2, 99, 1), 73 RK3066_PLL_RATE(1176000000, 1, 49, 1), 74 RK3066_PLL_RATE(1128000000, 1, 47, 1), 75 RK3066_PLL_RATE(1104000000, 1, 46, 1), 76 RK3066_PLL_RATE(1008000000, 1, 84, 2), 77 RK3066_PLL_RATE( 912000000, 1, 76, 2), 78 RK3066_PLL_RATE( 891000000, 8, 594, 2), 79 RK3066_PLL_RATE( 888000000, 1, 74, 2), 80 RK3066_PLL_RATE( 816000000, 1, 68, 2), 81 RK3066_PLL_RATE( 798000000, 2, 133, 2), 82 RK3066_PLL_RATE( 792000000, 1, 66, 2), 83 RK3066_PLL_RATE( 768000000, 1, 64, 2), 84 RK3066_PLL_RATE( 742500000, 8, 495, 2), 85 RK3066_PLL_RATE( 696000000, 1, 58, 2), 86 RK3066_PLL_RATE( 600000000, 1, 50, 2), 87 RK3066_PLL_RATE( 594000000, 2, 198, 4), 88 RK3066_PLL_RATE( 552000000, 1, 46, 2), 89 RK3066_PLL_RATE( 504000000, 1, 84, 4), 90 RK3066_PLL_RATE( 456000000, 1, 76, 4), 91 RK3066_PLL_RATE( 408000000, 1, 68, 4), 92 RK3066_PLL_RATE( 384000000, 2, 128, 4), 93 RK3066_PLL_RATE( 360000000, 1, 60, 4), 94 RK3066_PLL_RATE( 312000000, 1, 52, 4), 95 RK3066_PLL_RATE( 300000000, 1, 50, 4), 96 RK3066_PLL_RATE( 297000000, 2, 198, 8), 97 RK3066_PLL_RATE( 252000000, 1, 84, 8), 98 RK3066_PLL_RATE( 216000000, 1, 72, 8), 99 RK3066_PLL_RATE( 148500000, 2, 99, 8), 100 RK3066_PLL_RATE( 126000000, 1, 84, 16), 101 RK3066_PLL_RATE( 48000000, 1, 64, 32), 102 { /* sentinel */ }, 103 }; 104 105 #define RK3066_DIV_CORE_PERIPH_MASK 0x3 106 #define RK3066_DIV_CORE_PERIPH_SHIFT 6 107 #define RK3066_DIV_ACLK_CORE_MASK 0x7 108 #define RK3066_DIV_ACLK_CORE_SHIFT 0 109 #define RK3066_DIV_ACLK_HCLK_MASK 0x3 110 #define RK3066_DIV_ACLK_HCLK_SHIFT 8 111 #define RK3066_DIV_ACLK_PCLK_MASK 0x3 112 #define RK3066_DIV_ACLK_PCLK_SHIFT 12 113 #define RK3066_DIV_AHB2APB_MASK 0x3 114 #define RK3066_DIV_AHB2APB_SHIFT 14 115 116 #define RK3066_CLKSEL0(_core_peri) \ 117 { \ 118 .reg = RK2928_CLKSEL_CON(0), \ 119 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \ 120 RK3066_DIV_CORE_PERIPH_SHIFT) \ 121 } 122 #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \ 123 { \ 124 .reg = RK2928_CLKSEL_CON(1), \ 125 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \ 126 RK3066_DIV_ACLK_CORE_SHIFT) | \ 127 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \ 128 RK3066_DIV_ACLK_HCLK_SHIFT) | \ 129 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \ 130 RK3066_DIV_ACLK_PCLK_SHIFT) | \ 131 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \ 132 RK3066_DIV_AHB2APB_SHIFT), \ 133 } 134 135 #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \ 136 { \ 137 .prate = _prate, \ 138 .divs = { \ 139 RK3066_CLKSEL0(_core_peri), \ 140 RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \ 141 }, \ 142 } 143 144 static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = { 145 RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1), 146 RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1), 147 RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1), 148 RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1), 149 RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1), 150 RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1), 151 RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0), 152 }; 153 154 static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = { 155 .core_reg = RK2928_CLKSEL_CON(0), 156 .div_core_shift = 0, 157 .div_core_mask = 0x1f, 158 .mux_core_alt = 1, 159 .mux_core_main = 0, 160 .mux_core_shift = 8, 161 .mux_core_mask = 0x1, 162 }; 163 164 #define RK3188_DIV_ACLK_CORE_MASK 0x7 165 #define RK3188_DIV_ACLK_CORE_SHIFT 3 166 167 #define RK3188_CLKSEL1(_aclk_core) \ 168 { \ 169 .reg = RK2928_CLKSEL_CON(1), \ 170 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\ 171 RK3188_DIV_ACLK_CORE_SHIFT) \ 172 } 173 #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \ 174 { \ 175 .prate = _prate, \ 176 .divs = { \ 177 RK3066_CLKSEL0(_core_peri), \ 178 RK3188_CLKSEL1(_aclk_core), \ 179 }, \ 180 } 181 182 static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = { 183 RK3188_CPUCLK_RATE(1608000000, 2, 3), 184 RK3188_CPUCLK_RATE(1416000000, 2, 3), 185 RK3188_CPUCLK_RATE(1200000000, 2, 3), 186 RK3188_CPUCLK_RATE(1008000000, 2, 3), 187 RK3188_CPUCLK_RATE( 816000000, 2, 3), 188 RK3188_CPUCLK_RATE( 600000000, 1, 3), 189 RK3188_CPUCLK_RATE( 504000000, 1, 3), 190 RK3188_CPUCLK_RATE( 312000000, 0, 1), 191 }; 192 193 static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = { 194 .core_reg = RK2928_CLKSEL_CON(0), 195 .div_core_shift = 9, 196 .div_core_mask = 0x1f, 197 .mux_core_alt = 1, 198 .mux_core_main = 0, 199 .mux_core_shift = 8, 200 .mux_core_mask = 0x1, 201 }; 202 203 PNAME(mux_pll_p) = { "xin24m", "xin32k" }; 204 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; 205 PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" }; 206 PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" }; 207 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; 208 PNAME(mux_aclk_cpu_p) = { "apll", "gpll" }; 209 PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" }; 210 PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" }; 211 PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" }; 212 PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" }; 213 PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" }; 214 PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" }; 215 PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" }; 216 PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" }; 217 PNAME(mux_mac_p) = { "gpll", "dpll" }; 218 PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" }; 219 220 static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = { 221 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 222 RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates), 223 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 224 RK2928_MODE_CON, 4, 4, 0, NULL), 225 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), 226 RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), 227 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), 228 RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), 229 }; 230 231 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { 232 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 233 RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates), 234 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 235 RK2928_MODE_CON, 4, 5, 0, NULL), 236 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), 237 RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), 238 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), 239 RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), 240 }; 241 242 #define MFLAGS CLK_MUX_HIWORD_MASK 243 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 244 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 245 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 246 247 /* 2 ^ (val + 1) */ 248 static struct clk_div_table div_core_peri_t[] = { 249 { .val = 0, .div = 2 }, 250 { .val = 1, .div = 4 }, 251 { .val = 2, .div = 8 }, 252 { .val = 3, .div = 16 }, 253 { /* sentinel */ }, 254 }; 255 256 static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata = 257 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0, 258 RK2928_CLKSEL_CON(22), 4, 2, MFLAGS); 259 260 static struct rockchip_clk_branch common_spdif_fracmux __initdata = 261 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, 262 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); 263 264 static struct rockchip_clk_branch common_uart0_fracmux __initdata = 265 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, 266 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); 267 268 static struct rockchip_clk_branch common_uart1_fracmux __initdata = 269 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, 270 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); 271 272 static struct rockchip_clk_branch common_uart2_fracmux __initdata = 273 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, 274 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); 275 276 static struct rockchip_clk_branch common_uart3_fracmux __initdata = 277 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, 278 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); 279 280 static struct rockchip_clk_branch common_clk_branches[] __initdata = { 281 /* 282 * Clock-Architecture Diagram 2 283 */ 284 285 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), 286 287 /* these two are set by the cpuclk and should not be changed */ 288 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0, 289 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, 290 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS), 291 292 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, 293 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS, 294 RK2928_CLKGATE_CON(3), 9, GFLAGS), 295 GATE(0, "hclk_vepu", "aclk_vepu", 0, 296 RK2928_CLKGATE_CON(3), 10, GFLAGS), 297 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, 298 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, 299 RK2928_CLKGATE_CON(3), 11, GFLAGS), 300 GATE(0, "hclk_vdpu", "aclk_vdpu", 0, 301 RK2928_CLKGATE_CON(3), 12, GFLAGS), 302 303 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 304 RK2928_CLKGATE_CON(1), 7, GFLAGS), 305 COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, 306 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 307 RK2928_CLKGATE_CON(0), 2, GFLAGS), 308 309 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, 310 RK2928_CLKGATE_CON(0), 3, GFLAGS), 311 312 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, 313 RK2928_CLKGATE_CON(0), 6, GFLAGS), 314 GATE(0, "pclk_cpu", "pclk_cpu_pre", 0, 315 RK2928_CLKGATE_CON(0), 5, GFLAGS), 316 GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, 317 RK2928_CLKGATE_CON(0), 4, GFLAGS), 318 319 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, 320 RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS, 321 RK2928_CLKGATE_CON(3), 0, GFLAGS), 322 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0, 323 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, 324 RK2928_CLKGATE_CON(1), 4, GFLAGS), 325 326 GATE(0, "aclk_peri", "aclk_peri_pre", 0, 327 RK2928_CLKGATE_CON(2), 1, GFLAGS), 328 COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0, 329 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 330 RK2928_CLKGATE_CON(2), 2, GFLAGS), 331 COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, 332 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 333 RK2928_CLKGATE_CON(2), 3, GFLAGS), 334 335 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0, 336 RK2928_CLKSEL_CON(29), 0, 1, MFLAGS), 337 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0, 338 RK2928_CLKSEL_CON(29), 1, 5, DFLAGS, 339 RK2928_CLKGATE_CON(3), 7, GFLAGS), 340 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0, 341 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS), 342 343 GATE(0, "pclkin_cif0", "ext_cif0", 0, 344 RK2928_CLKGATE_CON(3), 3, GFLAGS), 345 INVERTER(0, "pclk_cif0", "pclkin_cif0", 346 RK2928_CLKSEL_CON(30), 8, IFLAGS), 347 348 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 349 350 /* 351 * the 480m are generated inside the usb block from these clocks, 352 * but they are also a source for the hsicphy clock. 353 */ 354 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED, 355 RK2928_CLKGATE_CON(1), 5, GFLAGS), 356 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED, 357 RK2928_CLKGATE_CON(1), 6, GFLAGS), 358 359 COMPOSITE(0, "mac_src", mux_mac_p, 0, 360 RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS, 361 RK2928_CLKGATE_CON(2), 5, GFLAGS), 362 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, 363 RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), 364 GATE(0, "sclk_mac_lbtest", "sclk_macref", 365 RK2928_CLKGATE_CON(2), 12, 0, GFLAGS), 366 367 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, 368 RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, 369 RK2928_CLKGATE_CON(2), 6, GFLAGS), 370 COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0, 371 RK2928_CLKSEL_CON(23), 0, 372 RK2928_CLKGATE_CON(2), 7, GFLAGS, 373 &common_hsadc_out_fracmux), 374 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", 375 RK2928_CLKSEL_CON(22), 7, IFLAGS), 376 377 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, 378 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, 379 RK2928_CLKGATE_CON(2), 8, GFLAGS), 380 381 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, 382 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, 383 RK2928_CLKGATE_CON(0), 13, GFLAGS), 384 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pll", CLK_SET_RATE_PARENT, 385 RK2928_CLKSEL_CON(9), 0, 386 RK2928_CLKGATE_CON(0), 14, GFLAGS, 387 &common_spdif_fracmux), 388 389 /* 390 * Clock-Architecture Diagram 4 391 */ 392 393 GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 394 RK2928_CLKGATE_CON(2), 4, 0, GFLAGS), 395 396 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0, 397 RK2928_CLKSEL_CON(25), 0, 7, DFLAGS, 398 RK2928_CLKGATE_CON(2), 9, GFLAGS), 399 COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0, 400 RK2928_CLKSEL_CON(25), 8, 7, DFLAGS, 401 RK2928_CLKGATE_CON(2), 10, GFLAGS), 402 403 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0, 404 RK2928_CLKSEL_CON(11), 0, 6, DFLAGS, 405 RK2928_CLKGATE_CON(2), 11, GFLAGS), 406 COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0, 407 RK2928_CLKSEL_CON(12), 0, 6, DFLAGS, 408 RK2928_CLKGATE_CON(2), 13, GFLAGS), 409 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0, 410 RK2928_CLKSEL_CON(12), 8, 6, DFLAGS, 411 RK2928_CLKGATE_CON(2), 14, GFLAGS), 412 413 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0, 414 RK2928_CLKSEL_CON(12), 15, 1, MFLAGS), 415 COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0, 416 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, 417 RK2928_CLKGATE_CON(1), 8, GFLAGS), 418 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0, 419 RK2928_CLKSEL_CON(17), 0, 420 RK2928_CLKGATE_CON(1), 9, GFLAGS, 421 &common_uart0_fracmux), 422 COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, 423 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, 424 RK2928_CLKGATE_CON(1), 10, GFLAGS), 425 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0, 426 RK2928_CLKSEL_CON(18), 0, 427 RK2928_CLKGATE_CON(1), 11, GFLAGS, 428 &common_uart1_fracmux), 429 COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, 430 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, 431 RK2928_CLKGATE_CON(1), 12, GFLAGS), 432 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0, 433 RK2928_CLKSEL_CON(19), 0, 434 RK2928_CLKGATE_CON(1), 13, GFLAGS, 435 &common_uart2_fracmux), 436 COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, 437 RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, 438 RK2928_CLKGATE_CON(1), 14, GFLAGS), 439 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0, 440 RK2928_CLKSEL_CON(20), 0, 441 RK2928_CLKGATE_CON(1), 15, GFLAGS, 442 &common_uart3_fracmux), 443 444 GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS), 445 446 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS), 447 GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS), 448 449 /* clk_core_pre gates */ 450 GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), 451 452 /* aclk_cpu gates */ 453 GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS), 454 GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), 455 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), 456 457 /* hclk_cpu gates */ 458 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), 459 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), 460 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), 461 GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), 462 /* hclk_ahb2apb is part of a clk branch */ 463 GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS), 464 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS), 465 GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS), 466 GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS), 467 GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS), 468 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS), 469 470 /* hclk_peri gates */ 471 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), 472 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS), 473 GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS), 474 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), 475 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), 476 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS), 477 GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), 478 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS), 479 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS), 480 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), 481 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), 482 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS), 483 484 /* aclk_lcdc0_pre gates */ 485 GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS), 486 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS), 487 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS), 488 GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS), 489 490 /* aclk_lcdc1_pre gates */ 491 GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), 492 GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS), 493 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS), 494 495 /* atclk_cpu gates */ 496 GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS), 497 GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), 498 499 /* pclk_cpu gates */ 500 GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), 501 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), 502 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), 503 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), 504 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), 505 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), 506 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), 507 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), 508 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS), 509 GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), 510 GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), 511 GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), 512 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), 513 GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS), 514 515 /* aclk_peri */ 516 GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), 517 GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS), 518 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS), 519 GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), 520 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), 521 522 /* pclk_peri gates */ 523 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), 524 GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS), 525 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), 526 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), 527 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS), 528 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), 529 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), 530 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), 531 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), 532 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), 533 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), 534 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS), 535 }; 536 537 PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" }; 538 PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" }; 539 PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" }; 540 PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" }; 541 PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" }; 542 543 static struct clk_div_table div_aclk_cpu_t[] = { 544 { .val = 0, .div = 1 }, 545 { .val = 1, .div = 2 }, 546 { .val = 2, .div = 3 }, 547 { .val = 3, .div = 4 }, 548 { .val = 4, .div = 8 }, 549 { /* sentinel */ }, 550 }; 551 552 static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata = 553 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, 554 RK2928_CLKSEL_CON(2), 8, 2, MFLAGS); 555 556 static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata = 557 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0, 558 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); 559 560 static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata = 561 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0, 562 RK2928_CLKSEL_CON(4), 8, 2, MFLAGS); 563 564 static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { 565 DIVTBL(0, "aclk_cpu_pre", "armclk", 0, 566 RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t), 567 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, 568 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 569 | CLK_DIVIDER_READ_ONLY), 570 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, 571 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 572 | CLK_DIVIDER_READ_ONLY), 573 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, 574 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO 575 | CLK_DIVIDER_READ_ONLY, 576 RK2928_CLKGATE_CON(4), 9, GFLAGS), 577 578 GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED, 579 RK2928_CLKGATE_CON(9), 4, GFLAGS), 580 581 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0, 582 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, 583 RK2928_CLKGATE_CON(2), 0, GFLAGS), 584 585 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0, 586 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, 587 RK2928_CLKGATE_CON(3), 1, GFLAGS), 588 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0, 589 RK2928_CLKSEL_CON(27), 4, 1, MFLAGS), 590 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0, 591 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, 592 RK2928_CLKGATE_CON(3), 2, GFLAGS), 593 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0, 594 RK2928_CLKSEL_CON(28), 4, 1, MFLAGS), 595 596 COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0, 597 RK2928_CLKSEL_CON(29), 8, 5, DFLAGS, 598 RK2928_CLKGATE_CON(3), 8, GFLAGS), 599 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0, 600 RK2928_CLKSEL_CON(29), 15, 1, MFLAGS), 601 602 GATE(0, "pclkin_cif1", "ext_cif1", 0, 603 RK2928_CLKGATE_CON(3), 4, GFLAGS), 604 INVERTER(0, "pclk_cif1", "pclkin_cif1", 605 RK2928_CLKSEL_CON(30), 12, IFLAGS), 606 607 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, 608 RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS, 609 RK2928_CLKGATE_CON(3), 13, GFLAGS), 610 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, 611 RK2928_CLKGATE_CON(5), 15, GFLAGS), 612 613 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, 614 RK2928_CLKGATE_CON(3), 2, GFLAGS), 615 616 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, 617 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS, 618 RK2928_CLKGATE_CON(2), 15, GFLAGS), 619 620 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, 621 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), 622 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, 623 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, 624 RK2928_CLKGATE_CON(0), 7, GFLAGS), 625 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0, 626 RK2928_CLKSEL_CON(6), 0, 627 RK2928_CLKGATE_CON(0), 8, GFLAGS, 628 &rk3066a_i2s0_fracmux), 629 COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, 630 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, 631 RK2928_CLKGATE_CON(0), 9, GFLAGS), 632 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0, 633 RK2928_CLKSEL_CON(7), 0, 634 RK2928_CLKGATE_CON(0), 10, GFLAGS, 635 &rk3066a_i2s1_fracmux), 636 COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, 637 RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, 638 RK2928_CLKGATE_CON(0), 11, GFLAGS), 639 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0, 640 RK2928_CLKSEL_CON(8), 0, 641 RK2928_CLKGATE_CON(0), 12, GFLAGS, 642 &rk3066a_i2s2_fracmux), 643 644 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), 645 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 646 GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), 647 GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), 648 649 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, 650 RK2928_CLKGATE_CON(5), 14, GFLAGS), 651 652 GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), 653 654 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), 655 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), 656 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), 657 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 658 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), 659 660 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), 661 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS), 662 }; 663 664 static struct clk_div_table div_rk3188_aclk_core_t[] = { 665 { .val = 0, .div = 1 }, 666 { .val = 1, .div = 2 }, 667 { .val = 2, .div = 3 }, 668 { .val = 3, .div = 4 }, 669 { .val = 4, .div = 8 }, 670 { /* sentinel */ }, 671 }; 672 673 PNAME(mux_hsicphy_p) = { "sclk_otgphy0_480m", "sclk_otgphy1_480m", 674 "gpll", "cpll" }; 675 676 static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata = 677 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, 678 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); 679 680 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { 681 COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, 682 RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 683 div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS), 684 685 /* do not source aclk_cpu_pre from the apll, to keep complexity down */ 686 COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT, 687 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS), 688 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, 689 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 690 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, 691 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 692 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, 693 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 694 RK2928_CLKGATE_CON(4), 9, GFLAGS), 695 696 GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED, 697 RK2928_CLKGATE_CON(9), 4, GFLAGS), 698 699 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0, 700 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, 701 RK2928_CLKGATE_CON(2), 0, GFLAGS), 702 703 COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0, 704 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, 705 RK2928_CLKGATE_CON(3), 1, GFLAGS), 706 COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0, 707 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, 708 RK2928_CLKGATE_CON(3), 2, GFLAGS), 709 710 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, 711 RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS, 712 RK2928_CLKGATE_CON(3), 15, GFLAGS), 713 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, 714 RK2928_CLKGATE_CON(9), 7, GFLAGS), 715 716 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), 717 GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS), 718 GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), 719 GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), 720 GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), 721 722 COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0, 723 RK2928_CLKSEL_CON(30), 0, 2, DFLAGS, 724 RK2928_CLKGATE_CON(3), 6, GFLAGS), 725 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0, 726 RK2928_CLKSEL_CON(11), 8, 6, DFLAGS), 727 728 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, 729 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), 730 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, 731 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, 732 RK2928_CLKGATE_CON(0), 9, GFLAGS), 733 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, 734 RK2928_CLKSEL_CON(7), 0, 735 RK2928_CLKGATE_CON(0), 10, GFLAGS, 736 &rk3188_i2s0_fracmux), 737 738 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), 739 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), 740 741 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, 742 RK2928_CLKGATE_CON(7), 3, GFLAGS), 743 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 744 745 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), 746 747 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 748 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), 749 750 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), 751 }; 752 753 static const char *const rk3188_critical_clocks[] __initconst = { 754 "aclk_cpu", 755 "aclk_peri", 756 "hclk_peri", 757 "pclk_cpu", 758 "pclk_peri", 759 "hclk_cpubus" 760 }; 761 762 static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np) 763 { 764 struct rockchip_clk_provider *ctx; 765 void __iomem *reg_base; 766 767 reg_base = of_iomap(np, 0); 768 if (!reg_base) { 769 pr_err("%s: could not map cru region\n", __func__); 770 return ERR_PTR(-ENOMEM); 771 } 772 773 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 774 if (IS_ERR(ctx)) { 775 pr_err("%s: rockchip clk init failed\n", __func__); 776 iounmap(reg_base); 777 return ERR_PTR(-ENOMEM); 778 } 779 780 rockchip_clk_register_branches(ctx, common_clk_branches, 781 ARRAY_SIZE(common_clk_branches)); 782 783 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), 784 ROCKCHIP_SOFTRST_HIWORD_MASK); 785 786 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); 787 788 return ctx; 789 } 790 791 static void __init rk3066a_clk_init(struct device_node *np) 792 { 793 struct rockchip_clk_provider *ctx; 794 795 ctx = rk3188_common_clk_init(np); 796 if (IS_ERR(ctx)) 797 return; 798 799 rockchip_clk_register_plls(ctx, rk3066_pll_clks, 800 ARRAY_SIZE(rk3066_pll_clks), 801 RK3066_GRF_SOC_STATUS); 802 rockchip_clk_register_branches(ctx, rk3066a_clk_branches, 803 ARRAY_SIZE(rk3066a_clk_branches)); 804 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 805 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 806 &rk3066_cpuclk_data, rk3066_cpuclk_rates, 807 ARRAY_SIZE(rk3066_cpuclk_rates)); 808 rockchip_clk_protect_critical(rk3188_critical_clocks, 809 ARRAY_SIZE(rk3188_critical_clocks)); 810 rockchip_clk_of_add_provider(np, ctx); 811 } 812 CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); 813 814 static void __init rk3188a_clk_init(struct device_node *np) 815 { 816 struct rockchip_clk_provider *ctx; 817 struct clk *clk1, *clk2; 818 unsigned long rate; 819 int ret; 820 821 ctx = rk3188_common_clk_init(np); 822 if (IS_ERR(ctx)) 823 return; 824 825 rockchip_clk_register_plls(ctx, rk3188_pll_clks, 826 ARRAY_SIZE(rk3188_pll_clks), 827 RK3188_GRF_SOC_STATUS); 828 rockchip_clk_register_branches(ctx, rk3188_clk_branches, 829 ARRAY_SIZE(rk3188_clk_branches)); 830 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 831 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 832 &rk3188_cpuclk_data, rk3188_cpuclk_rates, 833 ARRAY_SIZE(rk3188_cpuclk_rates)); 834 835 /* reparent aclk_cpu_pre from apll */ 836 clk1 = __clk_lookup("aclk_cpu_pre"); 837 clk2 = __clk_lookup("gpll"); 838 if (clk1 && clk2) { 839 rate = clk_get_rate(clk1); 840 841 ret = clk_set_parent(clk1, clk2); 842 if (ret < 0) 843 pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n", 844 __func__); 845 846 clk_set_rate(clk1, rate); 847 } else { 848 pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n", 849 __func__); 850 } 851 852 rockchip_clk_protect_critical(rk3188_critical_clocks, 853 ARRAY_SIZE(rk3188_critical_clocks)); 854 rockchip_clk_of_add_provider(np, ctx); 855 } 856 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init); 857 858 static void __init rk3188_clk_init(struct device_node *np) 859 { 860 int i; 861 862 for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) { 863 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i]; 864 struct rockchip_pll_rate_table *rate; 865 866 if (!pll->rate_table) 867 continue; 868 869 rate = pll->rate_table; 870 while (rate->rate > 0) { 871 rate->nb = 1; 872 rate++; 873 } 874 } 875 876 rk3188a_clk_init(np); 877 } 878 CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init); 879