1 /*
2  * Copyright (c) 2014 MundoReader S.L.
3  * Author: Heiko Stuebner <heiko@sntech.de>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <dt-bindings/clock/rk3188-cru-common.h>
21 #include "clk.h"
22 
23 #define RK3066_GRF_SOC_STATUS	0x15c
24 #define RK3188_GRF_SOC_STATUS	0xac
25 
26 enum rk3188_plls {
27 	apll, cpll, dpll, gpll,
28 };
29 
30 static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
31 	RK3066_PLL_RATE(2208000000, 1, 92, 1),
32 	RK3066_PLL_RATE(2184000000, 1, 91, 1),
33 	RK3066_PLL_RATE(2160000000, 1, 90, 1),
34 	RK3066_PLL_RATE(2136000000, 1, 89, 1),
35 	RK3066_PLL_RATE(2112000000, 1, 88, 1),
36 	RK3066_PLL_RATE(2088000000, 1, 87, 1),
37 	RK3066_PLL_RATE(2064000000, 1, 86, 1),
38 	RK3066_PLL_RATE(2040000000, 1, 85, 1),
39 	RK3066_PLL_RATE(2016000000, 1, 84, 1),
40 	RK3066_PLL_RATE(1992000000, 1, 83, 1),
41 	RK3066_PLL_RATE(1968000000, 1, 82, 1),
42 	RK3066_PLL_RATE(1944000000, 1, 81, 1),
43 	RK3066_PLL_RATE(1920000000, 1, 80, 1),
44 	RK3066_PLL_RATE(1896000000, 1, 79, 1),
45 	RK3066_PLL_RATE(1872000000, 1, 78, 1),
46 	RK3066_PLL_RATE(1848000000, 1, 77, 1),
47 	RK3066_PLL_RATE(1824000000, 1, 76, 1),
48 	RK3066_PLL_RATE(1800000000, 1, 75, 1),
49 	RK3066_PLL_RATE(1776000000, 1, 74, 1),
50 	RK3066_PLL_RATE(1752000000, 1, 73, 1),
51 	RK3066_PLL_RATE(1728000000, 1, 72, 1),
52 	RK3066_PLL_RATE(1704000000, 1, 71, 1),
53 	RK3066_PLL_RATE(1680000000, 1, 70, 1),
54 	RK3066_PLL_RATE(1656000000, 1, 69, 1),
55 	RK3066_PLL_RATE(1632000000, 1, 68, 1),
56 	RK3066_PLL_RATE(1608000000, 1, 67, 1),
57 	RK3066_PLL_RATE(1560000000, 1, 65, 1),
58 	RK3066_PLL_RATE(1512000000, 1, 63, 1),
59 	RK3066_PLL_RATE(1488000000, 1, 62, 1),
60 	RK3066_PLL_RATE(1464000000, 1, 61, 1),
61 	RK3066_PLL_RATE(1440000000, 1, 60, 1),
62 	RK3066_PLL_RATE(1416000000, 1, 59, 1),
63 	RK3066_PLL_RATE(1392000000, 1, 58, 1),
64 	RK3066_PLL_RATE(1368000000, 1, 57, 1),
65 	RK3066_PLL_RATE(1344000000, 1, 56, 1),
66 	RK3066_PLL_RATE(1320000000, 1, 55, 1),
67 	RK3066_PLL_RATE(1296000000, 1, 54, 1),
68 	RK3066_PLL_RATE(1272000000, 1, 53, 1),
69 	RK3066_PLL_RATE(1248000000, 1, 52, 1),
70 	RK3066_PLL_RATE(1224000000, 1, 51, 1),
71 	RK3066_PLL_RATE(1200000000, 1, 50, 1),
72 	RK3066_PLL_RATE(1188000000, 2, 99, 1),
73 	RK3066_PLL_RATE(1176000000, 1, 49, 1),
74 	RK3066_PLL_RATE(1128000000, 1, 47, 1),
75 	RK3066_PLL_RATE(1104000000, 1, 46, 1),
76 	RK3066_PLL_RATE(1008000000, 1, 84, 2),
77 	RK3066_PLL_RATE( 912000000, 1, 76, 2),
78 	RK3066_PLL_RATE( 891000000, 8, 594, 2),
79 	RK3066_PLL_RATE( 888000000, 1, 74, 2),
80 	RK3066_PLL_RATE( 816000000, 1, 68, 2),
81 	RK3066_PLL_RATE( 798000000, 2, 133, 2),
82 	RK3066_PLL_RATE( 792000000, 1, 66, 2),
83 	RK3066_PLL_RATE( 768000000, 1, 64, 2),
84 	RK3066_PLL_RATE( 742500000, 8, 495, 2),
85 	RK3066_PLL_RATE( 696000000, 1, 58, 2),
86 	RK3066_PLL_RATE( 600000000, 1, 50, 2),
87 	RK3066_PLL_RATE( 594000000, 2, 198, 4),
88 	RK3066_PLL_RATE( 552000000, 1, 46, 2),
89 	RK3066_PLL_RATE( 504000000, 1, 84, 4),
90 	RK3066_PLL_RATE( 456000000, 1, 76, 4),
91 	RK3066_PLL_RATE( 408000000, 1, 68, 4),
92 	RK3066_PLL_RATE( 400000000, 3, 100, 2),
93 	RK3066_PLL_RATE( 384000000, 2, 128, 4),
94 	RK3066_PLL_RATE( 360000000, 1, 60, 4),
95 	RK3066_PLL_RATE( 312000000, 1, 52, 4),
96 	RK3066_PLL_RATE( 300000000, 1, 50, 4),
97 	RK3066_PLL_RATE( 297000000, 2, 198, 8),
98 	RK3066_PLL_RATE( 252000000, 1, 84, 8),
99 	RK3066_PLL_RATE( 216000000, 1, 72, 8),
100 	RK3066_PLL_RATE( 148500000, 2, 99, 8),
101 	RK3066_PLL_RATE( 126000000, 1, 84, 16),
102 	RK3066_PLL_RATE(  48000000, 1, 64, 32),
103 	{ /* sentinel */ },
104 };
105 
106 #define RK3066_DIV_CORE_PERIPH_MASK	0x3
107 #define RK3066_DIV_CORE_PERIPH_SHIFT	6
108 #define RK3066_DIV_ACLK_CORE_MASK	0x7
109 #define RK3066_DIV_ACLK_CORE_SHIFT	0
110 #define RK3066_DIV_ACLK_HCLK_MASK	0x3
111 #define RK3066_DIV_ACLK_HCLK_SHIFT	8
112 #define RK3066_DIV_ACLK_PCLK_MASK	0x3
113 #define RK3066_DIV_ACLK_PCLK_SHIFT	12
114 #define RK3066_DIV_AHB2APB_MASK		0x3
115 #define RK3066_DIV_AHB2APB_SHIFT	14
116 
117 #define RK3066_CLKSEL0(_core_peri)					\
118 	{								\
119 		.reg = RK2928_CLKSEL_CON(0),				\
120 		.val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
121 				RK3066_DIV_CORE_PERIPH_SHIFT)		\
122 	}
123 #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb)	\
124 	{								\
125 		.reg = RK2928_CLKSEL_CON(1),				\
126 		.val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
127 				RK3066_DIV_ACLK_CORE_SHIFT) |		\
128 		       HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
129 				RK3066_DIV_ACLK_HCLK_SHIFT) |		\
130 		       HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
131 				RK3066_DIV_ACLK_PCLK_SHIFT) |		\
132 		       HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK,	\
133 				RK3066_DIV_AHB2APB_SHIFT),		\
134 	}
135 
136 #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
137 	{								\
138 		.prate = _prate,					\
139 		.divs = {						\
140 			RK3066_CLKSEL0(_core_peri),			\
141 			RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p),	\
142 		},							\
143 	}
144 
145 static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
146 	RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
147 	RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
148 	RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
149 	RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
150 	RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
151 	RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
152 	RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
153 };
154 
155 static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
156 	.core_reg = RK2928_CLKSEL_CON(0),
157 	.div_core_shift = 0,
158 	.div_core_mask = 0x1f,
159 	.mux_core_alt = 1,
160 	.mux_core_main = 0,
161 	.mux_core_shift = 8,
162 	.mux_core_mask = 0x1,
163 };
164 
165 #define RK3188_DIV_ACLK_CORE_MASK	0x7
166 #define RK3188_DIV_ACLK_CORE_SHIFT	3
167 
168 #define RK3188_CLKSEL1(_aclk_core)		\
169 	{					\
170 		.reg = RK2928_CLKSEL_CON(1),	\
171 		.val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
172 				 RK3188_DIV_ACLK_CORE_SHIFT) \
173 	}
174 #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core)	\
175 	{							\
176 		.prate = _prate,				\
177 		.divs = {					\
178 			RK3066_CLKSEL0(_core_peri),		\
179 			RK3188_CLKSEL1(_aclk_core),		\
180 		},						\
181 	}
182 
183 static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
184 	RK3188_CPUCLK_RATE(1608000000, 2, 3),
185 	RK3188_CPUCLK_RATE(1416000000, 2, 3),
186 	RK3188_CPUCLK_RATE(1200000000, 2, 3),
187 	RK3188_CPUCLK_RATE(1008000000, 2, 3),
188 	RK3188_CPUCLK_RATE( 816000000, 2, 3),
189 	RK3188_CPUCLK_RATE( 600000000, 1, 3),
190 	RK3188_CPUCLK_RATE( 504000000, 1, 3),
191 	RK3188_CPUCLK_RATE( 312000000, 0, 1),
192 };
193 
194 static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
195 	.core_reg = RK2928_CLKSEL_CON(0),
196 	.div_core_shift = 9,
197 	.div_core_mask = 0x1f,
198 	.mux_core_alt = 1,
199 	.mux_core_main = 0,
200 	.mux_core_shift = 8,
201 	.mux_core_mask = 0x1,
202 };
203 
204 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
205 PNAME(mux_armclk_p)		= { "apll", "gpll_armclk" };
206 PNAME(mux_ddrphy_p)		= { "dpll", "gpll_ddr" };
207 PNAME(mux_pll_src_gpll_cpll_p)	= { "gpll", "cpll" };
208 PNAME(mux_pll_src_cpll_gpll_p)	= { "cpll", "gpll" };
209 PNAME(mux_aclk_cpu_p)		= { "apll", "gpll" };
210 PNAME(mux_sclk_cif0_p)		= { "cif0_pre", "xin24m" };
211 PNAME(mux_sclk_i2s0_p)		= { "i2s0_pre", "i2s0_frac", "xin12m" };
212 PNAME(mux_sclk_spdif_p)		= { "spdif_pre", "spdif_frac", "xin12m" };
213 PNAME(mux_sclk_uart0_p)		= { "uart0_pre", "uart0_frac", "xin24m" };
214 PNAME(mux_sclk_uart1_p)		= { "uart1_pre", "uart1_frac", "xin24m" };
215 PNAME(mux_sclk_uart2_p)		= { "uart2_pre", "uart2_frac", "xin24m" };
216 PNAME(mux_sclk_uart3_p)		= { "uart3_pre", "uart3_frac", "xin24m" };
217 PNAME(mux_sclk_hsadc_p)		= { "hsadc_src", "hsadc_frac", "ext_hsadc" };
218 PNAME(mux_mac_p)		= { "gpll", "dpll" };
219 PNAME(mux_sclk_macref_p)	= { "mac_src", "ext_rmii" };
220 
221 static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
222 	[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
223 		     RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
224 	[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
225 		     RK2928_MODE_CON, 4, 4, 0, NULL),
226 	[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
227 		     RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
228 	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
229 		     RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
230 };
231 
232 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
233 	[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
234 		     RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
235 	[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
236 		     RK2928_MODE_CON, 4, 5, 0, NULL),
237 	[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
238 		     RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
239 	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
240 		     RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
241 };
242 
243 #define MFLAGS CLK_MUX_HIWORD_MASK
244 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
245 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
246 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
247 
248 /* 2 ^ (val + 1) */
249 static struct clk_div_table div_core_peri_t[] = {
250 	{ .val = 0, .div = 2 },
251 	{ .val = 1, .div = 4 },
252 	{ .val = 2, .div = 8 },
253 	{ .val = 3, .div = 16 },
254 	{ /* sentinel */ },
255 };
256 
257 static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata =
258 	MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
259 			RK2928_CLKSEL_CON(22), 4, 2, MFLAGS);
260 
261 static struct rockchip_clk_branch common_spdif_fracmux __initdata =
262 	MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
263 			RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
264 
265 static struct rockchip_clk_branch common_uart0_fracmux __initdata =
266 	MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
267 			RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
268 
269 static struct rockchip_clk_branch common_uart1_fracmux __initdata =
270 	MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
271 			RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
272 
273 static struct rockchip_clk_branch common_uart2_fracmux __initdata =
274 	MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
275 			RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
276 
277 static struct rockchip_clk_branch common_uart3_fracmux __initdata =
278 	MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
279 			RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
280 
281 static struct rockchip_clk_branch common_clk_branches[] __initdata = {
282 	/*
283 	 * Clock-Architecture Diagram 2
284 	 */
285 
286 	GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
287 
288 	/* these two are set by the cpuclk and should not be changed */
289 	COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
290 			RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
291 			div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
292 
293 	COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
294 			RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
295 			RK2928_CLKGATE_CON(3), 9, GFLAGS),
296 	GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
297 			RK2928_CLKGATE_CON(3), 10, GFLAGS),
298 	COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
299 			RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
300 			RK2928_CLKGATE_CON(3), 11, GFLAGS),
301 	GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
302 			RK2928_CLKGATE_CON(3), 12, GFLAGS),
303 
304 	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
305 			RK2928_CLKGATE_CON(1), 7, GFLAGS),
306 	COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
307 			RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
308 			RK2928_CLKGATE_CON(0), 2, GFLAGS),
309 
310 	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
311 			RK2928_CLKGATE_CON(0), 3, GFLAGS),
312 
313 	GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
314 			RK2928_CLKGATE_CON(0), 6, GFLAGS),
315 	GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0,
316 			RK2928_CLKGATE_CON(0), 5, GFLAGS),
317 	GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
318 			RK2928_CLKGATE_CON(0), 4, GFLAGS),
319 
320 	COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
321 			RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
322 			RK2928_CLKGATE_CON(3), 0, GFLAGS),
323 	COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
324 			RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
325 			RK2928_CLKGATE_CON(1), 4, GFLAGS),
326 
327 	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0,
328 			RK2928_CLKGATE_CON(2), 1, GFLAGS),
329 	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0,
330 			RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
331 			RK2928_CLKGATE_CON(2), 2, GFLAGS),
332 	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0,
333 			RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
334 			RK2928_CLKGATE_CON(2), 3, GFLAGS),
335 
336 	MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
337 			RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
338 	COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
339 			RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
340 			RK2928_CLKGATE_CON(3), 7, GFLAGS),
341 	MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
342 			RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
343 
344 	GATE(0, "pclkin_cif0", "ext_cif0", 0,
345 			RK2928_CLKGATE_CON(3), 3, GFLAGS),
346 	INVERTER(0, "pclk_cif0", "pclkin_cif0",
347 			RK2928_CLKSEL_CON(30), 8, IFLAGS),
348 
349 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
350 
351 	/*
352 	 * the 480m are generated inside the usb block from these clocks,
353 	 * but they are also a source for the hsicphy clock.
354 	 */
355 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
356 			RK2928_CLKGATE_CON(1), 5, GFLAGS),
357 	GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
358 			RK2928_CLKGATE_CON(1), 6, GFLAGS),
359 
360 	COMPOSITE(0, "mac_src", mux_mac_p, 0,
361 			RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
362 			RK2928_CLKGATE_CON(2), 5, GFLAGS),
363 	MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
364 			RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
365 	GATE(0, "sclk_mac_lbtest", "sclk_macref",
366 			RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
367 
368 	COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
369 			RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
370 			RK2928_CLKGATE_CON(2), 6, GFLAGS),
371 	COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
372 			RK2928_CLKSEL_CON(23), 0,
373 			RK2928_CLKGATE_CON(2), 7, GFLAGS,
374 			&common_hsadc_out_fracmux),
375 	INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
376 			RK2928_CLKSEL_CON(22), 7, IFLAGS),
377 
378 	COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
379 			RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
380 			RK2928_CLKGATE_CON(2), 8, GFLAGS),
381 
382 	COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
383 			RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
384 			RK2928_CLKGATE_CON(0), 13, GFLAGS),
385 	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pll", CLK_SET_RATE_PARENT,
386 			RK2928_CLKSEL_CON(9), 0,
387 			RK2928_CLKGATE_CON(0), 14, GFLAGS,
388 			&common_spdif_fracmux),
389 
390 	/*
391 	 * Clock-Architecture Diagram 4
392 	 */
393 
394 	GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
395 			RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
396 
397 	COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
398 			RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
399 			RK2928_CLKGATE_CON(2), 9, GFLAGS),
400 	COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
401 			RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
402 			RK2928_CLKGATE_CON(2), 10, GFLAGS),
403 
404 	COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
405 			RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
406 			RK2928_CLKGATE_CON(2), 11, GFLAGS),
407 	COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
408 			RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
409 			RK2928_CLKGATE_CON(2), 13, GFLAGS),
410 	COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
411 			RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
412 			RK2928_CLKGATE_CON(2), 14, GFLAGS),
413 
414 	MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
415 			RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
416 	COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
417 			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
418 			RK2928_CLKGATE_CON(1), 8, GFLAGS),
419 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
420 			RK2928_CLKSEL_CON(17), 0,
421 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
422 			&common_uart0_fracmux),
423 	COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
424 			RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
425 			RK2928_CLKGATE_CON(1), 10, GFLAGS),
426 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
427 			RK2928_CLKSEL_CON(18), 0,
428 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
429 			&common_uart1_fracmux),
430 	COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
431 			RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
432 			RK2928_CLKGATE_CON(1), 12, GFLAGS),
433 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
434 			RK2928_CLKSEL_CON(19), 0,
435 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
436 			&common_uart2_fracmux),
437 	COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
438 			RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
439 			RK2928_CLKGATE_CON(1), 14, GFLAGS),
440 	COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
441 			RK2928_CLKSEL_CON(20), 0,
442 			RK2928_CLKGATE_CON(1), 15, GFLAGS,
443 			&common_uart3_fracmux),
444 
445 	GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
446 
447 	GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
448 	GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
449 
450 	/* clk_core_pre gates */
451 	GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
452 
453 	/* aclk_cpu gates */
454 	GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
455 	GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
456 	GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
457 
458 	/* hclk_cpu gates */
459 	GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
460 	GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
461 	GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
462 	GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
463 	/* hclk_ahb2apb is part of a clk branch */
464 	GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
465 	GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
466 	GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
467 	GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
468 	GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
469 	GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
470 
471 	/* hclk_peri gates */
472 	GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
473 	GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
474 	GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
475 	GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
476 	GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
477 	GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
478 	GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
479 	GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
480 	GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
481 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
482 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
483 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
484 
485 	/* aclk_lcdc0_pre gates */
486 	GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
487 	GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
488 	GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
489 	GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
490 
491 	/* aclk_lcdc1_pre gates */
492 	GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
493 	GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
494 	GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
495 
496 	/* atclk_cpu gates */
497 	GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
498 	GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
499 
500 	/* pclk_cpu gates */
501 	GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
502 	GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
503 	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
504 	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
505 	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
506 	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
507 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
508 	GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
509 	GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
510 	GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
511 	GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
512 	GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
513 	GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
514 	GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
515 
516 	/* aclk_peri */
517 	GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
518 	GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
519 	GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
520 	GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
521 	GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
522 
523 	/* pclk_peri gates */
524 	GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
525 	GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
526 	GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
527 	GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
528 	GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
529 	GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
530 	GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
531 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
532 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
533 	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
534 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
535 	GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
536 };
537 
538 PNAME(mux_rk3066_lcdc0_p)	= { "dclk_lcdc0_src", "xin27m" };
539 PNAME(mux_rk3066_lcdc1_p)	= { "dclk_lcdc1_src", "xin27m" };
540 PNAME(mux_sclk_cif1_p)		= { "cif1_pre", "xin24m" };
541 PNAME(mux_sclk_i2s1_p)		= { "i2s1_pre", "i2s1_frac", "xin12m" };
542 PNAME(mux_sclk_i2s2_p)		= { "i2s2_pre", "i2s2_frac", "xin12m" };
543 
544 static struct clk_div_table div_aclk_cpu_t[] = {
545 	{ .val = 0, .div = 1 },
546 	{ .val = 1, .div = 2 },
547 	{ .val = 2, .div = 3 },
548 	{ .val = 3, .div = 4 },
549 	{ .val = 4, .div = 8 },
550 	{ /* sentinel */ },
551 };
552 
553 static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
554 	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
555 			RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
556 
557 static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
558 	MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
559 			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
560 
561 static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
562 	MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
563 			RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
564 
565 static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
566 	DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
567 			RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
568 	DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
569 			RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
570 							    | CLK_DIVIDER_READ_ONLY),
571 	DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
572 			RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
573 							   | CLK_DIVIDER_READ_ONLY),
574 	COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
575 			RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
576 							    | CLK_DIVIDER_READ_ONLY,
577 			RK2928_CLKGATE_CON(4), 9, GFLAGS),
578 
579 	GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
580 			RK2928_CLKGATE_CON(9), 4, GFLAGS),
581 
582 	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
583 			RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
584 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
585 
586 	COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
587 			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
588 			RK2928_CLKGATE_CON(3), 1, GFLAGS),
589 	MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,
590 			RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
591 	COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
592 			RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
593 			RK2928_CLKGATE_CON(3), 2, GFLAGS),
594 	MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,
595 			RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
596 
597 	COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
598 			RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
599 			RK2928_CLKGATE_CON(3), 8, GFLAGS),
600 	MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
601 			RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
602 
603 	GATE(0, "pclkin_cif1", "ext_cif1", 0,
604 			RK2928_CLKGATE_CON(3), 4, GFLAGS),
605 	INVERTER(0, "pclk_cif1", "pclkin_cif1",
606 			RK2928_CLKSEL_CON(30), 12, IFLAGS),
607 
608 	COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
609 			RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
610 			RK2928_CLKGATE_CON(3), 13, GFLAGS),
611 	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
612 			RK2928_CLKGATE_CON(5), 15, GFLAGS),
613 
614 	GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
615 			RK2928_CLKGATE_CON(3), 2, GFLAGS),
616 
617 	COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
618 			RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
619 			RK2928_CLKGATE_CON(2), 15, GFLAGS),
620 
621 	MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
622 			RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
623 	COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
624 			RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
625 			RK2928_CLKGATE_CON(0), 7, GFLAGS),
626 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
627 			RK2928_CLKSEL_CON(6), 0,
628 			RK2928_CLKGATE_CON(0), 8, GFLAGS,
629 			&rk3066a_i2s0_fracmux),
630 	COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
631 			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
632 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
633 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
634 			RK2928_CLKSEL_CON(7), 0,
635 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
636 			&rk3066a_i2s1_fracmux),
637 	COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
638 			RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
639 			RK2928_CLKGATE_CON(0), 11, GFLAGS),
640 	COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
641 			RK2928_CLKSEL_CON(8), 0,
642 			RK2928_CLKGATE_CON(0), 12, GFLAGS,
643 			&rk3066a_i2s2_fracmux),
644 
645 	GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
646 	GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
647 	GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
648 	GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
649 
650 	GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
651 			RK2928_CLKGATE_CON(5), 14, GFLAGS),
652 
653 	GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
654 
655 	GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
656 	GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
657 	GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
658 	GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
659 	GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
660 
661 	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
662 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
663 };
664 
665 static struct clk_div_table div_rk3188_aclk_core_t[] = {
666 	{ .val = 0, .div = 1 },
667 	{ .val = 1, .div = 2 },
668 	{ .val = 2, .div = 3 },
669 	{ .val = 3, .div = 4 },
670 	{ .val = 4, .div = 8 },
671 	{ /* sentinel */ },
672 };
673 
674 PNAME(mux_hsicphy_p)		= { "sclk_otgphy0_480m", "sclk_otgphy1_480m",
675 				    "gpll", "cpll" };
676 
677 static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
678 	MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
679 			RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
680 
681 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
682 	COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
683 			RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
684 			div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
685 
686 	/* do not source aclk_cpu_pre from the apll, to keep complexity down */
687 	COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
688 			RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
689 	DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
690 			RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
691 	DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
692 			RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
693 	COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
694 			RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
695 			RK2928_CLKGATE_CON(4), 9, GFLAGS),
696 
697 	GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
698 			RK2928_CLKGATE_CON(9), 4, GFLAGS),
699 
700 	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
701 			RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
702 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
703 
704 	COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
705 			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
706 			RK2928_CLKGATE_CON(3), 1, GFLAGS),
707 	COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
708 			RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
709 			RK2928_CLKGATE_CON(3), 2, GFLAGS),
710 
711 	COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
712 			RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
713 			RK2928_CLKGATE_CON(3), 15, GFLAGS),
714 	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
715 			RK2928_CLKGATE_CON(9), 7, GFLAGS),
716 
717 	GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
718 	GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
719 	GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
720 	GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
721 	GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
722 
723 	COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
724 			RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
725 			RK2928_CLKGATE_CON(3), 6, GFLAGS),
726 	DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
727 			RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
728 
729 	MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
730 			RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
731 	COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
732 			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
733 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
734 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
735 			RK2928_CLKSEL_CON(7), 0,
736 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
737 			&rk3188_i2s0_fracmux),
738 
739 	GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
740 	GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
741 
742 	GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
743 			RK2928_CLKGATE_CON(7), 3, GFLAGS),
744 	GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
745 
746 	GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
747 
748 	GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
749 	GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
750 
751 	GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
752 };
753 
754 static const char *const rk3188_critical_clocks[] __initconst = {
755 	"aclk_cpu",
756 	"aclk_peri",
757 	"hclk_peri",
758 	"pclk_cpu",
759 	"pclk_peri",
760 	"hclk_cpubus"
761 };
762 
763 static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
764 {
765 	struct rockchip_clk_provider *ctx;
766 	void __iomem *reg_base;
767 
768 	reg_base = of_iomap(np, 0);
769 	if (!reg_base) {
770 		pr_err("%s: could not map cru region\n", __func__);
771 		return ERR_PTR(-ENOMEM);
772 	}
773 
774 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
775 	if (IS_ERR(ctx)) {
776 		pr_err("%s: rockchip clk init failed\n", __func__);
777 		iounmap(reg_base);
778 		return ERR_PTR(-ENOMEM);
779 	}
780 
781 	rockchip_clk_register_branches(ctx, common_clk_branches,
782 				  ARRAY_SIZE(common_clk_branches));
783 
784 	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
785 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
786 
787 	rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
788 
789 	return ctx;
790 }
791 
792 static void __init rk3066a_clk_init(struct device_node *np)
793 {
794 	struct rockchip_clk_provider *ctx;
795 
796 	ctx = rk3188_common_clk_init(np);
797 	if (IS_ERR(ctx))
798 		return;
799 
800 	rockchip_clk_register_plls(ctx, rk3066_pll_clks,
801 				   ARRAY_SIZE(rk3066_pll_clks),
802 				   RK3066_GRF_SOC_STATUS);
803 	rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
804 				  ARRAY_SIZE(rk3066a_clk_branches));
805 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
806 			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
807 			&rk3066_cpuclk_data, rk3066_cpuclk_rates,
808 			ARRAY_SIZE(rk3066_cpuclk_rates));
809 	rockchip_clk_protect_critical(rk3188_critical_clocks,
810 				      ARRAY_SIZE(rk3188_critical_clocks));
811 	rockchip_clk_of_add_provider(np, ctx);
812 }
813 CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
814 
815 static void __init rk3188a_clk_init(struct device_node *np)
816 {
817 	struct rockchip_clk_provider *ctx;
818 	struct clk *clk1, *clk2;
819 	unsigned long rate;
820 	int ret;
821 
822 	ctx = rk3188_common_clk_init(np);
823 	if (IS_ERR(ctx))
824 		return;
825 
826 	rockchip_clk_register_plls(ctx, rk3188_pll_clks,
827 				   ARRAY_SIZE(rk3188_pll_clks),
828 				   RK3188_GRF_SOC_STATUS);
829 	rockchip_clk_register_branches(ctx, rk3188_clk_branches,
830 				  ARRAY_SIZE(rk3188_clk_branches));
831 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
832 				  mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
833 				  &rk3188_cpuclk_data, rk3188_cpuclk_rates,
834 				  ARRAY_SIZE(rk3188_cpuclk_rates));
835 
836 	/* reparent aclk_cpu_pre from apll */
837 	clk1 = __clk_lookup("aclk_cpu_pre");
838 	clk2 = __clk_lookup("gpll");
839 	if (clk1 && clk2) {
840 		rate = clk_get_rate(clk1);
841 
842 		ret = clk_set_parent(clk1, clk2);
843 		if (ret < 0)
844 			pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
845 				__func__);
846 
847 		clk_set_rate(clk1, rate);
848 	} else {
849 		pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
850 			__func__);
851 	}
852 
853 	rockchip_clk_protect_critical(rk3188_critical_clocks,
854 				      ARRAY_SIZE(rk3188_critical_clocks));
855 	rockchip_clk_of_add_provider(np, ctx);
856 }
857 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
858 
859 static void __init rk3188_clk_init(struct device_node *np)
860 {
861 	int i;
862 
863 	for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
864 		struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
865 		struct rockchip_pll_rate_table *rate;
866 
867 		if (!pll->rate_table)
868 			continue;
869 
870 		rate = pll->rate_table;
871 		while (rate->rate > 0) {
872 			rate->nb = 1;
873 			rate++;
874 		}
875 	}
876 
877 	rk3188a_clk_init(np);
878 }
879 CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);
880