1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 4 * Author: Elaine <zhangqing@rock-chips.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/io.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/syscore_ops.h> 12 #include <dt-bindings/clock/rk3128-cru.h> 13 #include "clk.h" 14 15 #define RK3128_GRF_SOC_STATUS0 0x14c 16 17 enum rk3128_plls { 18 apll, dpll, cpll, gpll, 19 }; 20 21 static struct rockchip_pll_rate_table rk3128_pll_rates[] = { 22 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 23 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 24 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 25 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 26 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 27 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 28 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 29 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 30 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 31 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 32 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 34 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 44 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 45 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), 46 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), 47 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), 48 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 49 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), 50 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), 51 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), 52 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), 53 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 54 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), 55 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), 56 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), 57 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 58 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 59 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), 60 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), 61 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 62 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), 63 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 64 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), 65 { /* sentinel */ }, 66 }; 67 68 #define RK3128_DIV_CPU_MASK 0x1f 69 #define RK3128_DIV_CPU_SHIFT 8 70 71 #define RK3128_DIV_PERI_MASK 0xf 72 #define RK3128_DIV_PERI_SHIFT 0 73 #define RK3128_DIV_ACLK_MASK 0x7 74 #define RK3128_DIV_ACLK_SHIFT 4 75 #define RK3128_DIV_HCLK_MASK 0x3 76 #define RK3128_DIV_HCLK_SHIFT 8 77 #define RK3128_DIV_PCLK_MASK 0x7 78 #define RK3128_DIV_PCLK_SHIFT 12 79 80 #define RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div) \ 81 { \ 82 .reg = RK2928_CLKSEL_CON(1), \ 83 .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \ 84 RK3128_DIV_PERI_SHIFT) | \ 85 HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \ 86 RK3128_DIV_ACLK_SHIFT), \ 87 } 88 89 #define RK3128_CPUCLK_RATE(_prate, _core_aclk_div, _pclk_dbg_div) \ 90 { \ 91 .prate = _prate, \ 92 .divs = { \ 93 RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div), \ 94 }, \ 95 } 96 97 static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = { 98 RK3128_CPUCLK_RATE(1800000000, 1, 7), 99 RK3128_CPUCLK_RATE(1704000000, 1, 7), 100 RK3128_CPUCLK_RATE(1608000000, 1, 7), 101 RK3128_CPUCLK_RATE(1512000000, 1, 7), 102 RK3128_CPUCLK_RATE(1488000000, 1, 5), 103 RK3128_CPUCLK_RATE(1416000000, 1, 5), 104 RK3128_CPUCLK_RATE(1392000000, 1, 5), 105 RK3128_CPUCLK_RATE(1296000000, 1, 5), 106 RK3128_CPUCLK_RATE(1200000000, 1, 5), 107 RK3128_CPUCLK_RATE(1104000000, 1, 5), 108 RK3128_CPUCLK_RATE(1008000000, 1, 5), 109 RK3128_CPUCLK_RATE(912000000, 1, 5), 110 RK3128_CPUCLK_RATE(816000000, 1, 3), 111 RK3128_CPUCLK_RATE(696000000, 1, 3), 112 RK3128_CPUCLK_RATE(600000000, 1, 3), 113 RK3128_CPUCLK_RATE(408000000, 1, 1), 114 RK3128_CPUCLK_RATE(312000000, 1, 1), 115 RK3128_CPUCLK_RATE(216000000, 1, 1), 116 RK3128_CPUCLK_RATE(96000000, 1, 1), 117 }; 118 119 static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = { 120 .core_reg[0] = RK2928_CLKSEL_CON(0), 121 .div_core_shift[0] = 0, 122 .div_core_mask[0] = 0x1f, 123 .num_cores = 1, 124 .mux_core_alt = 1, 125 .mux_core_main = 0, 126 .mux_core_shift = 7, 127 .mux_core_mask = 0x1, 128 }; 129 130 PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; 131 132 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_div2_ddr" }; 133 PNAME(mux_armclk_p) = { "apll_core", "gpll_div2_core" }; 134 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; 135 PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" }; 136 137 PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" }; 138 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" }; 139 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" }; 140 141 PNAME(mux_clk_peri_src_p) = { "gpll", "cpll", "gpll_div2", "gpll_div3" }; 142 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" }; 143 PNAME(mux_clk_cif_out_src_p) = { "clk_cif_src", "xin24m" }; 144 PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" }; 145 146 PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; 147 PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; 148 PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; 149 PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; 150 151 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; 152 PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; 153 PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 154 155 PNAME(mux_sclk_gmac_p) = { "sclk_gmac_src", "gmac_clkin" }; 156 PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" }; 157 158 static struct rockchip_pll_clock rk3128_pll_clks[] __initdata = { 159 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 160 RK2928_MODE_CON, 0, 1, 0, rk3128_pll_rates), 161 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 162 RK2928_MODE_CON, 4, 0, 0, NULL), 163 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), 164 RK2928_MODE_CON, 8, 2, 0, rk3128_pll_rates), 165 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), 166 RK2928_MODE_CON, 12, 3, ROCKCHIP_PLL_SYNC_RATE, rk3128_pll_rates), 167 }; 168 169 #define MFLAGS CLK_MUX_HIWORD_MASK 170 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 171 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 172 173 static struct rockchip_clk_branch rk3128_i2s0_fracmux __initdata = 174 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, 175 RK2928_CLKSEL_CON(9), 8, 2, MFLAGS); 176 177 static struct rockchip_clk_branch rk3128_i2s1_fracmux __initdata = 178 MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, 179 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); 180 181 static struct rockchip_clk_branch rk3128_spdif_fracmux __initdata = 182 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, 183 RK2928_CLKSEL_CON(6), 8, 2, MFLAGS); 184 185 static struct rockchip_clk_branch rk3128_uart0_fracmux __initdata = 186 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 187 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); 188 189 static struct rockchip_clk_branch rk3128_uart1_fracmux __initdata = 190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 191 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); 192 193 static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata = 194 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 195 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); 196 197 static struct rockchip_clk_branch common_clk_branches[] __initdata = { 198 /* 199 * Clock-Architecture Diagram 1 200 */ 201 202 FACTOR(PLL_GPLL_DIV2, "gpll_div2", "gpll", 0, 1, 2), 203 FACTOR(PLL_GPLL_DIV3, "gpll_div3", "gpll", 0, 1, 3), 204 205 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, 206 RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), 207 208 /* PD_DDR */ 209 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 210 RK2928_CLKGATE_CON(0), 2, GFLAGS), 211 GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED, 212 RK2928_CLKGATE_CON(0), 2, GFLAGS), 213 COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 214 RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 215 FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2), 216 FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2), 217 218 /* PD_CORE */ 219 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 220 RK2928_CLKGATE_CON(0), 6, GFLAGS), 221 GATE(0, "gpll_div2_core", "gpll_div2", CLK_IGNORE_UNUSED, 222 RK2928_CLKGATE_CON(0), 6, GFLAGS), 223 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, 224 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 225 RK2928_CLKGATE_CON(0), 0, GFLAGS), 226 COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, 227 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 228 RK2928_CLKGATE_CON(0), 7, GFLAGS), 229 230 /* PD_MISC */ 231 MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 232 RK2928_MISC_CON, 15, 1, MFLAGS), 233 234 /* PD_CPU */ 235 COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, 236 RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS, 237 RK2928_CLKGATE_CON(0), 1, GFLAGS), 238 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0, 239 RK2928_CLKGATE_CON(0), 3, GFLAGS), 240 COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0, 241 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, 242 RK2928_CLKGATE_CON(0), 4, GFLAGS), 243 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", 0, 244 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS, 245 RK2928_CLKGATE_CON(0), 5, GFLAGS), 246 COMPOSITE_NOMUX(SCLK_CRYPTO, "clk_crypto", "aclk_cpu_src", 0, 247 RK2928_CLKSEL_CON(24), 0, 2, DFLAGS, 248 RK2928_CLKGATE_CON(0), 12, GFLAGS), 249 250 /* PD_VIDEO */ 251 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0, 252 RK2928_CLKSEL_CON(32), 5, 3, MFLAGS, 0, 5, DFLAGS, 253 RK2928_CLKGATE_CON(3), 9, GFLAGS), 254 FACTOR(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, 1, 4), 255 256 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_5plls_p, 0, 257 RK2928_CLKSEL_CON(32), 13, 3, MFLAGS, 8, 5, DFLAGS, 258 RK2928_CLKGATE_CON(3), 11, GFLAGS), 259 FACTOR_GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, 1, 4, 260 RK2928_CLKGATE_CON(3), 12, GFLAGS), 261 262 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_5plls_p, 0, 263 RK2928_CLKSEL_CON(34), 13, 3, MFLAGS, 8, 5, DFLAGS, 264 RK2928_CLKGATE_CON(3), 10, GFLAGS), 265 266 /* PD_VIO */ 267 COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, 0, 268 RK2928_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS, 269 RK2928_CLKGATE_CON(3), 0, GFLAGS), 270 COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0, 271 RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS, 272 RK2928_CLKGATE_CON(1), 4, GFLAGS), 273 COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0, 274 RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, 275 RK2928_CLKGATE_CON(0), 11, GFLAGS), 276 277 /* PD_PERI */ 278 COMPOSITE(0, "clk_peri_src", mux_clk_peri_src_p, 0, 279 RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS, 280 RK2928_CLKGATE_CON(2), 0, GFLAGS), 281 282 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", 0, 283 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 284 RK2928_CLKGATE_CON(2), 3, GFLAGS), 285 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", 0, 286 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 287 RK2928_CLKGATE_CON(2), 2, GFLAGS), 288 GATE(ACLK_PERI, "aclk_peri", "clk_peri_src", 0, 289 RK2928_CLKGATE_CON(2), 1, GFLAGS), 290 291 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, 292 RK2928_CLKGATE_CON(10), 3, GFLAGS), 293 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, 294 RK2928_CLKGATE_CON(10), 4, GFLAGS), 295 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, 296 RK2928_CLKGATE_CON(10), 5, GFLAGS), 297 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, 298 RK2928_CLKGATE_CON(10), 6, GFLAGS), 299 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, 300 RK2928_CLKGATE_CON(10), 7, GFLAGS), 301 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, 302 RK2928_CLKGATE_CON(10), 8, GFLAGS), 303 304 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0, 305 RK2928_CLKGATE_CON(10), 0, GFLAGS), 306 GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0, 307 RK2928_CLKGATE_CON(10), 1, GFLAGS), 308 GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0, 309 RK2928_CLKGATE_CON(10), 2, GFLAGS), 310 GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED, 311 RK2928_CLKGATE_CON(2), 15, GFLAGS), 312 313 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, 314 RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS, 315 RK2928_CLKGATE_CON(2), 11, GFLAGS), 316 317 COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0, 318 RK2928_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS, 319 RK2928_CLKGATE_CON(2), 13, GFLAGS), 320 321 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, 322 RK2928_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS, 323 RK2928_CLKGATE_CON(2), 14, GFLAGS), 324 325 DIV(SCLK_PVTM, "clk_pvtm", "clk_pvtm_func", 0, 326 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS), 327 328 /* 329 * Clock-Architecture Diagram 2 330 */ 331 COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0, 332 RK2928_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS, 333 RK2928_CLKGATE_CON(3), 1, GFLAGS), 334 COMPOSITE(SCLK_VOP, "sclk_vop", mux_sclk_vop_src_p, 0, 335 RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS, 336 RK2928_CLKGATE_CON(3), 2, GFLAGS), 337 COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0, 338 RK2928_CLKSEL_CON(23), 0, 2, MFLAGS, 8, 8, DFLAGS, 339 RK2928_CLKGATE_CON(3), 4, GFLAGS), 340 341 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 342 343 COMPOSITE_NODIV(SCLK_CIF_SRC, "sclk_cif_src", mux_pll_src_4plls_p, 0, 344 RK2928_CLKSEL_CON(29), 0, 2, MFLAGS, 345 RK2928_CLKGATE_CON(3), 7, GFLAGS), 346 MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0, 347 RK2928_CLKSEL_CON(13), 14, 2, MFLAGS), 348 DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0, 349 RK2928_CLKSEL_CON(29), 2, 5, DFLAGS), 350 351 COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0, 352 RK2928_CLKSEL_CON(9), 14, 2, MFLAGS, 0, 7, DFLAGS, 353 RK2928_CLKGATE_CON(4), 4, GFLAGS), 354 COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, 355 RK2928_CLKSEL_CON(8), 0, 356 RK2928_CLKGATE_CON(4), 5, GFLAGS, 357 &rk3128_i2s0_fracmux), 358 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, 359 RK2928_CLKGATE_CON(4), 6, GFLAGS), 360 361 COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0, 362 RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS, 363 RK2928_CLKGATE_CON(0), 9, GFLAGS), 364 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 365 RK2928_CLKSEL_CON(7), 0, 366 RK2928_CLKGATE_CON(0), 10, GFLAGS, 367 &rk3128_i2s1_fracmux), 368 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 369 RK2928_CLKGATE_CON(0), 14, GFLAGS), 370 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, 371 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, 372 RK2928_CLKGATE_CON(0), 13, GFLAGS), 373 374 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0, 375 RK2928_CLKSEL_CON(6), 14, 2, MFLAGS, 0, 7, DFLAGS, 376 RK2928_CLKGATE_CON(2), 10, GFLAGS), 377 COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, 378 RK2928_CLKSEL_CON(20), 0, 379 RK2928_CLKGATE_CON(2), 12, GFLAGS, 380 &rk3128_spdif_fracmux), 381 382 GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, 383 RK2928_CLKGATE_CON(1), 3, GFLAGS), 384 385 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", 0, 386 RK2928_CLKGATE_CON(1), 5, GFLAGS), 387 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin12m", 0, 388 RK2928_CLKGATE_CON(1), 6, GFLAGS), 389 390 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, 391 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, 392 RK2928_CLKGATE_CON(2), 8, GFLAGS), 393 394 COMPOSITE(ACLK_GPU, "aclk_gpu", mux_pll_src_5plls_p, 0, 395 RK2928_CLKSEL_CON(34), 5, 3, MFLAGS, 0, 5, DFLAGS, 396 RK2928_CLKGATE_CON(3), 13, GFLAGS), 397 398 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0, 399 RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS, 400 RK2928_CLKGATE_CON(2), 9, GFLAGS), 401 402 /* PD_UART */ 403 COMPOSITE(0, "uart0_src", mux_pll_src_4plls_p, 0, 404 RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 405 RK2928_CLKGATE_CON(1), 8, GFLAGS), 406 MUX(0, "uart12_src", mux_pll_src_4plls_p, 0, 407 RK2928_CLKSEL_CON(13), 14, 2, MFLAGS), 408 COMPOSITE_NOMUX(0, "uart1_src", "uart12_src", 0, 409 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, 410 RK2928_CLKGATE_CON(1), 10, GFLAGS), 411 COMPOSITE_NOMUX(0, "uart2_src", "uart12_src", 0, 412 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, 413 RK2928_CLKGATE_CON(1), 13, GFLAGS), 414 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 415 RK2928_CLKSEL_CON(17), 0, 416 RK2928_CLKGATE_CON(1), 9, GFLAGS, 417 &rk3128_uart0_fracmux), 418 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 419 RK2928_CLKSEL_CON(18), 0, 420 RK2928_CLKGATE_CON(1), 11, GFLAGS, 421 &rk3128_uart1_fracmux), 422 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 423 RK2928_CLKSEL_CON(19), 0, 424 RK2928_CLKGATE_CON(1), 13, GFLAGS, 425 &rk3128_uart2_fracmux), 426 427 COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0, 428 RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS, 429 RK2928_CLKGATE_CON(1), 7, GFLAGS), 430 MUX(SCLK_MAC, "sclk_gmac", mux_sclk_gmac_p, 0, 431 RK2928_CLKSEL_CON(5), 15, 1, MFLAGS), 432 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac", 0, 433 RK2928_CLKGATE_CON(2), 5, GFLAGS), 434 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac", 0, 435 RK2928_CLKGATE_CON(2), 4, GFLAGS), 436 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac", 0, 437 RK2928_CLKGATE_CON(2), 6, GFLAGS), 438 GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac", 0, 439 RK2928_CLKGATE_CON(2), 7, GFLAGS), 440 441 COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0, 442 RK2928_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS, 443 RK2928_CLKGATE_CON(1), 14, GFLAGS), 444 445 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0, 446 RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS, 447 RK2928_CLKGATE_CON(10), 15, GFLAGS), 448 449 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0, 450 RK2928_CLKSEL_CON(29), 8, 6, DFLAGS, 451 RK2928_CLKGATE_CON(1), 0, GFLAGS), 452 453 /* 454 * Clock-Architecture Diagram 3 455 */ 456 457 /* PD_VOP */ 458 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS), 459 GATE(ACLK_CIF, "aclk_cif", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS), 460 GATE(ACLK_RGA, "aclk_rga", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS), 461 GATE(0, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS), 462 463 GATE(ACLK_IEP, "aclk_iep", "aclk_vio1", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS), 464 GATE(0, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 10, GFLAGS), 465 466 GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), 467 GATE(PCLK_MIPI, "pclk_mipi", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), 468 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS), 469 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS), 470 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS), 471 GATE(0, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS), 472 GATE(HCLK_CIF, "hclk_cif", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS), 473 GATE(HCLK_EBC, "hclk_ebc", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS), 474 475 /* PD_PERI */ 476 GATE(0, "aclk_peri_axi", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), 477 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(10), 10, GFLAGS), 478 GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), 479 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS), 480 GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), 481 482 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 483 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), 484 GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), 485 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS), 486 GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), 487 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS), 488 GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS), 489 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS), 490 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS), 491 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), 492 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), 493 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), 494 GATE(0, "hclk_emmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 6, GFLAGS), 495 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), 496 GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 14, GFLAGS), 497 498 GATE(PCLK_SIM_CARD, "pclk_sim_card", "pclk_peri", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS), 499 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS), 500 GATE(0, "pclk_peri_axi", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), 501 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), 502 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 503 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), 504 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), 505 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), 506 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), 507 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), 508 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), 509 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), 510 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), 511 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS), 512 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_peri", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), 513 GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 7, GFLAGS), 514 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), 515 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), 516 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), 517 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), 518 519 /* PD_BUS */ 520 GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), 521 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), 522 523 GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS), 524 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), 525 526 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), 527 GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS), 528 GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), 529 GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS), 530 531 GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), 532 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS), 533 534 /* PD_MMC */ 535 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), 536 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0), 537 538 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), 539 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0), 540 541 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), 542 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0), 543 }; 544 545 static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = { 546 GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS), 547 GATE(0, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), 548 GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 8, GFLAGS), 549 }; 550 551 static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = { 552 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0, 553 RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS, 554 RK2928_CLKGATE_CON(3), 15, GFLAGS), 555 556 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), 557 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), 558 }; 559 560 static const char *const rk3128_critical_clocks[] __initconst = { 561 "aclk_cpu", 562 "hclk_cpu", 563 "pclk_cpu", 564 "aclk_peri", 565 "hclk_peri", 566 "pclk_peri", 567 "pclk_pmu", 568 "sclk_timer5", 569 }; 570 571 static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np) 572 { 573 struct rockchip_clk_provider *ctx; 574 void __iomem *reg_base; 575 576 reg_base = of_iomap(np, 0); 577 if (!reg_base) { 578 pr_err("%s: could not map cru region\n", __func__); 579 return ERR_PTR(-ENOMEM); 580 } 581 582 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 583 if (IS_ERR(ctx)) { 584 pr_err("%s: rockchip clk init failed\n", __func__); 585 iounmap(reg_base); 586 return ERR_PTR(-ENOMEM); 587 } 588 589 rockchip_clk_register_plls(ctx, rk3128_pll_clks, 590 ARRAY_SIZE(rk3128_pll_clks), 591 RK3128_GRF_SOC_STATUS0); 592 rockchip_clk_register_branches(ctx, common_clk_branches, 593 ARRAY_SIZE(common_clk_branches)); 594 595 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 596 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 597 &rk3128_cpuclk_data, rk3128_cpuclk_rates, 598 ARRAY_SIZE(rk3128_cpuclk_rates)); 599 600 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), 601 ROCKCHIP_SOFTRST_HIWORD_MASK); 602 603 rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL); 604 605 return ctx; 606 } 607 608 static void __init rk3126_clk_init(struct device_node *np) 609 { 610 struct rockchip_clk_provider *ctx; 611 612 ctx = rk3128_common_clk_init(np); 613 if (IS_ERR(ctx)) 614 return; 615 616 rockchip_clk_register_branches(ctx, rk3126_clk_branches, 617 ARRAY_SIZE(rk3126_clk_branches)); 618 rockchip_clk_protect_critical(rk3128_critical_clocks, 619 ARRAY_SIZE(rk3128_critical_clocks)); 620 621 rockchip_clk_of_add_provider(np, ctx); 622 } 623 624 CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init); 625 626 static void __init rk3128_clk_init(struct device_node *np) 627 { 628 struct rockchip_clk_provider *ctx; 629 630 ctx = rk3128_common_clk_init(np); 631 if (IS_ERR(ctx)) 632 return; 633 634 rockchip_clk_register_branches(ctx, rk3128_clk_branches, 635 ARRAY_SIZE(rk3128_clk_branches)); 636 rockchip_clk_protect_critical(rk3128_critical_clocks, 637 ARRAY_SIZE(rk3128_critical_clocks)); 638 639 rockchip_clk_of_add_provider(np, ctx); 640 } 641 642 CLK_OF_DECLARE(rk3128_cru, "rockchip,rk3128-cru", rk3128_clk_init); 643