xref: /openbmc/linux/drivers/clk/rockchip/clk-px30.c (revision d58f75de)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4  * Author: Elaine Zhang<zhangqing@rock-chips.com>
5  */
6 
7 #include <linux/clk-provider.h>
8 #include <linux/io.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/syscore_ops.h>
12 #include <dt-bindings/clock/px30-cru.h>
13 #include "clk.h"
14 
15 #define PX30_GRF_SOC_STATUS0		0x480
16 
17 enum px30_plls {
18 	apll, dpll, cpll, npll, apll_b_h, apll_b_l,
19 };
20 
21 enum px30_pmu_plls {
22 	gpll,
23 };
24 
25 static struct rockchip_pll_rate_table px30_pll_rates[] = {
26 	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
27 	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
28 	RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
29 	RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
30 	RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
31 	RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
32 	RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
33 	RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
34 	RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
35 	RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
36 	RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
37 	RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
38 	RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
39 	RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
40 	RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
41 	RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
42 	RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
43 	RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
44 	RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
45 	RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
46 	RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
47 	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
48 	RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
49 	RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
50 	RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
51 	RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
52 	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
53 	RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
54 	RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
55 	RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
56 	RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
57 	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
58 	RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
59 	RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
60 	RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
61 	RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
62 	RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
63 	RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
64 	RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
65 	RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
66 	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
67 	RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
68 	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
69 	RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
70 	{ /* sentinel */ },
71 };
72 
73 #define PX30_DIV_ACLKM_MASK		0x7
74 #define PX30_DIV_ACLKM_SHIFT		12
75 #define PX30_DIV_PCLK_DBG_MASK	0xf
76 #define PX30_DIV_PCLK_DBG_SHIFT	8
77 
78 #define PX30_CLKSEL0(_aclk_core, _pclk_dbg)				\
79 {									\
80 	.reg = PX30_CLKSEL_CON(0),					\
81 	.val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK,		\
82 			     PX30_DIV_ACLKM_SHIFT) |			\
83 	       HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK,	\
84 			     PX30_DIV_PCLK_DBG_SHIFT),		\
85 }
86 
87 #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)		\
88 {									\
89 	.prate = _prate,						\
90 	.divs = {							\
91 		PX30_CLKSEL0(_aclk_core, _pclk_dbg),			\
92 	},								\
93 }
94 
95 static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
96 	PX30_CPUCLK_RATE(1608000000, 1, 7),
97 	PX30_CPUCLK_RATE(1584000000, 1, 7),
98 	PX30_CPUCLK_RATE(1560000000, 1, 7),
99 	PX30_CPUCLK_RATE(1536000000, 1, 7),
100 	PX30_CPUCLK_RATE(1512000000, 1, 7),
101 	PX30_CPUCLK_RATE(1488000000, 1, 5),
102 	PX30_CPUCLK_RATE(1464000000, 1, 5),
103 	PX30_CPUCLK_RATE(1440000000, 1, 5),
104 	PX30_CPUCLK_RATE(1416000000, 1, 5),
105 	PX30_CPUCLK_RATE(1392000000, 1, 5),
106 	PX30_CPUCLK_RATE(1368000000, 1, 5),
107 	PX30_CPUCLK_RATE(1344000000, 1, 5),
108 	PX30_CPUCLK_RATE(1320000000, 1, 5),
109 	PX30_CPUCLK_RATE(1296000000, 1, 5),
110 	PX30_CPUCLK_RATE(1272000000, 1, 5),
111 	PX30_CPUCLK_RATE(1248000000, 1, 5),
112 	PX30_CPUCLK_RATE(1224000000, 1, 5),
113 	PX30_CPUCLK_RATE(1200000000, 1, 5),
114 	PX30_CPUCLK_RATE(1104000000, 1, 5),
115 	PX30_CPUCLK_RATE(1008000000, 1, 5),
116 	PX30_CPUCLK_RATE(912000000, 1, 5),
117 	PX30_CPUCLK_RATE(816000000, 1, 3),
118 	PX30_CPUCLK_RATE(696000000, 1, 3),
119 	PX30_CPUCLK_RATE(600000000, 1, 3),
120 	PX30_CPUCLK_RATE(408000000, 1, 1),
121 	PX30_CPUCLK_RATE(312000000, 1, 1),
122 	PX30_CPUCLK_RATE(216000000,  1, 1),
123 	PX30_CPUCLK_RATE(96000000, 1, 1),
124 };
125 
126 static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
127 	.core_reg[0] = PX30_CLKSEL_CON(0),
128 	.div_core_shift[0] = 0,
129 	.div_core_mask[0] = 0xf,
130 	.num_cores = 1,
131 	.mux_core_alt = 1,
132 	.mux_core_main = 0,
133 	.mux_core_shift = 7,
134 	.mux_core_mask = 0x1,
135 };
136 
137 PNAME(mux_pll_p)		= { "xin24m"};
138 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
139 PNAME(mux_armclk_p)		= { "apll_core", "gpll_core" };
140 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
141 PNAME(mux_ddrstdby_p)		= { "clk_ddrphy1x", "clk_stdby_2wrap" };
142 PNAME(mux_4plls_p)		= { "gpll", "dummy_cpll", "usb480m", "npll" };
143 PNAME(mux_cpll_npll_p)		= { "cpll", "npll" };
144 PNAME(mux_npll_cpll_p)		= { "npll", "cpll" };
145 PNAME(mux_gpll_cpll_p)		= { "gpll", "dummy_cpll" };
146 PNAME(mux_gpll_npll_p)		= { "gpll", "npll" };
147 PNAME(mux_gpll_xin24m_p)		= { "gpll", "xin24m"};
148 PNAME(mux_gpll_cpll_npll_p)		= { "gpll", "dummy_cpll", "npll" };
149 PNAME(mux_gpll_cpll_npll_xin24m_p)	= { "gpll", "dummy_cpll", "npll", "xin24m" };
150 PNAME(mux_gpll_xin24m_npll_p)		= { "gpll", "xin24m", "npll"};
151 PNAME(mux_pdm_p)		= { "clk_pdm_src", "clk_pdm_frac" };
152 PNAME(mux_i2s0_tx_p)		= { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
153 PNAME(mux_i2s0_rx_p)		= { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
154 PNAME(mux_i2s1_p)		= { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"};
155 PNAME(mux_i2s2_p)		= { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"};
156 PNAME(mux_i2s0_tx_out_p)	= { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"};
157 PNAME(mux_i2s0_rx_out_p)	= { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"};
158 PNAME(mux_i2s1_out_p)		= { "clk_i2s1", "xin12m"};
159 PNAME(mux_i2s2_out_p)		= { "clk_i2s2", "xin12m"};
160 PNAME(mux_i2s0_tx_rx_p)		= { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
161 PNAME(mux_i2s0_rx_tx_p)		= { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
162 PNAME(mux_uart_src_p)		= { "gpll", "xin24m", "usb480m", "npll" };
163 PNAME(mux_uart1_p)		= { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
164 PNAME(mux_uart2_p)		= { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
165 PNAME(mux_uart3_p)		= { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" };
166 PNAME(mux_uart4_p)		= { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" };
167 PNAME(mux_uart5_p)		= { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
168 PNAME(mux_cif_out_p)		= { "xin24m", "dummy_cpll", "npll", "usb480m" };
169 PNAME(mux_dclk_vopb_p)		= { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
170 PNAME(mux_dclk_vopl_p)		= { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
171 PNAME(mux_nandc_p)		= { "clk_nandc_div", "clk_nandc_div50" };
172 PNAME(mux_sdio_p)		= { "clk_sdio_div", "clk_sdio_div50" };
173 PNAME(mux_emmc_p)		= { "clk_emmc_div", "clk_emmc_div50" };
174 PNAME(mux_sdmmc_p)		= { "clk_sdmmc_div", "clk_sdmmc_div50" };
175 PNAME(mux_gmac_p)		= { "clk_gmac_src", "gmac_clkin" };
176 PNAME(mux_gmac_rmii_sel_p)	= { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" };
177 PNAME(mux_rtc32k_pmu_p)		= { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", };
178 PNAME(mux_wifi_pmu_p)		= { "xin24m", "clk_wifi_pmu_src" };
179 PNAME(mux_uart0_pmu_p)		= { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" };
180 PNAME(mux_usbphy_ref_p)		= { "xin24m", "clk_ref24m_pmu" };
181 PNAME(mux_mipidsiphy_ref_p)	= { "xin24m", "clk_ref24m_pmu" };
182 PNAME(mux_gpu_p)		= { "clk_gpu_div", "clk_gpu_np5" };
183 
184 static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
185 	[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
186 		     0, PX30_PLL_CON(0),
187 		     PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
188 	[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
189 		     0, PX30_PLL_CON(8),
190 		     PX30_MODE_CON, 4, 1, 0, NULL),
191 	[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
192 		     0, PX30_PLL_CON(16),
193 		     PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
194 	[npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
195 		     0, PX30_PLL_CON(24),
196 		     PX30_MODE_CON, 6, 4, 0, px30_pll_rates),
197 };
198 
199 static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {
200 	[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll",  mux_pll_p, 0, PX30_PMU_PLL_CON(0),
201 		     PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
202 };
203 
204 #define MFLAGS CLK_MUX_HIWORD_MASK
205 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
206 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
207 
208 static struct rockchip_clk_branch px30_pdm_fracmux __initdata =
209 	MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
210 			PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
211 
212 static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =
213 	MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
214 			PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
215 
216 static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =
217 	MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
218 			PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
219 
220 static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =
221 	MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
222 			PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
223 
224 static struct rockchip_clk_branch px30_i2s2_fracmux __initdata =
225 	MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
226 			PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
227 
228 static struct rockchip_clk_branch px30_uart1_fracmux __initdata =
229 	MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
230 			PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
231 
232 static struct rockchip_clk_branch px30_uart2_fracmux __initdata =
233 	MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
234 			PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
235 
236 static struct rockchip_clk_branch px30_uart3_fracmux __initdata =
237 	MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
238 			PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
239 
240 static struct rockchip_clk_branch px30_uart4_fracmux __initdata =
241 	MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
242 			PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
243 
244 static struct rockchip_clk_branch px30_uart5_fracmux __initdata =
245 	MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
246 			PX30_CLKSEL_CON(47), 14, 2, MFLAGS);
247 
248 static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata =
249 	MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT,
250 			PX30_CLKSEL_CON(5), 14, 2, MFLAGS);
251 
252 static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata =
253 	MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT,
254 			PX30_CLKSEL_CON(8), 14, 2, MFLAGS);
255 
256 static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata =
257 	MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,
258 			PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
259 
260 static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =
261 	MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
262 			PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
263 
264 static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
265 	/*
266 	 * Clock-Architecture Diagram 1
267 	 */
268 
269 	MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
270 			PX30_MODE_CON, 8, 2, MFLAGS),
271 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
272 
273 	/*
274 	 * Clock-Architecture Diagram 3
275 	 */
276 
277 	/* PD_CORE */
278 	GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
279 			PX30_CLKGATE_CON(0), 0, GFLAGS),
280 	GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
281 			PX30_CLKGATE_CON(0), 0, GFLAGS),
282 	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
283 			PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
284 			PX30_CLKGATE_CON(0), 2, GFLAGS),
285 	COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
286 			PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
287 			PX30_CLKGATE_CON(0), 1, GFLAGS),
288 	GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
289 			PX30_CLKGATE_CON(0), 4, GFLAGS),
290 	GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED,
291 			PX30_CLKGATE_CON(17), 5, GFLAGS),
292 	GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
293 			PX30_CLKGATE_CON(0), 5, GFLAGS),
294 	GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED,
295 			PX30_CLKGATE_CON(0), 6, GFLAGS),
296 	GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED,
297 			PX30_CLKGATE_CON(17), 6, GFLAGS),
298 
299 	GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
300 			PX30_CLKGATE_CON(0), 3, GFLAGS),
301 	GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
302 			PX30_CLKGATE_CON(17), 4, GFLAGS),
303 
304 	/* PD_GPU */
305 	COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0,
306 			PX30_CLKSEL_CON(1), 6, 2, MFLAGS,
307 			PX30_CLKGATE_CON(0), 8, GFLAGS),
308 	COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", 0,
309 			PX30_CLKSEL_CON(1), 0, 4, DFLAGS,
310 			PX30_CLKGATE_CON(0), 12, GFLAGS),
311 	COMPOSITE_NOMUX_HALFDIV(0, "clk_gpu_np5", "clk_gpu_src", 0,
312 			PX30_CLKSEL_CON(1), 8, 4, DFLAGS,
313 			PX30_CLKGATE_CON(0), 9, GFLAGS),
314 	COMPOSITE_NODIV(SCLK_GPU, "clk_gpu", mux_gpu_p, CLK_SET_RATE_PARENT,
315 			PX30_CLKSEL_CON(1), 15, 1, MFLAGS,
316 			PX30_CLKGATE_CON(0), 10, GFLAGS),
317 	COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED,
318 			PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
319 			PX30_CLKGATE_CON(17), 10, GFLAGS),
320 	GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED,
321 			PX30_CLKGATE_CON(0), 11, GFLAGS),
322 	GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED,
323 			PX30_CLKGATE_CON(17), 8, GFLAGS),
324 	GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED,
325 			PX30_CLKGATE_CON(17), 9, GFLAGS),
326 
327 	/*
328 	 * Clock-Architecture Diagram 4
329 	 */
330 
331 	/* PD_DDR */
332 	GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
333 			PX30_CLKGATE_CON(0), 7, GFLAGS),
334 	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
335 			PX30_CLKGATE_CON(0), 13, GFLAGS),
336 	COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED,
337 			PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
338 	COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
339 			PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
340 	FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
341 			PX30_CLKGATE_CON(0), 14, GFLAGS),
342 	FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
343 			PX30_CLKGATE_CON(1), 0, GFLAGS),
344 	COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
345 			PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
346 			PX30_CLKGATE_CON(1), 13, GFLAGS),
347 	GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
348 			PX30_CLKGATE_CON(1), 15, GFLAGS),
349 	GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
350 			PX30_CLKGATE_CON(1), 8, GFLAGS),
351 	GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
352 			PX30_CLKGATE_CON(1), 5, GFLAGS),
353 	GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
354 			PX30_CLKGATE_CON(1), 6, GFLAGS),
355 	GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
356 			PX30_CLKGATE_CON(1), 6, GFLAGS),
357 	GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
358 			PX30_CLKGATE_CON(1), 11, GFLAGS),
359 
360 	GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED,
361 			PX30_CLKGATE_CON(0), 15, GFLAGS),
362 
363 	COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED,
364 			PX30_CLKSEL_CON(2), 8, 5, DFLAGS,
365 			PX30_CLKGATE_CON(1), 1, GFLAGS),
366 	GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
367 			PX30_CLKGATE_CON(1), 10, GFLAGS),
368 	GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
369 			PX30_CLKGATE_CON(1), 7, GFLAGS),
370 	GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
371 			PX30_CLKGATE_CON(1), 9, GFLAGS),
372 	GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
373 			PX30_CLKGATE_CON(1), 12, GFLAGS),
374 	GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
375 			PX30_CLKGATE_CON(1), 14, GFLAGS),
376 	GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED,
377 			PX30_CLKGATE_CON(1), 3, GFLAGS),
378 
379 	/*
380 	 * Clock-Architecture Diagram 5
381 	 */
382 
383 	/* PD_VI */
384 	COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,
385 			PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
386 			PX30_CLKGATE_CON(4), 8, GFLAGS),
387 	COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0,
388 			PX30_CLKSEL_CON(11), 8, 4, DFLAGS,
389 			PX30_CLKGATE_CON(4), 12, GFLAGS),
390 	COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
391 			PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
392 			PX30_CLKGATE_CON(4), 9, GFLAGS),
393 	COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
394 			PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS,
395 			PX30_CLKGATE_CON(4), 11, GFLAGS),
396 	GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
397 			PX30_CLKGATE_CON(4), 13, GFLAGS),
398 	GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
399 			PX30_CLKGATE_CON(4), 14, GFLAGS),
400 
401 	/*
402 	 * Clock-Architecture Diagram 6
403 	 */
404 
405 	/* PD_VO */
406 	COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,
407 			PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS,
408 			PX30_CLKGATE_CON(2), 0, GFLAGS),
409 	COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0,
410 			PX30_CLKSEL_CON(3), 8, 4, DFLAGS,
411 			PX30_CLKGATE_CON(2), 12, GFLAGS),
412 	COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0,
413 			PX30_CLKSEL_CON(3), 12, 4, DFLAGS,
414 			PX30_CLKGATE_CON(2), 13, GFLAGS),
415 	COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,
416 			PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
417 			PX30_CLKGATE_CON(2), 1, GFLAGS),
418 
419 	COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
420 			PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS,
421 			PX30_CLKGATE_CON(2), 5, GFLAGS),
422 	COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
423 			PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS,
424 			PX30_CLKGATE_CON(2), 2, GFLAGS),
425 	COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
426 			PX30_CLKSEL_CON(6), 0,
427 			PX30_CLKGATE_CON(2), 3, GFLAGS,
428 			&px30_dclk_vopb_fracmux),
429 	GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
430 			PX30_CLKGATE_CON(2), 4, GFLAGS),
431 	COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
432 			PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS,
433 			PX30_CLKGATE_CON(2), 6, GFLAGS),
434 	COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
435 			PX30_CLKSEL_CON(9), 0,
436 			PX30_CLKGATE_CON(2), 7, GFLAGS,
437 			&px30_dclk_vopl_fracmux),
438 	GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
439 			PX30_CLKGATE_CON(2), 8, GFLAGS),
440 
441 	/* PD_VPU */
442 	COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
443 			PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
444 			PX30_CLKGATE_CON(4), 0, GFLAGS),
445 	COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0,
446 			PX30_CLKSEL_CON(10), 8, 4, DFLAGS,
447 			PX30_CLKGATE_CON(4), 2, GFLAGS),
448 	COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,
449 			PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS,
450 			PX30_CLKGATE_CON(4), 1, GFLAGS),
451 
452 	/*
453 	 * Clock-Architecture Diagram 7
454 	 */
455 
456 	COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0,
457 			PX30_CLKSEL_CON(14), 15, 1, MFLAGS,
458 			PX30_CLKGATE_CON(5), 7, GFLAGS),
459 	COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
460 			PX30_CLKSEL_CON(14), 0, 5, DFLAGS,
461 			PX30_CLKGATE_CON(5), 8, GFLAGS),
462 	DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
463 			PX30_CLKSEL_CON(14), 8, 5, DFLAGS),
464 
465 	/* PD_MMC_NAND */
466 	GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0,
467 			PX30_CLKGATE_CON(6), 0, GFLAGS),
468 	COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0,
469 			PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
470 			PX30_CLKGATE_CON(5), 11, GFLAGS),
471 	COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
472 			PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5, DFLAGS,
473 			PX30_CLKGATE_CON(5), 12, GFLAGS),
474 	COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p,
475 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
476 			PX30_CLKSEL_CON(15), 15, 1, MFLAGS,
477 			PX30_CLKGATE_CON(5), 13, GFLAGS),
478 
479 	COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0,
480 			PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
481 			PX30_CLKGATE_CON(6), 1, GFLAGS),
482 	COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
483 			mux_gpll_cpll_npll_xin24m_p, 0,
484 			PX30_CLKSEL_CON(18), 14, 2, MFLAGS,
485 			PX30_CLKSEL_CON(19), 0, 8, DFLAGS,
486 			PX30_CLKGATE_CON(6), 2, GFLAGS),
487 	COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p,
488 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
489 			PX30_CLKSEL_CON(19), 15, 1, MFLAGS,
490 			PX30_CLKGATE_CON(6), 3, GFLAGS),
491 
492 	COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
493 			PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
494 			PX30_CLKGATE_CON(6), 4, GFLAGS),
495 	COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
496 			PX30_CLKSEL_CON(20), 14, 2, MFLAGS,
497 			PX30_CLKSEL_CON(21), 0, 8, DFLAGS,
498 			PX30_CLKGATE_CON(6), 5, GFLAGS),
499 	COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p,
500 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
501 			PX30_CLKSEL_CON(21), 15, 1, MFLAGS,
502 			PX30_CLKGATE_CON(6), 6, GFLAGS),
503 
504 	COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
505 			PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS,
506 			PX30_CLKGATE_CON(6), 7, GFLAGS),
507 
508 	MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
509 	    PX30_SDMMC_CON0, 1),
510 	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
511 	    PX30_SDMMC_CON1, 1),
512 
513 	MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
514 	    PX30_SDIO_CON0, 1),
515 	MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
516 	    PX30_SDIO_CON1, 1),
517 
518 	MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
519 	    PX30_EMMC_CON0, 1),
520 	MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
521 	    PX30_EMMC_CON1, 1),
522 
523 	/* PD_SDCARD */
524 	GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
525 			PX30_CLKGATE_CON(6), 12, GFLAGS),
526 	COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
527 			PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
528 			PX30_CLKGATE_CON(6), 13, GFLAGS),
529 	COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
530 			PX30_CLKSEL_CON(16), 14, 2, MFLAGS,
531 			PX30_CLKSEL_CON(17), 0, 8, DFLAGS,
532 			PX30_CLKGATE_CON(6), 14, GFLAGS),
533 	COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p,
534 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
535 			PX30_CLKSEL_CON(17), 15, 1, MFLAGS,
536 			PX30_CLKGATE_CON(6), 15, GFLAGS),
537 
538 	/* PD_USB */
539 	GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0,
540 			PX30_CLKGATE_CON(7), 2, GFLAGS),
541 	GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0,
542 			PX30_CLKGATE_CON(7), 3, GFLAGS),
543 
544 	/* PD_GMAC */
545 	COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0,
546 			PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS,
547 			PX30_CLKGATE_CON(7), 11, GFLAGS),
548 	MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p,  CLK_SET_RATE_PARENT,
549 			PX30_CLKSEL_CON(23), 6, 1, MFLAGS),
550 	GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0,
551 			PX30_CLKGATE_CON(7), 15, GFLAGS),
552 	GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0,
553 			PX30_CLKGATE_CON(7), 13, GFLAGS),
554 	FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2),
555 	FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20),
556 	MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p,  CLK_SET_RATE_PARENT,
557 			PX30_CLKSEL_CON(23), 7, 1, MFLAGS),
558 
559 	GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0,
560 			PX30_CLKGATE_CON(7), 10, GFLAGS),
561 	COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
562 			PX30_CLKSEL_CON(23), 0, 4, DFLAGS,
563 			PX30_CLKGATE_CON(7), 12, GFLAGS),
564 
565 	COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0,
566 			PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
567 			PX30_CLKGATE_CON(8), 5, GFLAGS),
568 
569 	/*
570 	 * Clock-Architecture Diagram 8
571 	 */
572 
573 	/* PD_BUS */
574 	COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
575 			PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
576 			PX30_CLKGATE_CON(8), 6, GFLAGS),
577 	COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
578 			PX30_CLKSEL_CON(24), 0, 5, DFLAGS,
579 			PX30_CLKGATE_CON(8), 8, GFLAGS),
580 	COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
581 			PX30_CLKSEL_CON(23), 8, 5, DFLAGS,
582 			PX30_CLKGATE_CON(8), 7, GFLAGS),
583 	COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED,
584 			PX30_CLKSEL_CON(24), 8, 2, DFLAGS,
585 			PX30_CLKGATE_CON(8), 9, GFLAGS),
586 	GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
587 			PX30_CLKGATE_CON(8), 10, GFLAGS),
588 
589 	COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
590 			PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS,
591 			PX30_CLKGATE_CON(9), 9, GFLAGS),
592 	COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
593 			PX30_CLKSEL_CON(27), 0,
594 			PX30_CLKGATE_CON(9), 10, GFLAGS,
595 			&px30_pdm_fracmux),
596 	GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
597 			PX30_CLKGATE_CON(9), 11, GFLAGS),
598 
599 	COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
600 			PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS,
601 			PX30_CLKGATE_CON(9), 12, GFLAGS),
602 	COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
603 			PX30_CLKSEL_CON(29), 0,
604 			PX30_CLKGATE_CON(9), 13, GFLAGS,
605 			&px30_i2s0_tx_fracmux),
606 	COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
607 			PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
608 			PX30_CLKGATE_CON(9), 14, GFLAGS),
609 	COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0,
610 			PX30_CLKSEL_CON(28), 14, 2, MFLAGS,
611 			PX30_CLKGATE_CON(9), 15, GFLAGS),
612 	GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,
613 			PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK),
614 
615 	COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
616 			PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
617 			PX30_CLKGATE_CON(17), 0, GFLAGS),
618 	COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
619 			PX30_CLKSEL_CON(59), 0,
620 			PX30_CLKGATE_CON(17), 1, GFLAGS,
621 			&px30_i2s0_rx_fracmux),
622 	COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
623 			PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
624 			PX30_CLKGATE_CON(17), 2, GFLAGS),
625 	COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0,
626 			PX30_CLKSEL_CON(58), 14, 2, MFLAGS,
627 			PX30_CLKGATE_CON(17), 3, GFLAGS),
628 	GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT,
629 			PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK),
630 
631 	COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
632 			PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
633 			PX30_CLKGATE_CON(10), 0, GFLAGS),
634 	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
635 			PX30_CLKSEL_CON(31), 0,
636 			PX30_CLKGATE_CON(10), 1, GFLAGS,
637 			&px30_i2s1_fracmux),
638 	GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
639 			PX30_CLKGATE_CON(10), 2, GFLAGS),
640 	COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0,
641 			PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
642 			PX30_CLKGATE_CON(10), 3, GFLAGS),
643 	GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,
644 			PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK),
645 
646 	COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
647 			PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
648 			PX30_CLKGATE_CON(10), 4, GFLAGS),
649 	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
650 			PX30_CLKSEL_CON(33), 0,
651 			PX30_CLKGATE_CON(10), 5, GFLAGS,
652 			&px30_i2s2_fracmux),
653 	GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
654 			PX30_CLKGATE_CON(10), 6, GFLAGS),
655 	COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
656 			PX30_CLKSEL_CON(32), 15, 1, MFLAGS,
657 			PX30_CLKGATE_CON(10), 7, GFLAGS),
658 	GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT,
659 			PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK),
660 
661 	COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,
662 			PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS,
663 			PX30_CLKGATE_CON(10), 12, GFLAGS),
664 	COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0,
665 			PX30_CLKSEL_CON(35), 0, 5, DFLAGS,
666 			PX30_CLKGATE_CON(10), 13, GFLAGS),
667 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
668 			PX30_CLKSEL_CON(36), 0,
669 			PX30_CLKGATE_CON(10), 14, GFLAGS,
670 			&px30_uart1_fracmux),
671 	GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
672 			PX30_CLKGATE_CON(10), 15, GFLAGS),
673 
674 	COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0,
675 			PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS,
676 			PX30_CLKGATE_CON(11), 0, GFLAGS),
677 	COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0,
678 			PX30_CLKSEL_CON(38), 0, 5, DFLAGS,
679 			PX30_CLKGATE_CON(11), 1, GFLAGS),
680 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
681 			PX30_CLKSEL_CON(39), 0,
682 			PX30_CLKGATE_CON(11), 2, GFLAGS,
683 			&px30_uart2_fracmux),
684 	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
685 			PX30_CLKGATE_CON(11), 3, GFLAGS),
686 
687 	COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
688 			PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS,
689 			PX30_CLKGATE_CON(11), 4, GFLAGS),
690 	COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0,
691 			PX30_CLKSEL_CON(41), 0, 5, DFLAGS,
692 			PX30_CLKGATE_CON(11), 5, GFLAGS),
693 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
694 			PX30_CLKSEL_CON(42), 0,
695 			PX30_CLKGATE_CON(11), 6, GFLAGS,
696 			&px30_uart3_fracmux),
697 	GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
698 			PX30_CLKGATE_CON(11), 7, GFLAGS),
699 
700 	COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
701 			PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS,
702 			PX30_CLKGATE_CON(11), 8, GFLAGS),
703 	COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0,
704 			PX30_CLKSEL_CON(44), 0, 5, DFLAGS,
705 			PX30_CLKGATE_CON(11), 9, GFLAGS),
706 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
707 			PX30_CLKSEL_CON(45), 0,
708 			PX30_CLKGATE_CON(11), 10, GFLAGS,
709 			&px30_uart4_fracmux),
710 	GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
711 			PX30_CLKGATE_CON(11), 11, GFLAGS),
712 
713 	COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
714 			PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS,
715 			PX30_CLKGATE_CON(11), 12, GFLAGS),
716 	COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0,
717 			PX30_CLKSEL_CON(47), 0, 5, DFLAGS,
718 			PX30_CLKGATE_CON(11), 13, GFLAGS),
719 	COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
720 			PX30_CLKSEL_CON(48), 0,
721 			PX30_CLKGATE_CON(11), 14, GFLAGS,
722 			&px30_uart5_fracmux),
723 	GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
724 			PX30_CLKGATE_CON(11), 15, GFLAGS),
725 
726 	COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
727 			PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS,
728 			PX30_CLKGATE_CON(12), 0, GFLAGS),
729 	COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
730 			PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS,
731 			PX30_CLKGATE_CON(12), 1, GFLAGS),
732 	COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
733 			PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS,
734 			PX30_CLKGATE_CON(12), 2, GFLAGS),
735 	COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
736 			PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS,
737 			PX30_CLKGATE_CON(12), 3, GFLAGS),
738 	COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
739 			PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,
740 			PX30_CLKGATE_CON(12), 5, GFLAGS),
741 	COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
742 			PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS,
743 			PX30_CLKGATE_CON(12), 6, GFLAGS),
744 	COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
745 			PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
746 			PX30_CLKGATE_CON(12), 7, GFLAGS),
747 	COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
748 			PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS,
749 			PX30_CLKGATE_CON(12), 8, GFLAGS),
750 
751 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
752 			PX30_CLKGATE_CON(13), 0, GFLAGS),
753 	GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
754 			PX30_CLKGATE_CON(13), 1, GFLAGS),
755 	GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
756 			PX30_CLKGATE_CON(13), 2, GFLAGS),
757 	GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
758 			PX30_CLKGATE_CON(13), 3, GFLAGS),
759 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
760 			PX30_CLKGATE_CON(13), 4, GFLAGS),
761 	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
762 			PX30_CLKGATE_CON(13), 5, GFLAGS),
763 
764 	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
765 			PX30_CLKSEL_CON(54), 0, 11, DFLAGS,
766 			PX30_CLKGATE_CON(12), 9, GFLAGS),
767 	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
768 			PX30_CLKSEL_CON(55), 0, 11, DFLAGS,
769 			PX30_CLKGATE_CON(12), 10, GFLAGS),
770 	COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
771 			PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
772 			PX30_CLKGATE_CON(12), 11, GFLAGS),
773 	COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
774 			PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
775 			PX30_CLKGATE_CON(13), 6, GFLAGS),
776 
777 	GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
778 			PX30_CLKGATE_CON(12), 12, GFLAGS),
779 
780 	/* PD_CRYPTO */
781 	GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0,
782 			PX30_CLKGATE_CON(8), 12, GFLAGS),
783 	GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0,
784 			PX30_CLKGATE_CON(8), 13, GFLAGS),
785 	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0,
786 			PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
787 			PX30_CLKGATE_CON(8), 14, GFLAGS),
788 	COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0,
789 			PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS,
790 			PX30_CLKGATE_CON(8), 15, GFLAGS),
791 
792 	/*
793 	 * Clock-Architecture Diagram 9
794 	 */
795 
796 	/* PD_BUS_TOP */
797 	GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS),
798 	GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS),
799 	GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
800 	GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
801 	GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
802 	GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
803 	GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 6, GFLAGS),
804 	GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
805 
806 	/* PD_VI */
807 	GATE(0, "aclk_vi_niu", "aclk_vi_pre", 0, PX30_CLKGATE_CON(4), 15, GFLAGS),
808 	GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
809 	GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
810 	GATE(0, "hclk_vi_niu", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 0, GFLAGS),
811 	GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
812 	GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
813 
814 	/* PD_VO */
815 	GATE(0, "aclk_vo_niu", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 0, GFLAGS),
816 	GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
817 	GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
818 	GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
819 
820 	GATE(0, "hclk_vo_niu", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 1, GFLAGS),
821 	GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
822 	GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
823 	GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
824 
825 	GATE(0, "pclk_vo_niu", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 2, GFLAGS),
826 	GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
827 
828 	/* PD_BUS */
829 	GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS),
830 	GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS),
831 	GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
832 	GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
833 
834 	/* aclk_dmac is controlled by sgrf_soc_con1[11]. */
835 	SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
836 
837 	GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
838 	GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
839 	GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
840 	GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS),
841 	GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS),
842 	GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS),
843 
844 	GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS),
845 	GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS),
846 	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
847 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS),
848 	GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
849 	GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS),
850 	GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
851 	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS),
852 	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS),
853 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS),
854 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS),
855 	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS),
856 	GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
857 	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS),
858 	GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
859 	GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS),
860 	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS),
861 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS),
862 	GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS),
863 	GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS),
864 	GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS),
865 	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS),
866 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS),
867 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS),
868 	GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS),
869 	GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS),
870 
871 	/* PD_VPU */
872 	GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS),
873 	GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
874 	GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS),
875 	GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS),
876 
877 	/* PD_CRYPTO */
878 	GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS),
879 	GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS),
880 	GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS),
881 	GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS),
882 
883 	/* PD_SDCARD */
884 	GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS),
885 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
886 
887 	/* PD_PERI */
888 	GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS),
889 
890 	/* PD_MMC_NAND */
891 	GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
892 	GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS),
893 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS),
894 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS),
895 	GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS),
896 
897 	/* PD_USB */
898 	GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS),
899 	GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
900 	GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
901 	GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS),
902 
903 	/* PD_GMAC */
904 	GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
905 			PX30_CLKGATE_CON(8), 0, GFLAGS),
906 	GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
907 			PX30_CLKGATE_CON(8), 2, GFLAGS),
908 	GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
909 			PX30_CLKGATE_CON(8), 1, GFLAGS),
910 	GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
911 			PX30_CLKGATE_CON(8), 3, GFLAGS),
912 };
913 
914 static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
915 	/*
916 	 * Clock-Architecture Diagram 2
917 	 */
918 
919 	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
920 			PX30_PMU_CLKSEL_CON(1), 0,
921 			PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
922 			&px30_rtc32k_pmu_fracmux),
923 
924 	COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
925 			PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
926 			PX30_PMU_CLKGATE_CON(0), 12, GFLAGS),
927 
928 	COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0,
929 			PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS,
930 			PX30_PMU_CLKGATE_CON(0), 14, GFLAGS),
931 	COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
932 			PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS,
933 			PX30_PMU_CLKGATE_CON(0), 15, GFLAGS),
934 
935 	COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0,
936 			PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS,
937 			PX30_PMU_CLKGATE_CON(1), 0, GFLAGS),
938 	COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
939 			PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS,
940 			PX30_PMU_CLKGATE_CON(1), 1, GFLAGS),
941 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
942 			PX30_PMU_CLKSEL_CON(5), 0,
943 			PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
944 			&px30_uart0_pmu_fracmux),
945 	GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
946 			PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
947 
948 	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
949 			PX30_PMU_CLKGATE_CON(1), 4, GFLAGS),
950 
951 	COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0,
952 			PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
953 			PX30_PMU_CLKGATE_CON(0), 0, GFLAGS),
954 
955 	COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0,
956 			PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
957 			PX30_PMU_CLKGATE_CON(1), 8, GFLAGS),
958 	COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
959 			PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
960 			PX30_PMU_CLKGATE_CON(1), 9, GFLAGS),
961 	COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
962 			PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
963 			PX30_PMU_CLKGATE_CON(1), 10, GFLAGS),
964 
965 	/*
966 	 * Clock-Architecture Diagram 9
967 	 */
968 
969 	/* PD_PMU */
970 	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS),
971 	GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS),
972 	GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS),
973 	GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS),
974 	GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS),
975 	GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS),
976 	GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),
977 	GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
978 };
979 
980 static const char *const px30_cru_critical_clocks[] __initconst = {
981 	"aclk_bus_pre",
982 	"pclk_bus_pre",
983 	"hclk_bus_pre",
984 	"aclk_peri_pre",
985 	"hclk_peri_pre",
986 	"aclk_gpu_niu",
987 	"pclk_top_pre",
988 	"pclk_pmu_pre",
989 	"hclk_usb_niu",
990 	"pclk_vo_niu",
991 	"aclk_vo_niu",
992 	"hclk_vo_niu",
993 	"aclk_vi_niu",
994 	"hclk_vi_niu",
995 	"pll_npll",
996 	"usb480m",
997 	"clk_uart2",
998 	"pclk_uart2",
999 	"pclk_usb_grf",
1000 };
1001 
1002 static void __init px30_clk_init(struct device_node *np)
1003 {
1004 	struct rockchip_clk_provider *ctx;
1005 	void __iomem *reg_base;
1006 
1007 	reg_base = of_iomap(np, 0);
1008 	if (!reg_base) {
1009 		pr_err("%s: could not map cru region\n", __func__);
1010 		return;
1011 	}
1012 
1013 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1014 	if (IS_ERR(ctx)) {
1015 		pr_err("%s: rockchip clk init failed\n", __func__);
1016 		iounmap(reg_base);
1017 		return;
1018 	}
1019 
1020 	rockchip_clk_register_plls(ctx, px30_pll_clks,
1021 				   ARRAY_SIZE(px30_pll_clks),
1022 				   PX30_GRF_SOC_STATUS0);
1023 	rockchip_clk_register_branches(ctx, px30_clk_branches,
1024 				       ARRAY_SIZE(px30_clk_branches));
1025 
1026 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1027 				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1028 				     &px30_cpuclk_data, px30_cpuclk_rates,
1029 				     ARRAY_SIZE(px30_cpuclk_rates));
1030 
1031 	rockchip_clk_protect_critical(px30_cru_critical_clocks,
1032 				      ARRAY_SIZE(px30_cru_critical_clocks));
1033 
1034 	rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
1035 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
1036 
1037 	rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL);
1038 
1039 	rockchip_clk_of_add_provider(np, ctx);
1040 }
1041 CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
1042 
1043 static void __init px30_pmu_clk_init(struct device_node *np)
1044 {
1045 	struct rockchip_clk_provider *ctx;
1046 	void __iomem *reg_base;
1047 
1048 	reg_base = of_iomap(np, 0);
1049 	if (!reg_base) {
1050 		pr_err("%s: could not map cru pmu region\n", __func__);
1051 		return;
1052 	}
1053 
1054 	ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1055 	if (IS_ERR(ctx)) {
1056 		pr_err("%s: rockchip pmu clk init failed\n", __func__);
1057 		return;
1058 	}
1059 
1060 	rockchip_clk_register_plls(ctx, px30_pmu_pll_clks,
1061 				   ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
1062 
1063 	rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
1064 				       ARRAY_SIZE(px30_clk_pmu_branches));
1065 
1066 	rockchip_clk_of_add_provider(np, ctx);
1067 }
1068 CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);
1069