1 /* 2 * Copyright (c) 2018 Rockchip Electronics Co. Ltd. 3 * Author: Elaine Zhang<zhangqing@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/syscore_ops.h> 20 #include <dt-bindings/clock/px30-cru.h> 21 #include "clk.h" 22 23 #define PX30_GRF_SOC_STATUS0 0x480 24 25 enum px30_plls { 26 apll, dpll, cpll, npll, apll_b_h, apll_b_l, 27 }; 28 29 enum px30_pmu_plls { 30 gpll, 31 }; 32 33 static struct rockchip_pll_rate_table px30_pll_rates[] = { 34 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 35 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 49 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 52 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 53 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 54 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 55 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 56 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 57 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), 58 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), 59 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), 60 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 61 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), 62 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), 63 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), 64 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), 65 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 66 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), 67 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), 68 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), 69 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0), 70 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 71 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 72 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), 73 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), 74 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 75 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), 76 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 77 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), 78 { /* sentinel */ }, 79 }; 80 81 #define PX30_DIV_ACLKM_MASK 0x7 82 #define PX30_DIV_ACLKM_SHIFT 12 83 #define PX30_DIV_PCLK_DBG_MASK 0xf 84 #define PX30_DIV_PCLK_DBG_SHIFT 8 85 86 #define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \ 87 { \ 88 .reg = PX30_CLKSEL_CON(0), \ 89 .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \ 90 PX30_DIV_ACLKM_SHIFT) | \ 91 HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \ 92 PX30_DIV_PCLK_DBG_SHIFT), \ 93 } 94 95 #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ 96 { \ 97 .prate = _prate, \ 98 .divs = { \ 99 PX30_CLKSEL0(_aclk_core, _pclk_dbg), \ 100 }, \ 101 } 102 103 static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = { 104 PX30_CPUCLK_RATE(1608000000, 1, 7), 105 PX30_CPUCLK_RATE(1584000000, 1, 7), 106 PX30_CPUCLK_RATE(1560000000, 1, 7), 107 PX30_CPUCLK_RATE(1536000000, 1, 7), 108 PX30_CPUCLK_RATE(1512000000, 1, 7), 109 PX30_CPUCLK_RATE(1488000000, 1, 5), 110 PX30_CPUCLK_RATE(1464000000, 1, 5), 111 PX30_CPUCLK_RATE(1440000000, 1, 5), 112 PX30_CPUCLK_RATE(1416000000, 1, 5), 113 PX30_CPUCLK_RATE(1392000000, 1, 5), 114 PX30_CPUCLK_RATE(1368000000, 1, 5), 115 PX30_CPUCLK_RATE(1344000000, 1, 5), 116 PX30_CPUCLK_RATE(1320000000, 1, 5), 117 PX30_CPUCLK_RATE(1296000000, 1, 5), 118 PX30_CPUCLK_RATE(1272000000, 1, 5), 119 PX30_CPUCLK_RATE(1248000000, 1, 5), 120 PX30_CPUCLK_RATE(1224000000, 1, 5), 121 PX30_CPUCLK_RATE(1200000000, 1, 5), 122 PX30_CPUCLK_RATE(1104000000, 1, 5), 123 PX30_CPUCLK_RATE(1008000000, 1, 5), 124 PX30_CPUCLK_RATE(912000000, 1, 5), 125 PX30_CPUCLK_RATE(816000000, 1, 3), 126 PX30_CPUCLK_RATE(696000000, 1, 3), 127 PX30_CPUCLK_RATE(600000000, 1, 3), 128 PX30_CPUCLK_RATE(408000000, 1, 1), 129 PX30_CPUCLK_RATE(312000000, 1, 1), 130 PX30_CPUCLK_RATE(216000000, 1, 1), 131 PX30_CPUCLK_RATE(96000000, 1, 1), 132 }; 133 134 static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = { 135 .core_reg = PX30_CLKSEL_CON(0), 136 .div_core_shift = 0, 137 .div_core_mask = 0xf, 138 .mux_core_alt = 1, 139 .mux_core_main = 0, 140 .mux_core_shift = 7, 141 .mux_core_mask = 0x1, 142 }; 143 144 PNAME(mux_pll_p) = { "xin24m"}; 145 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" }; 146 PNAME(mux_armclk_p) = { "apll_core", "gpll_core" }; 147 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; 148 PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" }; 149 PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" }; 150 PNAME(mux_cpll_npll_p) = { "cpll", "npll" }; 151 PNAME(mux_npll_cpll_p) = { "npll", "cpll" }; 152 PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" }; 153 PNAME(mux_gpll_npll_p) = { "gpll", "npll" }; 154 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"}; 155 PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" }; 156 PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" }; 157 PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"}; 158 PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" }; 159 PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"}; 160 PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"}; 161 PNAME(mux_i2s1_p) = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"}; 162 PNAME(mux_i2s2_p) = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"}; 163 PNAME(mux_i2s0_tx_out_p) = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"}; 164 PNAME(mux_i2s0_rx_out_p) = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"}; 165 PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"}; 166 PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"}; 167 PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"}; 168 PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"}; 169 PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" }; 170 PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" }; 171 PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" }; 172 PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" }; 173 PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" }; 174 PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" }; 175 PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" }; 176 PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" }; 177 PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" }; 178 PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" }; 179 PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" }; 180 PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", }; 181 PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" }; 182 PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" }; 183 PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; 184 PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; 185 PNAME(mux_gpu_p) = { "clk_gpu_div", "clk_gpu_np5" }; 186 187 static struct rockchip_pll_clock px30_pll_clks[] __initdata = { 188 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 189 0, PX30_PLL_CON(0), 190 PX30_MODE_CON, 0, 0, 0, px30_pll_rates), 191 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 192 0, PX30_PLL_CON(8), 193 PX30_MODE_CON, 4, 1, 0, NULL), 194 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 195 0, PX30_PLL_CON(16), 196 PX30_MODE_CON, 2, 2, 0, px30_pll_rates), 197 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 198 0, PX30_PLL_CON(24), 199 PX30_MODE_CON, 6, 4, 0, px30_pll_rates), 200 }; 201 202 static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = { 203 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0), 204 PX30_PMU_MODE, 0, 3, 0, px30_pll_rates), 205 }; 206 207 #define MFLAGS CLK_MUX_HIWORD_MASK 208 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 209 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 210 211 static struct rockchip_clk_branch px30_pdm_fracmux __initdata = 212 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, 213 PX30_CLKSEL_CON(26), 15, 1, MFLAGS); 214 215 static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata = 216 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT, 217 PX30_CLKSEL_CON(28), 10, 2, MFLAGS); 218 219 static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata = 220 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT, 221 PX30_CLKSEL_CON(58), 10, 2, MFLAGS); 222 223 static struct rockchip_clk_branch px30_i2s1_fracmux __initdata = 224 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, 225 PX30_CLKSEL_CON(30), 10, 2, MFLAGS); 226 227 static struct rockchip_clk_branch px30_i2s2_fracmux __initdata = 228 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, 229 PX30_CLKSEL_CON(32), 10, 2, MFLAGS); 230 231 static struct rockchip_clk_branch px30_uart1_fracmux __initdata = 232 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, 233 PX30_CLKSEL_CON(35), 14, 2, MFLAGS); 234 235 static struct rockchip_clk_branch px30_uart2_fracmux __initdata = 236 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, 237 PX30_CLKSEL_CON(38), 14, 2, MFLAGS); 238 239 static struct rockchip_clk_branch px30_uart3_fracmux __initdata = 240 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, 241 PX30_CLKSEL_CON(41), 14, 2, MFLAGS); 242 243 static struct rockchip_clk_branch px30_uart4_fracmux __initdata = 244 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, 245 PX30_CLKSEL_CON(44), 14, 2, MFLAGS); 246 247 static struct rockchip_clk_branch px30_uart5_fracmux __initdata = 248 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, 249 PX30_CLKSEL_CON(47), 14, 2, MFLAGS); 250 251 static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata = 252 MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT, 253 PX30_CLKSEL_CON(5), 14, 2, MFLAGS); 254 255 static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata = 256 MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT, 257 PX30_CLKSEL_CON(8), 14, 2, MFLAGS); 258 259 static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata = 260 MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT, 261 PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS); 262 263 static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata = 264 MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT, 265 PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS); 266 267 static struct rockchip_clk_branch px30_clk_branches[] __initdata = { 268 /* 269 * Clock-Architecture Diagram 1 270 */ 271 272 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 273 PX30_MODE_CON, 8, 2, MFLAGS), 274 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 275 276 /* 277 * Clock-Architecture Diagram 3 278 */ 279 280 /* PD_CORE */ 281 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 282 PX30_CLKGATE_CON(0), 0, GFLAGS), 283 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 284 PX30_CLKGATE_CON(0), 0, GFLAGS), 285 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, 286 PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 287 PX30_CLKGATE_CON(0), 2, GFLAGS), 288 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, 289 PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 290 PX30_CLKGATE_CON(0), 1, GFLAGS), 291 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, 292 PX30_CLKGATE_CON(0), 4, GFLAGS), 293 GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED, 294 PX30_CLKGATE_CON(17), 5, GFLAGS), 295 GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED, 296 PX30_CLKGATE_CON(0), 5, GFLAGS), 297 GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED, 298 PX30_CLKGATE_CON(0), 6, GFLAGS), 299 GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED, 300 PX30_CLKGATE_CON(17), 6, GFLAGS), 301 302 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED, 303 PX30_CLKGATE_CON(0), 3, GFLAGS), 304 GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0, 305 PX30_CLKGATE_CON(17), 4, GFLAGS), 306 307 /* PD_GPU */ 308 COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0, 309 PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 310 PX30_CLKGATE_CON(0), 8, GFLAGS), 311 COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", 0, 312 PX30_CLKSEL_CON(1), 0, 4, DFLAGS, 313 PX30_CLKGATE_CON(0), 12, GFLAGS), 314 COMPOSITE_NOMUX_HALFDIV(0, "clk_gpu_np5", "clk_gpu_src", 0, 315 PX30_CLKSEL_CON(1), 8, 4, DFLAGS, 316 PX30_CLKGATE_CON(0), 9, GFLAGS), 317 COMPOSITE_NODIV(SCLK_GPU, "clk_gpu", mux_gpu_p, CLK_SET_RATE_PARENT, 318 PX30_CLKSEL_CON(1), 15, 1, MFLAGS, 319 PX30_CLKGATE_CON(0), 10, GFLAGS), 320 COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED, 321 PX30_CLKSEL_CON(1), 13, 2, DFLAGS, 322 PX30_CLKGATE_CON(17), 10, GFLAGS), 323 GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED, 324 PX30_CLKGATE_CON(0), 11, GFLAGS), 325 GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED, 326 PX30_CLKGATE_CON(17), 8, GFLAGS), 327 GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED, 328 PX30_CLKGATE_CON(17), 9, GFLAGS), 329 330 /* 331 * Clock-Architecture Diagram 4 332 */ 333 334 /* PD_DDR */ 335 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 336 PX30_CLKGATE_CON(0), 7, GFLAGS), 337 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 338 PX30_CLKGATE_CON(0), 13, GFLAGS), 339 COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED, 340 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 341 COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 342 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS), 343 FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, 344 PX30_CLKGATE_CON(0), 14, GFLAGS), 345 FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, 346 PX30_CLKGATE_CON(1), 0, GFLAGS), 347 COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED, 348 PX30_CLKSEL_CON(2), 4, 1, MFLAGS, 349 PX30_CLKGATE_CON(1), 13, GFLAGS), 350 GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 351 PX30_CLKGATE_CON(1), 15, GFLAGS), 352 GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 353 PX30_CLKGATE_CON(1), 8, GFLAGS), 354 GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 355 PX30_CLKGATE_CON(1), 5, GFLAGS), 356 GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 357 PX30_CLKGATE_CON(1), 6, GFLAGS), 358 GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 359 PX30_CLKGATE_CON(1), 6, GFLAGS), 360 GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 361 PX30_CLKGATE_CON(1), 11, GFLAGS), 362 363 GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED, 364 PX30_CLKGATE_CON(0), 15, GFLAGS), 365 366 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED, 367 PX30_CLKSEL_CON(2), 8, 5, DFLAGS, 368 PX30_CLKGATE_CON(1), 1, GFLAGS), 369 GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED, 370 PX30_CLKGATE_CON(1), 10, GFLAGS), 371 GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED, 372 PX30_CLKGATE_CON(1), 7, GFLAGS), 373 GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED, 374 PX30_CLKGATE_CON(1), 9, GFLAGS), 375 GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED, 376 PX30_CLKGATE_CON(1), 12, GFLAGS), 377 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, 378 PX30_CLKGATE_CON(1), 14, GFLAGS), 379 GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED, 380 PX30_CLKGATE_CON(1), 3, GFLAGS), 381 382 /* 383 * Clock-Architecture Diagram 5 384 */ 385 386 /* PD_VI */ 387 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0, 388 PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, 389 PX30_CLKGATE_CON(4), 8, GFLAGS), 390 COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0, 391 PX30_CLKSEL_CON(11), 8, 4, DFLAGS, 392 PX30_CLKGATE_CON(4), 12, GFLAGS), 393 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0, 394 PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, 395 PX30_CLKGATE_CON(4), 9, GFLAGS), 396 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0, 397 PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS, 398 PX30_CLKGATE_CON(4), 11, GFLAGS), 399 GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0, 400 PX30_CLKGATE_CON(4), 13, GFLAGS), 401 GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0, 402 PX30_CLKGATE_CON(4), 14, GFLAGS), 403 404 /* 405 * Clock-Architecture Diagram 6 406 */ 407 408 /* PD_VO */ 409 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0, 410 PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS, 411 PX30_CLKGATE_CON(2), 0, GFLAGS), 412 COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0, 413 PX30_CLKSEL_CON(3), 8, 4, DFLAGS, 414 PX30_CLKGATE_CON(2), 12, GFLAGS), 415 COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0, 416 PX30_CLKSEL_CON(3), 12, 4, DFLAGS, 417 PX30_CLKGATE_CON(2), 13, GFLAGS), 418 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0, 419 PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS, 420 PX30_CLKGATE_CON(2), 1, GFLAGS), 421 422 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0, 423 PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS, 424 PX30_CLKGATE_CON(2), 5, GFLAGS), 425 COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 426 PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS, 427 PX30_CLKGATE_CON(2), 2, GFLAGS), 428 COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT, 429 PX30_CLKSEL_CON(6), 0, 430 PX30_CLKGATE_CON(2), 3, GFLAGS, 431 &px30_dclk_vopb_fracmux), 432 GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT, 433 PX30_CLKGATE_CON(2), 4, GFLAGS), 434 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0, 435 PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS, 436 PX30_CLKGATE_CON(2), 6, GFLAGS), 437 COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT, 438 PX30_CLKSEL_CON(9), 0, 439 PX30_CLKGATE_CON(2), 7, GFLAGS, 440 &px30_dclk_vopl_fracmux), 441 GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT, 442 PX30_CLKGATE_CON(2), 8, GFLAGS), 443 444 /* PD_VPU */ 445 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0, 446 PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, 447 PX30_CLKGATE_CON(4), 0, GFLAGS), 448 COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 449 PX30_CLKSEL_CON(10), 8, 4, DFLAGS, 450 PX30_CLKGATE_CON(4), 2, GFLAGS), 451 COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0, 452 PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS, 453 PX30_CLKGATE_CON(4), 1, GFLAGS), 454 455 /* 456 * Clock-Architecture Diagram 7 457 */ 458 459 COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0, 460 PX30_CLKSEL_CON(14), 15, 1, MFLAGS, 461 PX30_CLKGATE_CON(5), 7, GFLAGS), 462 COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED, 463 PX30_CLKSEL_CON(14), 0, 5, DFLAGS, 464 PX30_CLKGATE_CON(5), 8, GFLAGS), 465 DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED, 466 PX30_CLKSEL_CON(14), 8, 5, DFLAGS), 467 468 /* PD_MMC_NAND */ 469 GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0, 470 PX30_CLKGATE_CON(6), 0, GFLAGS), 471 COMPOSITE(SCLK_NANDC, "clk_nandc", mux_gpll_cpll_npll_p, 0, 472 PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS, 473 PX30_CLKGATE_CON(5), 13, GFLAGS), 474 475 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_gpll_cpll_npll_xin24m_p, 0, 476 PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS, 477 PX30_CLKGATE_CON(6), 3, GFLAGS), 478 479 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_gpll_cpll_npll_xin24m_p, 0, 480 PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS, 481 PX30_CLKGATE_CON(6), 6, GFLAGS), 482 483 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0, 484 PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS, 485 PX30_CLKGATE_CON(6), 7, GFLAGS), 486 487 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", 488 PX30_SDMMC_CON0, 1), 489 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", 490 PX30_SDMMC_CON1, 1), 491 492 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", 493 PX30_SDIO_CON0, 1), 494 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", 495 PX30_SDIO_CON1, 1), 496 497 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", 498 PX30_EMMC_CON0, 1), 499 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", 500 PX30_EMMC_CON1, 1), 501 502 /* PD_SDCARD */ 503 GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0, 504 PX30_CLKGATE_CON(6), 12, GFLAGS), 505 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_npll_xin24m_p, 0, 506 PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS, 507 PX30_CLKGATE_CON(6), 15, GFLAGS), 508 509 /* PD_USB */ 510 GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0, 511 PX30_CLKGATE_CON(7), 2, GFLAGS), 512 GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0, 513 PX30_CLKGATE_CON(7), 3, GFLAGS), 514 515 /* PD_GMAC */ 516 COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0, 517 PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS, 518 PX30_CLKGATE_CON(7), 11, GFLAGS), 519 MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT, 520 PX30_CLKSEL_CON(23), 6, 1, MFLAGS), 521 GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0, 522 PX30_CLKGATE_CON(7), 15, GFLAGS), 523 GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0, 524 PX30_CLKGATE_CON(7), 13, GFLAGS), 525 FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2), 526 FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20), 527 MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT, 528 PX30_CLKSEL_CON(23), 7, 1, MFLAGS), 529 530 GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0, 531 PX30_CLKGATE_CON(7), 10, GFLAGS), 532 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, 533 PX30_CLKSEL_CON(23), 0, 4, DFLAGS, 534 PX30_CLKGATE_CON(7), 12, GFLAGS), 535 536 COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0, 537 PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, 538 PX30_CLKGATE_CON(8), 5, GFLAGS), 539 540 /* 541 * Clock-Architecture Diagram 8 542 */ 543 544 /* PD_BUS */ 545 COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED, 546 PX30_CLKSEL_CON(23), 15, 1, MFLAGS, 547 PX30_CLKGATE_CON(8), 6, GFLAGS), 548 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED, 549 PX30_CLKSEL_CON(24), 0, 5, DFLAGS, 550 PX30_CLKGATE_CON(8), 8, GFLAGS), 551 COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED, 552 PX30_CLKSEL_CON(23), 8, 5, DFLAGS, 553 PX30_CLKGATE_CON(8), 7, GFLAGS), 554 COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED, 555 PX30_CLKSEL_CON(24), 8, 2, DFLAGS, 556 PX30_CLKGATE_CON(8), 9, GFLAGS), 557 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 558 PX30_CLKGATE_CON(8), 10, GFLAGS), 559 560 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0, 561 PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS, 562 PX30_CLKGATE_CON(9), 9, GFLAGS), 563 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT, 564 PX30_CLKSEL_CON(27), 0, 565 PX30_CLKGATE_CON(9), 10, GFLAGS, 566 &px30_pdm_fracmux), 567 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT, 568 PX30_CLKGATE_CON(9), 11, GFLAGS), 569 570 COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0, 571 PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS, 572 PX30_CLKGATE_CON(9), 12, GFLAGS), 573 COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT, 574 PX30_CLKSEL_CON(29), 0, 575 PX30_CLKGATE_CON(9), 13, GFLAGS, 576 &px30_i2s0_tx_fracmux), 577 COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT, 578 PX30_CLKSEL_CON(28), 12, 1, MFLAGS, 579 PX30_CLKGATE_CON(9), 14, GFLAGS), 580 COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0, 581 PX30_CLKSEL_CON(28), 14, 2, MFLAGS, 582 PX30_CLKGATE_CON(9), 15, GFLAGS), 583 GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT, 584 PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK), 585 586 COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0, 587 PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS, 588 PX30_CLKGATE_CON(17), 0, GFLAGS), 589 COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT, 590 PX30_CLKSEL_CON(59), 0, 591 PX30_CLKGATE_CON(17), 1, GFLAGS, 592 &px30_i2s0_rx_fracmux), 593 COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT, 594 PX30_CLKSEL_CON(58), 12, 1, MFLAGS, 595 PX30_CLKGATE_CON(17), 2, GFLAGS), 596 COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0, 597 PX30_CLKSEL_CON(58), 14, 2, MFLAGS, 598 PX30_CLKGATE_CON(17), 3, GFLAGS), 599 GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT, 600 PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK), 601 602 COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0, 603 PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS, 604 PX30_CLKGATE_CON(10), 0, GFLAGS), 605 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT, 606 PX30_CLKSEL_CON(31), 0, 607 PX30_CLKGATE_CON(10), 1, GFLAGS, 608 &px30_i2s1_fracmux), 609 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, 610 PX30_CLKGATE_CON(10), 2, GFLAGS), 611 COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0, 612 PX30_CLKSEL_CON(30), 15, 1, MFLAGS, 613 PX30_CLKGATE_CON(10), 3, GFLAGS), 614 GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT, 615 PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK), 616 617 COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0, 618 PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS, 619 PX30_CLKGATE_CON(10), 4, GFLAGS), 620 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT, 621 PX30_CLKSEL_CON(33), 0, 622 PX30_CLKGATE_CON(10), 5, GFLAGS, 623 &px30_i2s2_fracmux), 624 GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, 625 PX30_CLKGATE_CON(10), 6, GFLAGS), 626 COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0, 627 PX30_CLKSEL_CON(32), 15, 1, MFLAGS, 628 PX30_CLKGATE_CON(10), 7, GFLAGS), 629 GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT, 630 PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK), 631 632 COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT, 633 PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS, 634 PX30_CLKGATE_CON(10), 12, GFLAGS), 635 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0, 636 PX30_CLKSEL_CON(35), 0, 5, DFLAGS, 637 PX30_CLKGATE_CON(10), 13, GFLAGS), 638 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 639 PX30_CLKSEL_CON(36), 0, 640 PX30_CLKGATE_CON(10), 14, GFLAGS, 641 &px30_uart1_fracmux), 642 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT, 643 PX30_CLKGATE_CON(10), 15, GFLAGS), 644 645 COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0, 646 PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS, 647 PX30_CLKGATE_CON(11), 0, GFLAGS), 648 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0, 649 PX30_CLKSEL_CON(38), 0, 5, DFLAGS, 650 PX30_CLKGATE_CON(11), 1, GFLAGS), 651 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 652 PX30_CLKSEL_CON(39), 0, 653 PX30_CLKGATE_CON(11), 2, GFLAGS, 654 &px30_uart2_fracmux), 655 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT, 656 PX30_CLKGATE_CON(11), 3, GFLAGS), 657 658 COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0, 659 PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS, 660 PX30_CLKGATE_CON(11), 4, GFLAGS), 661 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0, 662 PX30_CLKSEL_CON(41), 0, 5, DFLAGS, 663 PX30_CLKGATE_CON(11), 5, GFLAGS), 664 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 665 PX30_CLKSEL_CON(42), 0, 666 PX30_CLKGATE_CON(11), 6, GFLAGS, 667 &px30_uart3_fracmux), 668 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT, 669 PX30_CLKGATE_CON(11), 7, GFLAGS), 670 671 COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0, 672 PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS, 673 PX30_CLKGATE_CON(11), 8, GFLAGS), 674 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0, 675 PX30_CLKSEL_CON(44), 0, 5, DFLAGS, 676 PX30_CLKGATE_CON(11), 9, GFLAGS), 677 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 678 PX30_CLKSEL_CON(45), 0, 679 PX30_CLKGATE_CON(11), 10, GFLAGS, 680 &px30_uart4_fracmux), 681 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT, 682 PX30_CLKGATE_CON(11), 11, GFLAGS), 683 684 COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0, 685 PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS, 686 PX30_CLKGATE_CON(11), 12, GFLAGS), 687 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0, 688 PX30_CLKSEL_CON(47), 0, 5, DFLAGS, 689 PX30_CLKGATE_CON(11), 13, GFLAGS), 690 COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 691 PX30_CLKSEL_CON(48), 0, 692 PX30_CLKGATE_CON(11), 14, GFLAGS, 693 &px30_uart5_fracmux), 694 GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT, 695 PX30_CLKGATE_CON(11), 15, GFLAGS), 696 697 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0, 698 PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS, 699 PX30_CLKGATE_CON(12), 0, GFLAGS), 700 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, 701 PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS, 702 PX30_CLKGATE_CON(12), 1, GFLAGS), 703 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, 704 PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS, 705 PX30_CLKGATE_CON(12), 2, GFLAGS), 706 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, 707 PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS, 708 PX30_CLKGATE_CON(12), 3, GFLAGS), 709 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, 710 PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS, 711 PX30_CLKGATE_CON(12), 5, GFLAGS), 712 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0, 713 PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS, 714 PX30_CLKGATE_CON(12), 6, GFLAGS), 715 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, 716 PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS, 717 PX30_CLKGATE_CON(12), 7, GFLAGS), 718 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0, 719 PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS, 720 PX30_CLKGATE_CON(12), 8, GFLAGS), 721 722 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, 723 PX30_CLKGATE_CON(13), 0, GFLAGS), 724 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, 725 PX30_CLKGATE_CON(13), 1, GFLAGS), 726 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, 727 PX30_CLKGATE_CON(13), 2, GFLAGS), 728 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, 729 PX30_CLKGATE_CON(13), 3, GFLAGS), 730 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, 731 PX30_CLKGATE_CON(13), 4, GFLAGS), 732 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, 733 PX30_CLKGATE_CON(13), 5, GFLAGS), 734 735 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0, 736 PX30_CLKSEL_CON(54), 0, 11, DFLAGS, 737 PX30_CLKGATE_CON(12), 9, GFLAGS), 738 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, 739 PX30_CLKSEL_CON(55), 0, 11, DFLAGS, 740 PX30_CLKGATE_CON(12), 10, GFLAGS), 741 COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0, 742 PX30_CLKSEL_CON(56), 0, 3, DFLAGS, 743 PX30_CLKGATE_CON(12), 11, GFLAGS), 744 COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0, 745 PX30_CLKSEL_CON(56), 4, 2, DFLAGS, 746 PX30_CLKGATE_CON(13), 6, GFLAGS), 747 748 GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED, 749 PX30_CLKGATE_CON(12), 12, GFLAGS), 750 751 /* PD_CRYPTO */ 752 GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0, 753 PX30_CLKGATE_CON(8), 12, GFLAGS), 754 GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0, 755 PX30_CLKGATE_CON(8), 13, GFLAGS), 756 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0, 757 PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS, 758 PX30_CLKGATE_CON(8), 14, GFLAGS), 759 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0, 760 PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS, 761 PX30_CLKGATE_CON(8), 15, GFLAGS), 762 763 /* 764 * Clock-Architecture Diagram 9 765 */ 766 767 /* PD_BUS_TOP */ 768 GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS), 769 GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS), 770 GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS), 771 GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS), 772 GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS), 773 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS), 774 GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 6, GFLAGS), 775 GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS), 776 777 /* PD_VI */ 778 GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 15, GFLAGS), 779 GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS), 780 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS), 781 GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 0, GFLAGS), 782 GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS), 783 GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS), 784 785 /* PD_VO */ 786 GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 0, GFLAGS), 787 GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS), 788 GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS), 789 GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS), 790 791 GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 1, GFLAGS), 792 GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS), 793 GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS), 794 GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS), 795 796 GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 2, GFLAGS), 797 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS), 798 799 /* PD_BUS */ 800 GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS), 801 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS), 802 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS), 803 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS), 804 805 GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS), 806 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS), 807 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS), 808 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS), 809 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS), 810 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS), 811 812 GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS), 813 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS), 814 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS), 815 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS), 816 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS), 817 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS), 818 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS), 819 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS), 820 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS), 821 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS), 822 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS), 823 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS), 824 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS), 825 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS), 826 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS), 827 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS), 828 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS), 829 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS), 830 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS), 831 GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS), 832 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS), 833 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS), 834 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS), 835 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS), 836 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS), 837 GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS), 838 839 /* PD_VPU */ 840 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS), 841 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS), 842 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS), 843 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS), 844 845 /* PD_CRYPTO */ 846 GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS), 847 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS), 848 GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS), 849 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS), 850 851 /* PD_SDCARD */ 852 GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS), 853 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS), 854 855 /* PD_PERI */ 856 GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS), 857 858 /* PD_MMC_NAND */ 859 GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS), 860 GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS), 861 GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS), 862 GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS), 863 GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS), 864 865 /* PD_USB */ 866 GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS), 867 GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS), 868 GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS), 869 GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS), 870 871 /* PD_GMAC */ 872 GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 873 PX30_CLKGATE_CON(8), 0, GFLAGS), 874 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, 875 PX30_CLKGATE_CON(8), 2, GFLAGS), 876 GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED, 877 PX30_CLKGATE_CON(8), 1, GFLAGS), 878 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, 879 PX30_CLKGATE_CON(8), 3, GFLAGS), 880 }; 881 882 static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = { 883 /* 884 * Clock-Architecture Diagram 2 885 */ 886 887 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, 888 PX30_PMU_CLKSEL_CON(1), 0, 889 PX30_PMU_CLKGATE_CON(0), 13, GFLAGS, 890 &px30_rtc32k_pmu_fracmux), 891 892 COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED, 893 PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS, 894 PX30_PMU_CLKGATE_CON(0), 12, GFLAGS), 895 896 COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0, 897 PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS, 898 PX30_PMU_CLKGATE_CON(0), 14, GFLAGS), 899 COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, 900 PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS, 901 PX30_PMU_CLKGATE_CON(0), 15, GFLAGS), 902 903 COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0, 904 PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS, 905 PX30_PMU_CLKGATE_CON(1), 0, GFLAGS), 906 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0, 907 PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS, 908 PX30_PMU_CLKGATE_CON(1), 1, GFLAGS), 909 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT, 910 PX30_PMU_CLKSEL_CON(5), 0, 911 PX30_PMU_CLKGATE_CON(1), 2, GFLAGS, 912 &px30_uart0_pmu_fracmux), 913 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, 914 PX30_PMU_CLKGATE_CON(1), 3, GFLAGS), 915 916 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, 917 PX30_PMU_CLKGATE_CON(1), 4, GFLAGS), 918 919 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0, 920 PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, 921 PX30_PMU_CLKGATE_CON(0), 0, GFLAGS), 922 923 COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0, 924 PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS, 925 PX30_PMU_CLKGATE_CON(1), 8, GFLAGS), 926 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT, 927 PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, 928 PX30_PMU_CLKGATE_CON(1), 9, GFLAGS), 929 COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT, 930 PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS, 931 PX30_PMU_CLKGATE_CON(1), 10, GFLAGS), 932 933 /* 934 * Clock-Architecture Diagram 9 935 */ 936 937 /* PD_PMU */ 938 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS), 939 GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS), 940 GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS), 941 GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS), 942 GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS), 943 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS), 944 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS), 945 GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS), 946 }; 947 948 static const char *const px30_pmucru_critical_clocks[] __initconst = { 949 "aclk_bus_pre", 950 "pclk_bus_pre", 951 "hclk_bus_pre", 952 "aclk_peri_pre", 953 "hclk_peri_pre", 954 "aclk_gpu_niu", 955 "pclk_top_pre", 956 "pclk_pmu_pre", 957 "hclk_usb_niu", 958 "pll_npll", 959 "usb480m", 960 "clk_uart2", 961 "pclk_uart2", 962 }; 963 964 static void __init px30_clk_init(struct device_node *np) 965 { 966 struct rockchip_clk_provider *ctx; 967 void __iomem *reg_base; 968 struct clk *clk; 969 970 reg_base = of_iomap(np, 0); 971 if (!reg_base) { 972 pr_err("%s: could not map cru region\n", __func__); 973 return; 974 } 975 976 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 977 if (IS_ERR(ctx)) { 978 pr_err("%s: rockchip clk init failed\n", __func__); 979 iounmap(reg_base); 980 return; 981 } 982 983 /* aclk_dmac is controlled by sgrf_soc_con1[11]. */ 984 clk = clk_register_fixed_factor(NULL, "aclk_dmac", "aclk_bus_pre", 0, 1, 1); 985 if (IS_ERR(clk)) 986 pr_warn("%s: could not register clock aclk_dmac: %ld\n", 987 __func__, PTR_ERR(clk)); 988 else 989 rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC); 990 991 rockchip_clk_register_plls(ctx, px30_pll_clks, 992 ARRAY_SIZE(px30_pll_clks), 993 PX30_GRF_SOC_STATUS0); 994 rockchip_clk_register_branches(ctx, px30_clk_branches, 995 ARRAY_SIZE(px30_clk_branches)); 996 997 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 998 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 999 &px30_cpuclk_data, px30_cpuclk_rates, 1000 ARRAY_SIZE(px30_cpuclk_rates)); 1001 1002 rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0), 1003 ROCKCHIP_SOFTRST_HIWORD_MASK); 1004 1005 rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL); 1006 1007 rockchip_clk_of_add_provider(np, ctx); 1008 } 1009 CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init); 1010 1011 static void __init px30_pmu_clk_init(struct device_node *np) 1012 { 1013 struct rockchip_clk_provider *ctx; 1014 void __iomem *reg_base; 1015 1016 reg_base = of_iomap(np, 0); 1017 if (!reg_base) { 1018 pr_err("%s: could not map cru pmu region\n", __func__); 1019 return; 1020 } 1021 1022 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 1023 if (IS_ERR(ctx)) { 1024 pr_err("%s: rockchip pmu clk init failed\n", __func__); 1025 return; 1026 } 1027 1028 rockchip_clk_register_plls(ctx, px30_pmu_pll_clks, 1029 ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0); 1030 1031 rockchip_clk_register_branches(ctx, px30_clk_pmu_branches, 1032 ARRAY_SIZE(px30_clk_pmu_branches)); 1033 1034 rockchip_clk_protect_critical(px30_pmucru_critical_clocks, 1035 ARRAY_SIZE(px30_pmucru_critical_clocks)); 1036 1037 rockchip_clk_of_add_provider(np, ctx); 1038 } 1039 CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init); 1040