1 /* 2 * Copyright (c) 2018 Rockchip Electronics Co. Ltd. 3 * Author: Elaine Zhang<zhangqing@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/syscore_ops.h> 21 #include <dt-bindings/clock/px30-cru.h> 22 #include "clk.h" 23 24 #define PX30_GRF_SOC_STATUS0 0x480 25 26 enum px30_plls { 27 apll, dpll, cpll, npll, apll_b_h, apll_b_l, 28 }; 29 30 enum px30_pmu_plls { 31 gpll, 32 }; 33 34 static struct rockchip_pll_rate_table px30_pll_rates[] = { 35 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 36 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 37 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 38 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 39 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 40 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 49 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 52 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 53 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 54 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 55 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 56 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 57 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 58 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), 59 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), 60 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), 61 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 62 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), 63 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), 64 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), 65 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), 66 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 67 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), 68 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), 69 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), 70 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0), 71 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 72 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 73 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), 74 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), 75 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 76 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), 77 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 78 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), 79 { /* sentinel */ }, 80 }; 81 82 #define PX30_DIV_ACLKM_MASK 0x7 83 #define PX30_DIV_ACLKM_SHIFT 12 84 #define PX30_DIV_PCLK_DBG_MASK 0xf 85 #define PX30_DIV_PCLK_DBG_SHIFT 8 86 87 #define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \ 88 { \ 89 .reg = PX30_CLKSEL_CON(0), \ 90 .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \ 91 PX30_DIV_ACLKM_SHIFT) | \ 92 HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \ 93 PX30_DIV_PCLK_DBG_SHIFT), \ 94 } 95 96 #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \ 97 { \ 98 .prate = _prate, \ 99 .divs = { \ 100 PX30_CLKSEL0(_aclk_core, _pclk_dbg), \ 101 }, \ 102 } 103 104 static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = { 105 PX30_CPUCLK_RATE(1608000000, 1, 7), 106 PX30_CPUCLK_RATE(1584000000, 1, 7), 107 PX30_CPUCLK_RATE(1560000000, 1, 7), 108 PX30_CPUCLK_RATE(1536000000, 1, 7), 109 PX30_CPUCLK_RATE(1512000000, 1, 7), 110 PX30_CPUCLK_RATE(1488000000, 1, 5), 111 PX30_CPUCLK_RATE(1464000000, 1, 5), 112 PX30_CPUCLK_RATE(1440000000, 1, 5), 113 PX30_CPUCLK_RATE(1416000000, 1, 5), 114 PX30_CPUCLK_RATE(1392000000, 1, 5), 115 PX30_CPUCLK_RATE(1368000000, 1, 5), 116 PX30_CPUCLK_RATE(1344000000, 1, 5), 117 PX30_CPUCLK_RATE(1320000000, 1, 5), 118 PX30_CPUCLK_RATE(1296000000, 1, 5), 119 PX30_CPUCLK_RATE(1272000000, 1, 5), 120 PX30_CPUCLK_RATE(1248000000, 1, 5), 121 PX30_CPUCLK_RATE(1224000000, 1, 5), 122 PX30_CPUCLK_RATE(1200000000, 1, 5), 123 PX30_CPUCLK_RATE(1104000000, 1, 5), 124 PX30_CPUCLK_RATE(1008000000, 1, 5), 125 PX30_CPUCLK_RATE(912000000, 1, 5), 126 PX30_CPUCLK_RATE(816000000, 1, 3), 127 PX30_CPUCLK_RATE(696000000, 1, 3), 128 PX30_CPUCLK_RATE(600000000, 1, 3), 129 PX30_CPUCLK_RATE(408000000, 1, 1), 130 PX30_CPUCLK_RATE(312000000, 1, 1), 131 PX30_CPUCLK_RATE(216000000, 1, 1), 132 PX30_CPUCLK_RATE(96000000, 1, 1), 133 }; 134 135 static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = { 136 .core_reg = PX30_CLKSEL_CON(0), 137 .div_core_shift = 0, 138 .div_core_mask = 0xf, 139 .mux_core_alt = 1, 140 .mux_core_main = 0, 141 .mux_core_shift = 7, 142 .mux_core_mask = 0x1, 143 }; 144 145 PNAME(mux_pll_p) = { "xin24m"}; 146 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" }; 147 PNAME(mux_armclk_p) = { "apll_core", "gpll_core" }; 148 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; 149 PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" }; 150 PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" }; 151 PNAME(mux_cpll_npll_p) = { "cpll", "npll" }; 152 PNAME(mux_npll_cpll_p) = { "npll", "cpll" }; 153 PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" }; 154 PNAME(mux_gpll_npll_p) = { "gpll", "npll" }; 155 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"}; 156 PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" }; 157 PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" }; 158 PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"}; 159 PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" }; 160 PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"}; 161 PNAME(mux_i2s0_rx_p) = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"}; 162 PNAME(mux_i2s1_p) = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"}; 163 PNAME(mux_i2s2_p) = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"}; 164 PNAME(mux_i2s0_tx_out_p) = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"}; 165 PNAME(mux_i2s0_rx_out_p) = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"}; 166 PNAME(mux_i2s1_out_p) = { "clk_i2s1", "xin12m"}; 167 PNAME(mux_i2s2_out_p) = { "clk_i2s2", "xin12m"}; 168 PNAME(mux_i2s0_tx_rx_p) = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"}; 169 PNAME(mux_i2s0_rx_tx_p) = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"}; 170 PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" }; 171 PNAME(mux_uart1_p) = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" }; 172 PNAME(mux_uart2_p) = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" }; 173 PNAME(mux_uart3_p) = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" }; 174 PNAME(mux_uart4_p) = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" }; 175 PNAME(mux_uart5_p) = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" }; 176 PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" }; 177 PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" }; 178 PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" }; 179 PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" }; 180 PNAME(mux_gmac_rmii_sel_p) = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" }; 181 PNAME(mux_rtc32k_pmu_p) = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", }; 182 PNAME(mux_wifi_pmu_p) = { "xin24m", "clk_wifi_pmu_src" }; 183 PNAME(mux_uart0_pmu_p) = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" }; 184 PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; 185 PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; 186 PNAME(mux_gpu_p) = { "clk_gpu_div", "clk_gpu_np5" }; 187 188 static struct rockchip_pll_clock px30_pll_clks[] __initdata = { 189 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 190 0, PX30_PLL_CON(0), 191 PX30_MODE_CON, 0, 0, 0, px30_pll_rates), 192 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 193 0, PX30_PLL_CON(8), 194 PX30_MODE_CON, 4, 1, 0, NULL), 195 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 196 0, PX30_PLL_CON(16), 197 PX30_MODE_CON, 2, 2, 0, px30_pll_rates), 198 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p, 199 0, PX30_PLL_CON(24), 200 PX30_MODE_CON, 6, 4, 0, px30_pll_rates), 201 }; 202 203 static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = { 204 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0), 205 PX30_PMU_MODE, 0, 3, 0, px30_pll_rates), 206 }; 207 208 #define MFLAGS CLK_MUX_HIWORD_MASK 209 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 210 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 211 212 static struct rockchip_clk_branch px30_pdm_fracmux __initdata = 213 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT, 214 PX30_CLKSEL_CON(26), 15, 1, MFLAGS); 215 216 static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata = 217 MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT, 218 PX30_CLKSEL_CON(28), 10, 2, MFLAGS); 219 220 static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata = 221 MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT, 222 PX30_CLKSEL_CON(58), 10, 2, MFLAGS); 223 224 static struct rockchip_clk_branch px30_i2s1_fracmux __initdata = 225 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT, 226 PX30_CLKSEL_CON(30), 10, 2, MFLAGS); 227 228 static struct rockchip_clk_branch px30_i2s2_fracmux __initdata = 229 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT, 230 PX30_CLKSEL_CON(32), 10, 2, MFLAGS); 231 232 static struct rockchip_clk_branch px30_uart1_fracmux __initdata = 233 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT, 234 PX30_CLKSEL_CON(35), 14, 2, MFLAGS); 235 236 static struct rockchip_clk_branch px30_uart2_fracmux __initdata = 237 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT, 238 PX30_CLKSEL_CON(38), 14, 2, MFLAGS); 239 240 static struct rockchip_clk_branch px30_uart3_fracmux __initdata = 241 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT, 242 PX30_CLKSEL_CON(41), 14, 2, MFLAGS); 243 244 static struct rockchip_clk_branch px30_uart4_fracmux __initdata = 245 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT, 246 PX30_CLKSEL_CON(44), 14, 2, MFLAGS); 247 248 static struct rockchip_clk_branch px30_uart5_fracmux __initdata = 249 MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT, 250 PX30_CLKSEL_CON(47), 14, 2, MFLAGS); 251 252 static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata = 253 MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT, 254 PX30_CLKSEL_CON(5), 14, 2, MFLAGS); 255 256 static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata = 257 MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT, 258 PX30_CLKSEL_CON(8), 14, 2, MFLAGS); 259 260 static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata = 261 MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT, 262 PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS); 263 264 static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata = 265 MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT, 266 PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS); 267 268 static struct rockchip_clk_branch px30_clk_branches[] __initdata = { 269 /* 270 * Clock-Architecture Diagram 1 271 */ 272 273 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, 274 PX30_MODE_CON, 8, 2, MFLAGS), 275 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 276 277 /* 278 * Clock-Architecture Diagram 3 279 */ 280 281 /* PD_CORE */ 282 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 283 PX30_CLKGATE_CON(0), 0, GFLAGS), 284 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 285 PX30_CLKGATE_CON(0), 0, GFLAGS), 286 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, 287 PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 288 PX30_CLKGATE_CON(0), 2, GFLAGS), 289 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, 290 PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 291 PX30_CLKGATE_CON(0), 1, GFLAGS), 292 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, 293 PX30_CLKGATE_CON(0), 4, GFLAGS), 294 GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED, 295 PX30_CLKGATE_CON(17), 5, GFLAGS), 296 GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED, 297 PX30_CLKGATE_CON(0), 5, GFLAGS), 298 GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED, 299 PX30_CLKGATE_CON(0), 6, GFLAGS), 300 GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED, 301 PX30_CLKGATE_CON(17), 6, GFLAGS), 302 303 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED, 304 PX30_CLKGATE_CON(0), 3, GFLAGS), 305 GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0, 306 PX30_CLKGATE_CON(17), 4, GFLAGS), 307 308 /* PD_GPU */ 309 COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0, 310 PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 311 PX30_CLKGATE_CON(0), 8, GFLAGS), 312 COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", 0, 313 PX30_CLKSEL_CON(1), 0, 4, DFLAGS, 314 PX30_CLKGATE_CON(0), 12, GFLAGS), 315 COMPOSITE_NOMUX_HALFDIV(0, "clk_gpu_np5", "clk_gpu_src", 0, 316 PX30_CLKSEL_CON(1), 8, 4, DFLAGS, 317 PX30_CLKGATE_CON(0), 9, GFLAGS), 318 COMPOSITE_NODIV(SCLK_GPU, "clk_gpu", mux_gpu_p, CLK_SET_RATE_PARENT, 319 PX30_CLKSEL_CON(1), 15, 1, MFLAGS, 320 PX30_CLKGATE_CON(0), 10, GFLAGS), 321 COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED, 322 PX30_CLKSEL_CON(1), 13, 2, DFLAGS, 323 PX30_CLKGATE_CON(17), 10, GFLAGS), 324 GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED, 325 PX30_CLKGATE_CON(0), 11, GFLAGS), 326 GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED, 327 PX30_CLKGATE_CON(17), 8, GFLAGS), 328 GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED, 329 PX30_CLKGATE_CON(17), 9, GFLAGS), 330 331 /* 332 * Clock-Architecture Diagram 4 333 */ 334 335 /* PD_DDR */ 336 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 337 PX30_CLKGATE_CON(0), 7, GFLAGS), 338 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 339 PX30_CLKGATE_CON(0), 13, GFLAGS), 340 COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED, 341 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), 342 COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 343 PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS), 344 FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, 345 PX30_CLKGATE_CON(0), 14, GFLAGS), 346 FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, 347 PX30_CLKGATE_CON(1), 0, GFLAGS), 348 COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED, 349 PX30_CLKSEL_CON(2), 4, 1, MFLAGS, 350 PX30_CLKGATE_CON(1), 13, GFLAGS), 351 GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 352 PX30_CLKGATE_CON(1), 15, GFLAGS), 353 GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 354 PX30_CLKGATE_CON(1), 8, GFLAGS), 355 GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 356 PX30_CLKGATE_CON(1), 5, GFLAGS), 357 GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 358 PX30_CLKGATE_CON(1), 6, GFLAGS), 359 GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 360 PX30_CLKGATE_CON(1), 6, GFLAGS), 361 GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED, 362 PX30_CLKGATE_CON(1), 11, GFLAGS), 363 364 GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED, 365 PX30_CLKGATE_CON(0), 15, GFLAGS), 366 367 COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED, 368 PX30_CLKSEL_CON(2), 8, 5, DFLAGS, 369 PX30_CLKGATE_CON(1), 1, GFLAGS), 370 GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED, 371 PX30_CLKGATE_CON(1), 10, GFLAGS), 372 GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED, 373 PX30_CLKGATE_CON(1), 7, GFLAGS), 374 GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED, 375 PX30_CLKGATE_CON(1), 9, GFLAGS), 376 GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED, 377 PX30_CLKGATE_CON(1), 12, GFLAGS), 378 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, 379 PX30_CLKGATE_CON(1), 14, GFLAGS), 380 GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED, 381 PX30_CLKGATE_CON(1), 3, GFLAGS), 382 383 /* 384 * Clock-Architecture Diagram 5 385 */ 386 387 /* PD_VI */ 388 COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0, 389 PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS, 390 PX30_CLKGATE_CON(4), 8, GFLAGS), 391 COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0, 392 PX30_CLKSEL_CON(11), 8, 4, DFLAGS, 393 PX30_CLKGATE_CON(4), 12, GFLAGS), 394 COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0, 395 PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, 396 PX30_CLKGATE_CON(4), 9, GFLAGS), 397 COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0, 398 PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS, 399 PX30_CLKGATE_CON(4), 11, GFLAGS), 400 GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0, 401 PX30_CLKGATE_CON(4), 13, GFLAGS), 402 GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0, 403 PX30_CLKGATE_CON(4), 14, GFLAGS), 404 405 /* 406 * Clock-Architecture Diagram 6 407 */ 408 409 /* PD_VO */ 410 COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0, 411 PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS, 412 PX30_CLKGATE_CON(2), 0, GFLAGS), 413 COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0, 414 PX30_CLKSEL_CON(3), 8, 4, DFLAGS, 415 PX30_CLKGATE_CON(2), 12, GFLAGS), 416 COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0, 417 PX30_CLKSEL_CON(3), 12, 4, DFLAGS, 418 PX30_CLKGATE_CON(2), 13, GFLAGS), 419 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0, 420 PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS, 421 PX30_CLKGATE_CON(2), 1, GFLAGS), 422 423 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0, 424 PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS, 425 PX30_CLKGATE_CON(2), 5, GFLAGS), 426 COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 427 PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS, 428 PX30_CLKGATE_CON(2), 2, GFLAGS), 429 COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT, 430 PX30_CLKSEL_CON(6), 0, 431 PX30_CLKGATE_CON(2), 3, GFLAGS, 432 &px30_dclk_vopb_fracmux), 433 GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT, 434 PX30_CLKGATE_CON(2), 4, GFLAGS), 435 COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0, 436 PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS, 437 PX30_CLKGATE_CON(2), 6, GFLAGS), 438 COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT, 439 PX30_CLKSEL_CON(9), 0, 440 PX30_CLKGATE_CON(2), 7, GFLAGS, 441 &px30_dclk_vopl_fracmux), 442 GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT, 443 PX30_CLKGATE_CON(2), 8, GFLAGS), 444 445 /* PD_VPU */ 446 COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0, 447 PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS, 448 PX30_CLKGATE_CON(4), 0, GFLAGS), 449 COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 450 PX30_CLKSEL_CON(10), 8, 4, DFLAGS, 451 PX30_CLKGATE_CON(4), 2, GFLAGS), 452 COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0, 453 PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS, 454 PX30_CLKGATE_CON(4), 1, GFLAGS), 455 456 /* 457 * Clock-Architecture Diagram 7 458 */ 459 460 COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0, 461 PX30_CLKSEL_CON(14), 15, 1, MFLAGS, 462 PX30_CLKGATE_CON(5), 7, GFLAGS), 463 COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED, 464 PX30_CLKSEL_CON(14), 0, 5, DFLAGS, 465 PX30_CLKGATE_CON(5), 8, GFLAGS), 466 DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED, 467 PX30_CLKSEL_CON(14), 8, 5, DFLAGS), 468 469 /* PD_MMC_NAND */ 470 GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0, 471 PX30_CLKGATE_CON(6), 0, GFLAGS), 472 COMPOSITE(SCLK_NANDC, "clk_nandc", mux_gpll_cpll_npll_p, 0, 473 PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS, 474 PX30_CLKGATE_CON(5), 13, GFLAGS), 475 476 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_gpll_cpll_npll_xin24m_p, 0, 477 PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS, 478 PX30_CLKGATE_CON(6), 3, GFLAGS), 479 480 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_gpll_cpll_npll_xin24m_p, 0, 481 PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS, 482 PX30_CLKGATE_CON(6), 6, GFLAGS), 483 484 COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0, 485 PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS, 486 PX30_CLKGATE_CON(6), 7, GFLAGS), 487 488 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", 489 PX30_SDMMC_CON0, 1), 490 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", 491 PX30_SDMMC_CON1, 1), 492 493 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", 494 PX30_SDIO_CON0, 1), 495 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", 496 PX30_SDIO_CON1, 1), 497 498 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", 499 PX30_EMMC_CON0, 1), 500 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", 501 PX30_EMMC_CON1, 1), 502 503 /* PD_SDCARD */ 504 GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0, 505 PX30_CLKGATE_CON(6), 12, GFLAGS), 506 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_npll_xin24m_p, 0, 507 PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS, 508 PX30_CLKGATE_CON(6), 15, GFLAGS), 509 510 /* PD_USB */ 511 GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0, 512 PX30_CLKGATE_CON(7), 2, GFLAGS), 513 GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0, 514 PX30_CLKGATE_CON(7), 3, GFLAGS), 515 516 /* PD_GMAC */ 517 COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0, 518 PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS, 519 PX30_CLKGATE_CON(7), 11, GFLAGS), 520 MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p, CLK_SET_RATE_PARENT, 521 PX30_CLKSEL_CON(23), 6, 1, MFLAGS), 522 GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0, 523 PX30_CLKGATE_CON(7), 15, GFLAGS), 524 GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0, 525 PX30_CLKGATE_CON(7), 13, GFLAGS), 526 FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2), 527 FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20), 528 MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT, 529 PX30_CLKSEL_CON(23), 7, 1, MFLAGS), 530 531 GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0, 532 PX30_CLKGATE_CON(7), 10, GFLAGS), 533 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0, 534 PX30_CLKSEL_CON(23), 0, 4, DFLAGS, 535 PX30_CLKGATE_CON(7), 12, GFLAGS), 536 537 COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0, 538 PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS, 539 PX30_CLKGATE_CON(8), 5, GFLAGS), 540 541 /* 542 * Clock-Architecture Diagram 8 543 */ 544 545 /* PD_BUS */ 546 COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED, 547 PX30_CLKSEL_CON(23), 15, 1, MFLAGS, 548 PX30_CLKGATE_CON(8), 6, GFLAGS), 549 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED, 550 PX30_CLKSEL_CON(24), 0, 5, DFLAGS, 551 PX30_CLKGATE_CON(8), 8, GFLAGS), 552 COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED, 553 PX30_CLKSEL_CON(23), 8, 5, DFLAGS, 554 PX30_CLKGATE_CON(8), 7, GFLAGS), 555 COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED, 556 PX30_CLKSEL_CON(24), 8, 2, DFLAGS, 557 PX30_CLKGATE_CON(8), 9, GFLAGS), 558 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, 559 PX30_CLKGATE_CON(8), 10, GFLAGS), 560 561 COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0, 562 PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS, 563 PX30_CLKGATE_CON(9), 9, GFLAGS), 564 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT, 565 PX30_CLKSEL_CON(27), 0, 566 PX30_CLKGATE_CON(9), 10, GFLAGS, 567 &px30_pdm_fracmux), 568 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT, 569 PX30_CLKGATE_CON(9), 11, GFLAGS), 570 571 COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0, 572 PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS, 573 PX30_CLKGATE_CON(9), 12, GFLAGS), 574 COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT, 575 PX30_CLKSEL_CON(29), 0, 576 PX30_CLKGATE_CON(9), 13, GFLAGS, 577 &px30_i2s0_tx_fracmux), 578 COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT, 579 PX30_CLKSEL_CON(28), 12, 1, MFLAGS, 580 PX30_CLKGATE_CON(9), 14, GFLAGS), 581 COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0, 582 PX30_CLKSEL_CON(28), 14, 2, MFLAGS, 583 PX30_CLKGATE_CON(9), 15, GFLAGS), 584 GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT, 585 PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK), 586 587 COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0, 588 PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS, 589 PX30_CLKGATE_CON(17), 0, GFLAGS), 590 COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT, 591 PX30_CLKSEL_CON(59), 0, 592 PX30_CLKGATE_CON(17), 1, GFLAGS, 593 &px30_i2s0_rx_fracmux), 594 COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT, 595 PX30_CLKSEL_CON(58), 12, 1, MFLAGS, 596 PX30_CLKGATE_CON(17), 2, GFLAGS), 597 COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0, 598 PX30_CLKSEL_CON(58), 14, 2, MFLAGS, 599 PX30_CLKGATE_CON(17), 3, GFLAGS), 600 GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT, 601 PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK), 602 603 COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0, 604 PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS, 605 PX30_CLKGATE_CON(10), 0, GFLAGS), 606 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT, 607 PX30_CLKSEL_CON(31), 0, 608 PX30_CLKGATE_CON(10), 1, GFLAGS, 609 &px30_i2s1_fracmux), 610 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, 611 PX30_CLKGATE_CON(10), 2, GFLAGS), 612 COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0, 613 PX30_CLKSEL_CON(30), 15, 1, MFLAGS, 614 PX30_CLKGATE_CON(10), 3, GFLAGS), 615 GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT, 616 PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK), 617 618 COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0, 619 PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS, 620 PX30_CLKGATE_CON(10), 4, GFLAGS), 621 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT, 622 PX30_CLKSEL_CON(33), 0, 623 PX30_CLKGATE_CON(10), 5, GFLAGS, 624 &px30_i2s2_fracmux), 625 GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, 626 PX30_CLKGATE_CON(10), 6, GFLAGS), 627 COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0, 628 PX30_CLKSEL_CON(32), 15, 1, MFLAGS, 629 PX30_CLKGATE_CON(10), 7, GFLAGS), 630 GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT, 631 PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK), 632 633 COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT, 634 PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS, 635 PX30_CLKGATE_CON(10), 12, GFLAGS), 636 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0, 637 PX30_CLKSEL_CON(35), 0, 5, DFLAGS, 638 PX30_CLKGATE_CON(10), 13, GFLAGS), 639 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 640 PX30_CLKSEL_CON(36), 0, 641 PX30_CLKGATE_CON(10), 14, GFLAGS, 642 &px30_uart1_fracmux), 643 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT, 644 PX30_CLKGATE_CON(10), 15, GFLAGS), 645 646 COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0, 647 PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS, 648 PX30_CLKGATE_CON(11), 0, GFLAGS), 649 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0, 650 PX30_CLKSEL_CON(38), 0, 5, DFLAGS, 651 PX30_CLKGATE_CON(11), 1, GFLAGS), 652 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 653 PX30_CLKSEL_CON(39), 0, 654 PX30_CLKGATE_CON(11), 2, GFLAGS, 655 &px30_uart2_fracmux), 656 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT, 657 PX30_CLKGATE_CON(11), 3, GFLAGS), 658 659 COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0, 660 PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS, 661 PX30_CLKGATE_CON(11), 4, GFLAGS), 662 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0, 663 PX30_CLKSEL_CON(41), 0, 5, DFLAGS, 664 PX30_CLKGATE_CON(11), 5, GFLAGS), 665 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 666 PX30_CLKSEL_CON(42), 0, 667 PX30_CLKGATE_CON(11), 6, GFLAGS, 668 &px30_uart3_fracmux), 669 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT, 670 PX30_CLKGATE_CON(11), 7, GFLAGS), 671 672 COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0, 673 PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS, 674 PX30_CLKGATE_CON(11), 8, GFLAGS), 675 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0, 676 PX30_CLKSEL_CON(44), 0, 5, DFLAGS, 677 PX30_CLKGATE_CON(11), 9, GFLAGS), 678 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 679 PX30_CLKSEL_CON(45), 0, 680 PX30_CLKGATE_CON(11), 10, GFLAGS, 681 &px30_uart4_fracmux), 682 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT, 683 PX30_CLKGATE_CON(11), 11, GFLAGS), 684 685 COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0, 686 PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS, 687 PX30_CLKGATE_CON(11), 12, GFLAGS), 688 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0, 689 PX30_CLKSEL_CON(47), 0, 5, DFLAGS, 690 PX30_CLKGATE_CON(11), 13, GFLAGS), 691 COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 692 PX30_CLKSEL_CON(48), 0, 693 PX30_CLKGATE_CON(11), 14, GFLAGS, 694 &px30_uart5_fracmux), 695 GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT, 696 PX30_CLKGATE_CON(11), 15, GFLAGS), 697 698 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0, 699 PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS, 700 PX30_CLKGATE_CON(12), 0, GFLAGS), 701 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, 702 PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS, 703 PX30_CLKGATE_CON(12), 1, GFLAGS), 704 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, 705 PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS, 706 PX30_CLKGATE_CON(12), 2, GFLAGS), 707 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, 708 PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS, 709 PX30_CLKGATE_CON(12), 3, GFLAGS), 710 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, 711 PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS, 712 PX30_CLKGATE_CON(12), 5, GFLAGS), 713 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0, 714 PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS, 715 PX30_CLKGATE_CON(12), 6, GFLAGS), 716 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, 717 PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS, 718 PX30_CLKGATE_CON(12), 7, GFLAGS), 719 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0, 720 PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS, 721 PX30_CLKGATE_CON(12), 8, GFLAGS), 722 723 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, 724 PX30_CLKGATE_CON(13), 0, GFLAGS), 725 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, 726 PX30_CLKGATE_CON(13), 1, GFLAGS), 727 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, 728 PX30_CLKGATE_CON(13), 2, GFLAGS), 729 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, 730 PX30_CLKGATE_CON(13), 3, GFLAGS), 731 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, 732 PX30_CLKGATE_CON(13), 4, GFLAGS), 733 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, 734 PX30_CLKGATE_CON(13), 5, GFLAGS), 735 736 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0, 737 PX30_CLKSEL_CON(54), 0, 11, DFLAGS, 738 PX30_CLKGATE_CON(12), 9, GFLAGS), 739 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0, 740 PX30_CLKSEL_CON(55), 0, 11, DFLAGS, 741 PX30_CLKGATE_CON(12), 10, GFLAGS), 742 COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0, 743 PX30_CLKSEL_CON(56), 0, 3, DFLAGS, 744 PX30_CLKGATE_CON(12), 11, GFLAGS), 745 COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0, 746 PX30_CLKSEL_CON(56), 4, 2, DFLAGS, 747 PX30_CLKGATE_CON(13), 6, GFLAGS), 748 749 GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED, 750 PX30_CLKGATE_CON(12), 12, GFLAGS), 751 752 /* PD_CRYPTO */ 753 GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0, 754 PX30_CLKGATE_CON(8), 12, GFLAGS), 755 GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0, 756 PX30_CLKGATE_CON(8), 13, GFLAGS), 757 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0, 758 PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS, 759 PX30_CLKGATE_CON(8), 14, GFLAGS), 760 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0, 761 PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS, 762 PX30_CLKGATE_CON(8), 15, GFLAGS), 763 764 /* 765 * Clock-Architecture Diagram 9 766 */ 767 768 /* PD_BUS_TOP */ 769 GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS), 770 GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS), 771 GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS), 772 GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS), 773 GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS), 774 GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS), 775 GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 6, GFLAGS), 776 GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS), 777 778 /* PD_VI */ 779 GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 15, GFLAGS), 780 GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS), 781 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS), 782 GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 0, GFLAGS), 783 GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS), 784 GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS), 785 786 /* PD_VO */ 787 GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 0, GFLAGS), 788 GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS), 789 GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS), 790 GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS), 791 792 GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 1, GFLAGS), 793 GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS), 794 GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS), 795 GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS), 796 797 GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 2, GFLAGS), 798 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS), 799 800 /* PD_BUS */ 801 GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS), 802 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS), 803 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS), 804 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS), 805 806 GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS), 807 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS), 808 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS), 809 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS), 810 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS), 811 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS), 812 813 GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS), 814 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS), 815 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS), 816 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS), 817 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS), 818 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS), 819 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS), 820 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS), 821 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS), 822 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS), 823 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS), 824 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS), 825 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS), 826 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS), 827 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS), 828 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS), 829 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS), 830 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS), 831 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS), 832 GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS), 833 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS), 834 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS), 835 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS), 836 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS), 837 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS), 838 GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS), 839 840 /* PD_VPU */ 841 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS), 842 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS), 843 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS), 844 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS), 845 846 /* PD_CRYPTO */ 847 GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS), 848 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS), 849 GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS), 850 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS), 851 852 /* PD_SDCARD */ 853 GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS), 854 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS), 855 856 /* PD_PERI */ 857 GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS), 858 859 /* PD_MMC_NAND */ 860 GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS), 861 GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS), 862 GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS), 863 GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS), 864 GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS), 865 866 /* PD_USB */ 867 GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS), 868 GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS), 869 GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS), 870 GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS), 871 872 /* PD_GMAC */ 873 GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED, 874 PX30_CLKGATE_CON(8), 0, GFLAGS), 875 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0, 876 PX30_CLKGATE_CON(8), 2, GFLAGS), 877 GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED, 878 PX30_CLKGATE_CON(8), 1, GFLAGS), 879 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0, 880 PX30_CLKGATE_CON(8), 3, GFLAGS), 881 }; 882 883 static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = { 884 /* 885 * Clock-Architecture Diagram 2 886 */ 887 888 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED, 889 PX30_PMU_CLKSEL_CON(1), 0, 890 PX30_PMU_CLKGATE_CON(0), 13, GFLAGS, 891 &px30_rtc32k_pmu_fracmux), 892 893 COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED, 894 PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS, 895 PX30_PMU_CLKGATE_CON(0), 12, GFLAGS), 896 897 COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0, 898 PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS, 899 PX30_PMU_CLKGATE_CON(0), 14, GFLAGS), 900 COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT, 901 PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS, 902 PX30_PMU_CLKGATE_CON(0), 15, GFLAGS), 903 904 COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0, 905 PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS, 906 PX30_PMU_CLKGATE_CON(1), 0, GFLAGS), 907 COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0, 908 PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS, 909 PX30_PMU_CLKGATE_CON(1), 1, GFLAGS), 910 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT, 911 PX30_PMU_CLKSEL_CON(5), 0, 912 PX30_PMU_CLKGATE_CON(1), 2, GFLAGS, 913 &px30_uart0_pmu_fracmux), 914 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, 915 PX30_PMU_CLKGATE_CON(1), 3, GFLAGS), 916 917 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, 918 PX30_PMU_CLKGATE_CON(1), 4, GFLAGS), 919 920 COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0, 921 PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, 922 PX30_PMU_CLKGATE_CON(0), 0, GFLAGS), 923 924 COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0, 925 PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS, 926 PX30_PMU_CLKGATE_CON(1), 8, GFLAGS), 927 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT, 928 PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS, 929 PX30_PMU_CLKGATE_CON(1), 9, GFLAGS), 930 COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT, 931 PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS, 932 PX30_PMU_CLKGATE_CON(1), 10, GFLAGS), 933 934 /* 935 * Clock-Architecture Diagram 9 936 */ 937 938 /* PD_PMU */ 939 GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS), 940 GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS), 941 GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS), 942 GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS), 943 GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS), 944 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS), 945 GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS), 946 GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS), 947 }; 948 949 static const char *const px30_pmucru_critical_clocks[] __initconst = { 950 "aclk_bus_pre", 951 "pclk_bus_pre", 952 "hclk_bus_pre", 953 "aclk_peri_pre", 954 "hclk_peri_pre", 955 "aclk_gpu_niu", 956 "pclk_top_pre", 957 "pclk_pmu_pre", 958 "hclk_usb_niu", 959 "pll_npll", 960 "usb480m", 961 "clk_uart2", 962 "pclk_uart2", 963 }; 964 965 static void __init px30_clk_init(struct device_node *np) 966 { 967 struct rockchip_clk_provider *ctx; 968 void __iomem *reg_base; 969 struct clk *clk; 970 971 reg_base = of_iomap(np, 0); 972 if (!reg_base) { 973 pr_err("%s: could not map cru region\n", __func__); 974 return; 975 } 976 977 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 978 if (IS_ERR(ctx)) { 979 pr_err("%s: rockchip clk init failed\n", __func__); 980 iounmap(reg_base); 981 return; 982 } 983 984 /* aclk_dmac is controlled by sgrf_soc_con1[11]. */ 985 clk = clk_register_fixed_factor(NULL, "aclk_dmac", "aclk_bus_pre", 0, 1, 1); 986 if (IS_ERR(clk)) 987 pr_warn("%s: could not register clock aclk_dmac: %ld\n", 988 __func__, PTR_ERR(clk)); 989 else 990 rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC); 991 992 rockchip_clk_register_plls(ctx, px30_pll_clks, 993 ARRAY_SIZE(px30_pll_clks), 994 PX30_GRF_SOC_STATUS0); 995 rockchip_clk_register_branches(ctx, px30_clk_branches, 996 ARRAY_SIZE(px30_clk_branches)); 997 998 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 999 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 1000 &px30_cpuclk_data, px30_cpuclk_rates, 1001 ARRAY_SIZE(px30_cpuclk_rates)); 1002 1003 rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0), 1004 ROCKCHIP_SOFTRST_HIWORD_MASK); 1005 1006 rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL); 1007 1008 rockchip_clk_of_add_provider(np, ctx); 1009 } 1010 CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init); 1011 1012 static void __init px30_pmu_clk_init(struct device_node *np) 1013 { 1014 struct rockchip_clk_provider *ctx; 1015 void __iomem *reg_base; 1016 1017 reg_base = of_iomap(np, 0); 1018 if (!reg_base) { 1019 pr_err("%s: could not map cru pmu region\n", __func__); 1020 return; 1021 } 1022 1023 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS); 1024 if (IS_ERR(ctx)) { 1025 pr_err("%s: rockchip pmu clk init failed\n", __func__); 1026 return; 1027 } 1028 1029 rockchip_clk_register_plls(ctx, px30_pmu_pll_clks, 1030 ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0); 1031 1032 rockchip_clk_register_branches(ctx, px30_clk_pmu_branches, 1033 ARRAY_SIZE(px30_clk_pmu_branches)); 1034 1035 rockchip_clk_protect_critical(px30_pmucru_critical_clocks, 1036 ARRAY_SIZE(px30_pmucru_critical_clocks)); 1037 1038 rockchip_clk_of_add_provider(np, ctx); 1039 } 1040 CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init); 1041