1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 6 * Author: Xing Zheng <zhengxing@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <asm/div64.h> 20 #include <linux/slab.h> 21 #include <linux/io.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/regmap.h> 25 #include <linux/clk.h> 26 #include "clk.h" 27 28 #define PLL_MODE_MASK 0x3 29 #define PLL_MODE_SLOW 0x0 30 #define PLL_MODE_NORM 0x1 31 #define PLL_MODE_DEEP 0x2 32 33 struct rockchip_clk_pll { 34 struct clk_hw hw; 35 36 struct clk_mux pll_mux; 37 const struct clk_ops *pll_mux_ops; 38 39 struct notifier_block clk_nb; 40 41 void __iomem *reg_base; 42 int lock_offset; 43 unsigned int lock_shift; 44 enum rockchip_pll_type type; 45 u8 flags; 46 const struct rockchip_pll_rate_table *rate_table; 47 unsigned int rate_count; 48 spinlock_t *lock; 49 }; 50 51 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw) 52 #define to_rockchip_clk_pll_nb(nb) \ 53 container_of(nb, struct rockchip_clk_pll, clk_nb) 54 55 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings( 56 struct rockchip_clk_pll *pll, unsigned long rate) 57 { 58 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 59 int i; 60 61 for (i = 0; i < pll->rate_count; i++) { 62 if (rate == rate_table[i].rate) 63 return &rate_table[i]; 64 } 65 66 return NULL; 67 } 68 69 static long rockchip_pll_round_rate(struct clk_hw *hw, 70 unsigned long drate, unsigned long *prate) 71 { 72 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 73 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 74 int i; 75 76 /* Assumming rate_table is in descending order */ 77 for (i = 0; i < pll->rate_count; i++) { 78 if (drate >= rate_table[i].rate) 79 return rate_table[i].rate; 80 } 81 82 /* return minimum supported value */ 83 return rate_table[i - 1].rate; 84 } 85 86 /* 87 * Wait for the pll to reach the locked state. 88 * The calling set_rate function is responsible for making sure the 89 * grf regmap is available. 90 */ 91 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) 92 { 93 struct regmap *grf = rockchip_clk_get_grf(); 94 unsigned int val; 95 int delay = 24000000, ret; 96 97 while (delay > 0) { 98 ret = regmap_read(grf, pll->lock_offset, &val); 99 if (ret) { 100 pr_err("%s: failed to read pll lock status: %d\n", 101 __func__, ret); 102 return ret; 103 } 104 105 if (val & BIT(pll->lock_shift)) 106 return 0; 107 delay--; 108 } 109 110 pr_err("%s: timeout waiting for pll to lock\n", __func__); 111 return -ETIMEDOUT; 112 } 113 114 /** 115 * PLL used in RK3036 116 */ 117 118 #define RK3036_PLLCON(i) (i * 0x4) 119 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 120 #define RK3036_PLLCON0_FBDIV_SHIFT 0 121 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 122 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 123 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 124 #define RK3036_PLLCON1_REFDIV_SHIFT 0 125 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 126 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 127 #define RK3036_PLLCON1_DSMPD_MASK 0x1 128 #define RK3036_PLLCON1_DSMPD_SHIFT 12 129 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 130 #define RK3036_PLLCON2_FRAC_SHIFT 0 131 132 #define RK3036_PLLCON1_PWRDOWN (1 << 13) 133 134 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, 135 struct rockchip_pll_rate_table *rate) 136 { 137 u32 pllcon; 138 139 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); 140 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) 141 & RK3036_PLLCON0_FBDIV_MASK); 142 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) 143 & RK3036_PLLCON0_POSTDIV1_MASK); 144 145 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); 146 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) 147 & RK3036_PLLCON1_REFDIV_MASK); 148 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) 149 & RK3036_PLLCON1_POSTDIV2_MASK); 150 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) 151 & RK3036_PLLCON1_DSMPD_MASK); 152 153 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 154 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) 155 & RK3036_PLLCON2_FRAC_MASK); 156 } 157 158 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, 159 unsigned long prate) 160 { 161 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 162 struct rockchip_pll_rate_table cur; 163 u64 rate64 = prate; 164 165 rockchip_rk3036_pll_get_params(pll, &cur); 166 167 rate64 *= cur.fbdiv; 168 do_div(rate64, cur.refdiv); 169 170 if (cur.dsmpd == 0) { 171 /* fractional mode */ 172 u64 frac_rate64 = prate * cur.frac; 173 174 do_div(frac_rate64, cur.refdiv); 175 rate64 += frac_rate64 >> 24; 176 } 177 178 do_div(rate64, cur.postdiv1); 179 do_div(rate64, cur.postdiv2); 180 181 return (unsigned long)rate64; 182 } 183 184 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, 185 const struct rockchip_pll_rate_table *rate) 186 { 187 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 188 struct clk_mux *pll_mux = &pll->pll_mux; 189 struct rockchip_pll_rate_table cur; 190 u32 pllcon; 191 int rate_change_remuxed = 0; 192 int cur_parent; 193 int ret; 194 195 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 196 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, 197 rate->postdiv2, rate->dsmpd, rate->frac); 198 199 rockchip_rk3036_pll_get_params(pll, &cur); 200 cur.rate = 0; 201 202 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 203 if (cur_parent == PLL_MODE_NORM) { 204 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 205 rate_change_remuxed = 1; 206 } 207 208 /* update pll values */ 209 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, 210 RK3036_PLLCON0_FBDIV_SHIFT) | 211 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, 212 RK3036_PLLCON0_POSTDIV1_SHIFT), 213 pll->reg_base + RK3036_PLLCON(0)); 214 215 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, 216 RK3036_PLLCON1_REFDIV_SHIFT) | 217 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, 218 RK3036_PLLCON1_POSTDIV2_SHIFT) | 219 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, 220 RK3036_PLLCON1_DSMPD_SHIFT), 221 pll->reg_base + RK3036_PLLCON(1)); 222 223 /* GPLL CON2 is not HIWORD_MASK */ 224 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 225 pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT); 226 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; 227 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); 228 229 /* wait for the pll to lock */ 230 ret = rockchip_pll_wait_lock(pll); 231 if (ret) { 232 pr_warn("%s: pll update unsucessful, trying to restore old params\n", 233 __func__); 234 rockchip_rk3036_pll_set_params(pll, &cur); 235 } 236 237 if (rate_change_remuxed) 238 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 239 240 return ret; 241 } 242 243 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, 244 unsigned long prate) 245 { 246 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 247 const struct rockchip_pll_rate_table *rate; 248 unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate); 249 struct regmap *grf = rockchip_clk_get_grf(); 250 251 if (IS_ERR(grf)) { 252 pr_debug("%s: grf regmap not available, aborting rate change\n", 253 __func__); 254 return PTR_ERR(grf); 255 } 256 257 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", 258 __func__, __clk_get_name(hw->clk), old_rate, drate, prate); 259 260 /* Get required rate settings from table */ 261 rate = rockchip_get_pll_settings(pll, drate); 262 if (!rate) { 263 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 264 drate, __clk_get_name(hw->clk)); 265 return -EINVAL; 266 } 267 268 return rockchip_rk3036_pll_set_params(pll, rate); 269 } 270 271 static int rockchip_rk3036_pll_enable(struct clk_hw *hw) 272 { 273 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 274 275 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), 276 pll->reg_base + RK3036_PLLCON(1)); 277 278 return 0; 279 } 280 281 static void rockchip_rk3036_pll_disable(struct clk_hw *hw) 282 { 283 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 284 285 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, 286 RK3036_PLLCON1_PWRDOWN, 0), 287 pll->reg_base + RK3036_PLLCON(1)); 288 } 289 290 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw) 291 { 292 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 293 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); 294 295 return !(pllcon & RK3036_PLLCON1_PWRDOWN); 296 } 297 298 static void rockchip_rk3036_pll_init(struct clk_hw *hw) 299 { 300 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 301 const struct rockchip_pll_rate_table *rate; 302 struct rockchip_pll_rate_table cur; 303 unsigned long drate; 304 305 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 306 return; 307 308 drate = clk_hw_get_rate(hw); 309 rate = rockchip_get_pll_settings(pll, drate); 310 311 /* when no rate setting for the current rate, rely on clk_set_rate */ 312 if (!rate) 313 return; 314 315 rockchip_rk3036_pll_get_params(pll, &cur); 316 317 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), 318 drate); 319 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 320 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, 321 cur.dsmpd, cur.frac); 322 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 323 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, 324 rate->dsmpd, rate->frac); 325 326 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 327 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 328 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) { 329 struct clk *parent = clk_get_parent(hw->clk); 330 331 if (!parent) { 332 pr_warn("%s: parent of %s not available\n", 333 __func__, __clk_get_name(hw->clk)); 334 return; 335 } 336 337 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 338 __func__, __clk_get_name(hw->clk)); 339 rockchip_rk3036_pll_set_params(pll, rate); 340 } 341 } 342 343 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { 344 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 345 .enable = rockchip_rk3036_pll_enable, 346 .disable = rockchip_rk3036_pll_disable, 347 .is_enabled = rockchip_rk3036_pll_is_enabled, 348 }; 349 350 static const struct clk_ops rockchip_rk3036_pll_clk_ops = { 351 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 352 .round_rate = rockchip_pll_round_rate, 353 .set_rate = rockchip_rk3036_pll_set_rate, 354 .enable = rockchip_rk3036_pll_enable, 355 .disable = rockchip_rk3036_pll_disable, 356 .is_enabled = rockchip_rk3036_pll_is_enabled, 357 .init = rockchip_rk3036_pll_init, 358 }; 359 360 /** 361 * PLL used in RK3066, RK3188 and RK3288 362 */ 363 364 #define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1) 365 366 #define RK3066_PLLCON(i) (i * 0x4) 367 #define RK3066_PLLCON0_OD_MASK 0xf 368 #define RK3066_PLLCON0_OD_SHIFT 0 369 #define RK3066_PLLCON0_NR_MASK 0x3f 370 #define RK3066_PLLCON0_NR_SHIFT 8 371 #define RK3066_PLLCON1_NF_MASK 0x1fff 372 #define RK3066_PLLCON1_NF_SHIFT 0 373 #define RK3066_PLLCON2_NB_MASK 0xfff 374 #define RK3066_PLLCON2_NB_SHIFT 0 375 #define RK3066_PLLCON3_RESET (1 << 5) 376 #define RK3066_PLLCON3_PWRDOWN (1 << 1) 377 #define RK3066_PLLCON3_BYPASS (1 << 0) 378 379 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, 380 struct rockchip_pll_rate_table *rate) 381 { 382 u32 pllcon; 383 384 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); 385 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) 386 & RK3066_PLLCON0_NR_MASK) + 1; 387 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) 388 & RK3066_PLLCON0_OD_MASK) + 1; 389 390 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); 391 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) 392 & RK3066_PLLCON1_NF_MASK) + 1; 393 394 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); 395 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) 396 & RK3066_PLLCON2_NB_MASK) + 1; 397 } 398 399 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, 400 unsigned long prate) 401 { 402 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 403 struct rockchip_pll_rate_table cur; 404 u64 rate64 = prate; 405 u32 pllcon; 406 407 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); 408 if (pllcon & RK3066_PLLCON3_BYPASS) { 409 pr_debug("%s: pll %s is bypassed\n", __func__, 410 clk_hw_get_name(hw)); 411 return prate; 412 } 413 414 rockchip_rk3066_pll_get_params(pll, &cur); 415 416 rate64 *= cur.nf; 417 do_div(rate64, cur.nr); 418 do_div(rate64, cur.no); 419 420 return (unsigned long)rate64; 421 } 422 423 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, 424 const struct rockchip_pll_rate_table *rate) 425 { 426 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 427 struct clk_mux *pll_mux = &pll->pll_mux; 428 struct rockchip_pll_rate_table cur; 429 int rate_change_remuxed = 0; 430 int cur_parent; 431 int ret; 432 433 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", 434 __func__, rate->rate, rate->nr, rate->no, rate->nf); 435 436 rockchip_rk3066_pll_get_params(pll, &cur); 437 cur.rate = 0; 438 439 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 440 if (cur_parent == PLL_MODE_NORM) { 441 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 442 rate_change_remuxed = 1; 443 } 444 445 /* enter reset mode */ 446 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), 447 pll->reg_base + RK3066_PLLCON(3)); 448 449 /* update pll values */ 450 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, 451 RK3066_PLLCON0_NR_SHIFT) | 452 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, 453 RK3066_PLLCON0_OD_SHIFT), 454 pll->reg_base + RK3066_PLLCON(0)); 455 456 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, 457 RK3066_PLLCON1_NF_SHIFT), 458 pll->reg_base + RK3066_PLLCON(1)); 459 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, 460 RK3066_PLLCON2_NB_SHIFT), 461 pll->reg_base + RK3066_PLLCON(2)); 462 463 /* leave reset and wait the reset_delay */ 464 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), 465 pll->reg_base + RK3066_PLLCON(3)); 466 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); 467 468 /* wait for the pll to lock */ 469 ret = rockchip_pll_wait_lock(pll); 470 if (ret) { 471 pr_warn("%s: pll update unsucessful, trying to restore old params\n", 472 __func__); 473 rockchip_rk3066_pll_set_params(pll, &cur); 474 } 475 476 if (rate_change_remuxed) 477 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 478 479 return ret; 480 } 481 482 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, 483 unsigned long prate) 484 { 485 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 486 const struct rockchip_pll_rate_table *rate; 487 unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); 488 struct regmap *grf = rockchip_clk_get_grf(); 489 490 if (IS_ERR(grf)) { 491 pr_debug("%s: grf regmap not available, aborting rate change\n", 492 __func__); 493 return PTR_ERR(grf); 494 } 495 496 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", 497 __func__, clk_hw_get_name(hw), old_rate, drate, prate); 498 499 /* Get required rate settings from table */ 500 rate = rockchip_get_pll_settings(pll, drate); 501 if (!rate) { 502 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 503 drate, clk_hw_get_name(hw)); 504 return -EINVAL; 505 } 506 507 return rockchip_rk3066_pll_set_params(pll, rate); 508 } 509 510 static int rockchip_rk3066_pll_enable(struct clk_hw *hw) 511 { 512 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 513 514 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), 515 pll->reg_base + RK3066_PLLCON(3)); 516 517 return 0; 518 } 519 520 static void rockchip_rk3066_pll_disable(struct clk_hw *hw) 521 { 522 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 523 524 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN, 525 RK3066_PLLCON3_PWRDOWN, 0), 526 pll->reg_base + RK3066_PLLCON(3)); 527 } 528 529 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw) 530 { 531 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 532 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); 533 534 return !(pllcon & RK3066_PLLCON3_PWRDOWN); 535 } 536 537 static void rockchip_rk3066_pll_init(struct clk_hw *hw) 538 { 539 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 540 const struct rockchip_pll_rate_table *rate; 541 struct rockchip_pll_rate_table cur; 542 unsigned long drate; 543 544 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 545 return; 546 547 drate = clk_hw_get_rate(hw); 548 rate = rockchip_get_pll_settings(pll, drate); 549 550 /* when no rate setting for the current rate, rely on clk_set_rate */ 551 if (!rate) 552 return; 553 554 rockchip_rk3066_pll_get_params(pll, &cur); 555 556 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", 557 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, 558 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); 559 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf 560 || rate->nb != cur.nb) { 561 struct regmap *grf = rockchip_clk_get_grf(); 562 563 if (IS_ERR(grf)) 564 return; 565 566 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 567 __func__, clk_hw_get_name(hw)); 568 rockchip_rk3066_pll_set_params(pll, rate); 569 } 570 } 571 572 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { 573 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 574 .enable = rockchip_rk3066_pll_enable, 575 .disable = rockchip_rk3066_pll_disable, 576 .is_enabled = rockchip_rk3066_pll_is_enabled, 577 }; 578 579 static const struct clk_ops rockchip_rk3066_pll_clk_ops = { 580 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 581 .round_rate = rockchip_pll_round_rate, 582 .set_rate = rockchip_rk3066_pll_set_rate, 583 .enable = rockchip_rk3066_pll_enable, 584 .disable = rockchip_rk3066_pll_disable, 585 .is_enabled = rockchip_rk3066_pll_is_enabled, 586 .init = rockchip_rk3066_pll_init, 587 }; 588 589 /* 590 * Common registering of pll clocks 591 */ 592 593 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, 594 const char *name, const char *const *parent_names, 595 u8 num_parents, void __iomem *base, int con_offset, 596 int grf_lock_offset, int lock_shift, int mode_offset, 597 int mode_shift, struct rockchip_pll_rate_table *rate_table, 598 u8 clk_pll_flags, spinlock_t *lock) 599 { 600 const char *pll_parents[3]; 601 struct clk_init_data init; 602 struct rockchip_clk_pll *pll; 603 struct clk_mux *pll_mux; 604 struct clk *pll_clk, *mux_clk; 605 char pll_name[20]; 606 607 if (num_parents != 2) { 608 pr_err("%s: needs two parent clocks\n", __func__); 609 return ERR_PTR(-EINVAL); 610 } 611 612 /* name the actual pll */ 613 snprintf(pll_name, sizeof(pll_name), "pll_%s", name); 614 615 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 616 if (!pll) 617 return ERR_PTR(-ENOMEM); 618 619 /* create the mux on top of the real pll */ 620 pll->pll_mux_ops = &clk_mux_ops; 621 pll_mux = &pll->pll_mux; 622 pll_mux->reg = base + mode_offset; 623 pll_mux->shift = mode_shift; 624 pll_mux->mask = PLL_MODE_MASK; 625 pll_mux->flags = 0; 626 pll_mux->lock = lock; 627 pll_mux->hw.init = &init; 628 629 if (pll_type == pll_rk3036 || pll_type == pll_rk3066) 630 pll_mux->flags |= CLK_MUX_HIWORD_MASK; 631 632 /* the actual muxing is xin24m, pll-output, xin32k */ 633 pll_parents[0] = parent_names[0]; 634 pll_parents[1] = pll_name; 635 pll_parents[2] = parent_names[1]; 636 637 init.name = name; 638 init.flags = CLK_SET_RATE_PARENT; 639 init.ops = pll->pll_mux_ops; 640 init.parent_names = pll_parents; 641 init.num_parents = ARRAY_SIZE(pll_parents); 642 643 mux_clk = clk_register(NULL, &pll_mux->hw); 644 if (IS_ERR(mux_clk)) 645 goto err_mux; 646 647 /* now create the actual pll */ 648 init.name = pll_name; 649 650 /* keep all plls untouched for now */ 651 init.flags = CLK_IGNORE_UNUSED; 652 653 init.parent_names = &parent_names[0]; 654 init.num_parents = 1; 655 656 if (rate_table) { 657 int len; 658 659 /* find count of rates in rate_table */ 660 for (len = 0; rate_table[len].rate != 0; ) 661 len++; 662 663 pll->rate_count = len; 664 pll->rate_table = kmemdup(rate_table, 665 pll->rate_count * 666 sizeof(struct rockchip_pll_rate_table), 667 GFP_KERNEL); 668 WARN(!pll->rate_table, 669 "%s: could not allocate rate table for %s\n", 670 __func__, name); 671 } 672 673 switch (pll_type) { 674 case pll_rk3036: 675 if (!pll->rate_table) 676 init.ops = &rockchip_rk3036_pll_clk_norate_ops; 677 else 678 init.ops = &rockchip_rk3036_pll_clk_ops; 679 break; 680 case pll_rk3066: 681 if (!pll->rate_table) 682 init.ops = &rockchip_rk3066_pll_clk_norate_ops; 683 else 684 init.ops = &rockchip_rk3066_pll_clk_ops; 685 break; 686 default: 687 pr_warn("%s: Unknown pll type for pll clk %s\n", 688 __func__, name); 689 } 690 691 pll->hw.init = &init; 692 pll->type = pll_type; 693 pll->reg_base = base + con_offset; 694 pll->lock_offset = grf_lock_offset; 695 pll->lock_shift = lock_shift; 696 pll->flags = clk_pll_flags; 697 pll->lock = lock; 698 699 pll_clk = clk_register(NULL, &pll->hw); 700 if (IS_ERR(pll_clk)) { 701 pr_err("%s: failed to register pll clock %s : %ld\n", 702 __func__, name, PTR_ERR(pll_clk)); 703 goto err_pll; 704 } 705 706 return mux_clk; 707 708 err_pll: 709 clk_unregister(mux_clk); 710 mux_clk = pll_clk; 711 err_mux: 712 kfree(pll); 713 return mux_clk; 714 } 715