1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 6 * Author: Xing Zheng <zhengxing@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <asm/div64.h> 20 #include <linux/slab.h> 21 #include <linux/io.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/regmap.h> 25 #include <linux/clk.h> 26 #include "clk.h" 27 28 #define PLL_MODE_MASK 0x3 29 #define PLL_MODE_SLOW 0x0 30 #define PLL_MODE_NORM 0x1 31 #define PLL_MODE_DEEP 0x2 32 33 struct rockchip_clk_pll { 34 struct clk_hw hw; 35 36 struct clk_mux pll_mux; 37 const struct clk_ops *pll_mux_ops; 38 39 struct notifier_block clk_nb; 40 41 void __iomem *reg_base; 42 int lock_offset; 43 unsigned int lock_shift; 44 enum rockchip_pll_type type; 45 u8 flags; 46 const struct rockchip_pll_rate_table *rate_table; 47 unsigned int rate_count; 48 spinlock_t *lock; 49 50 struct rockchip_clk_provider *ctx; 51 }; 52 53 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw) 54 #define to_rockchip_clk_pll_nb(nb) \ 55 container_of(nb, struct rockchip_clk_pll, clk_nb) 56 57 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings( 58 struct rockchip_clk_pll *pll, unsigned long rate) 59 { 60 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 61 int i; 62 63 for (i = 0; i < pll->rate_count; i++) { 64 if (rate == rate_table[i].rate) 65 return &rate_table[i]; 66 } 67 68 return NULL; 69 } 70 71 static long rockchip_pll_round_rate(struct clk_hw *hw, 72 unsigned long drate, unsigned long *prate) 73 { 74 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 75 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 76 int i; 77 78 /* Assumming rate_table is in descending order */ 79 for (i = 0; i < pll->rate_count; i++) { 80 if (drate >= rate_table[i].rate) 81 return rate_table[i].rate; 82 } 83 84 /* return minimum supported value */ 85 return rate_table[i - 1].rate; 86 } 87 88 /* 89 * Wait for the pll to reach the locked state. 90 * The calling set_rate function is responsible for making sure the 91 * grf regmap is available. 92 */ 93 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) 94 { 95 struct regmap *grf = pll->ctx->grf; 96 unsigned int val; 97 int delay = 24000000, ret; 98 99 while (delay > 0) { 100 ret = regmap_read(grf, pll->lock_offset, &val); 101 if (ret) { 102 pr_err("%s: failed to read pll lock status: %d\n", 103 __func__, ret); 104 return ret; 105 } 106 107 if (val & BIT(pll->lock_shift)) 108 return 0; 109 delay--; 110 } 111 112 pr_err("%s: timeout waiting for pll to lock\n", __func__); 113 return -ETIMEDOUT; 114 } 115 116 /** 117 * PLL used in RK3036 118 */ 119 120 #define RK3036_PLLCON(i) (i * 0x4) 121 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 122 #define RK3036_PLLCON0_FBDIV_SHIFT 0 123 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 124 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 125 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 126 #define RK3036_PLLCON1_REFDIV_SHIFT 0 127 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 128 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 129 #define RK3036_PLLCON1_DSMPD_MASK 0x1 130 #define RK3036_PLLCON1_DSMPD_SHIFT 12 131 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 132 #define RK3036_PLLCON2_FRAC_SHIFT 0 133 134 #define RK3036_PLLCON1_PWRDOWN (1 << 13) 135 136 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, 137 struct rockchip_pll_rate_table *rate) 138 { 139 u32 pllcon; 140 141 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); 142 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) 143 & RK3036_PLLCON0_FBDIV_MASK); 144 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) 145 & RK3036_PLLCON0_POSTDIV1_MASK); 146 147 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); 148 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) 149 & RK3036_PLLCON1_REFDIV_MASK); 150 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) 151 & RK3036_PLLCON1_POSTDIV2_MASK); 152 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) 153 & RK3036_PLLCON1_DSMPD_MASK); 154 155 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 156 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) 157 & RK3036_PLLCON2_FRAC_MASK); 158 } 159 160 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, 161 unsigned long prate) 162 { 163 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 164 struct rockchip_pll_rate_table cur; 165 u64 rate64 = prate; 166 167 rockchip_rk3036_pll_get_params(pll, &cur); 168 169 rate64 *= cur.fbdiv; 170 do_div(rate64, cur.refdiv); 171 172 if (cur.dsmpd == 0) { 173 /* fractional mode */ 174 u64 frac_rate64 = prate * cur.frac; 175 176 do_div(frac_rate64, cur.refdiv); 177 rate64 += frac_rate64 >> 24; 178 } 179 180 do_div(rate64, cur.postdiv1); 181 do_div(rate64, cur.postdiv2); 182 183 return (unsigned long)rate64; 184 } 185 186 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, 187 const struct rockchip_pll_rate_table *rate) 188 { 189 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 190 struct clk_mux *pll_mux = &pll->pll_mux; 191 struct rockchip_pll_rate_table cur; 192 u32 pllcon; 193 int rate_change_remuxed = 0; 194 int cur_parent; 195 int ret; 196 197 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 198 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, 199 rate->postdiv2, rate->dsmpd, rate->frac); 200 201 rockchip_rk3036_pll_get_params(pll, &cur); 202 cur.rate = 0; 203 204 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 205 if (cur_parent == PLL_MODE_NORM) { 206 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 207 rate_change_remuxed = 1; 208 } 209 210 /* update pll values */ 211 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, 212 RK3036_PLLCON0_FBDIV_SHIFT) | 213 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, 214 RK3036_PLLCON0_POSTDIV1_SHIFT), 215 pll->reg_base + RK3036_PLLCON(0)); 216 217 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, 218 RK3036_PLLCON1_REFDIV_SHIFT) | 219 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, 220 RK3036_PLLCON1_POSTDIV2_SHIFT) | 221 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, 222 RK3036_PLLCON1_DSMPD_SHIFT), 223 pll->reg_base + RK3036_PLLCON(1)); 224 225 /* GPLL CON2 is not HIWORD_MASK */ 226 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 227 pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT); 228 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; 229 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); 230 231 /* wait for the pll to lock */ 232 ret = rockchip_pll_wait_lock(pll); 233 if (ret) { 234 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 235 __func__); 236 rockchip_rk3036_pll_set_params(pll, &cur); 237 } 238 239 if (rate_change_remuxed) 240 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 241 242 return ret; 243 } 244 245 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, 246 unsigned long prate) 247 { 248 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 249 const struct rockchip_pll_rate_table *rate; 250 251 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 252 __func__, __clk_get_name(hw->clk), drate, prate); 253 254 /* Get required rate settings from table */ 255 rate = rockchip_get_pll_settings(pll, drate); 256 if (!rate) { 257 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 258 drate, __clk_get_name(hw->clk)); 259 return -EINVAL; 260 } 261 262 return rockchip_rk3036_pll_set_params(pll, rate); 263 } 264 265 static int rockchip_rk3036_pll_enable(struct clk_hw *hw) 266 { 267 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 268 269 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), 270 pll->reg_base + RK3036_PLLCON(1)); 271 272 return 0; 273 } 274 275 static void rockchip_rk3036_pll_disable(struct clk_hw *hw) 276 { 277 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 278 279 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, 280 RK3036_PLLCON1_PWRDOWN, 0), 281 pll->reg_base + RK3036_PLLCON(1)); 282 } 283 284 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw) 285 { 286 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 287 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); 288 289 return !(pllcon & RK3036_PLLCON1_PWRDOWN); 290 } 291 292 static void rockchip_rk3036_pll_init(struct clk_hw *hw) 293 { 294 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 295 const struct rockchip_pll_rate_table *rate; 296 struct rockchip_pll_rate_table cur; 297 unsigned long drate; 298 299 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 300 return; 301 302 drate = clk_hw_get_rate(hw); 303 rate = rockchip_get_pll_settings(pll, drate); 304 305 /* when no rate setting for the current rate, rely on clk_set_rate */ 306 if (!rate) 307 return; 308 309 rockchip_rk3036_pll_get_params(pll, &cur); 310 311 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), 312 drate); 313 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 314 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, 315 cur.dsmpd, cur.frac); 316 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 317 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, 318 rate->dsmpd, rate->frac); 319 320 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 321 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 322 rate->dsmpd != cur.dsmpd || 323 (!cur.dsmpd && (rate->frac != cur.frac))) { 324 struct clk *parent = clk_get_parent(hw->clk); 325 326 if (!parent) { 327 pr_warn("%s: parent of %s not available\n", 328 __func__, __clk_get_name(hw->clk)); 329 return; 330 } 331 332 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 333 __func__, __clk_get_name(hw->clk)); 334 rockchip_rk3036_pll_set_params(pll, rate); 335 } 336 } 337 338 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { 339 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 340 .enable = rockchip_rk3036_pll_enable, 341 .disable = rockchip_rk3036_pll_disable, 342 .is_enabled = rockchip_rk3036_pll_is_enabled, 343 }; 344 345 static const struct clk_ops rockchip_rk3036_pll_clk_ops = { 346 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 347 .round_rate = rockchip_pll_round_rate, 348 .set_rate = rockchip_rk3036_pll_set_rate, 349 .enable = rockchip_rk3036_pll_enable, 350 .disable = rockchip_rk3036_pll_disable, 351 .is_enabled = rockchip_rk3036_pll_is_enabled, 352 .init = rockchip_rk3036_pll_init, 353 }; 354 355 /** 356 * PLL used in RK3066, RK3188 and RK3288 357 */ 358 359 #define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1) 360 361 #define RK3066_PLLCON(i) (i * 0x4) 362 #define RK3066_PLLCON0_OD_MASK 0xf 363 #define RK3066_PLLCON0_OD_SHIFT 0 364 #define RK3066_PLLCON0_NR_MASK 0x3f 365 #define RK3066_PLLCON0_NR_SHIFT 8 366 #define RK3066_PLLCON1_NF_MASK 0x1fff 367 #define RK3066_PLLCON1_NF_SHIFT 0 368 #define RK3066_PLLCON2_NB_MASK 0xfff 369 #define RK3066_PLLCON2_NB_SHIFT 0 370 #define RK3066_PLLCON3_RESET (1 << 5) 371 #define RK3066_PLLCON3_PWRDOWN (1 << 1) 372 #define RK3066_PLLCON3_BYPASS (1 << 0) 373 374 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, 375 struct rockchip_pll_rate_table *rate) 376 { 377 u32 pllcon; 378 379 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); 380 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) 381 & RK3066_PLLCON0_NR_MASK) + 1; 382 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) 383 & RK3066_PLLCON0_OD_MASK) + 1; 384 385 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); 386 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) 387 & RK3066_PLLCON1_NF_MASK) + 1; 388 389 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); 390 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) 391 & RK3066_PLLCON2_NB_MASK) + 1; 392 } 393 394 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, 395 unsigned long prate) 396 { 397 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 398 struct rockchip_pll_rate_table cur; 399 u64 rate64 = prate; 400 u32 pllcon; 401 402 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); 403 if (pllcon & RK3066_PLLCON3_BYPASS) { 404 pr_debug("%s: pll %s is bypassed\n", __func__, 405 clk_hw_get_name(hw)); 406 return prate; 407 } 408 409 rockchip_rk3066_pll_get_params(pll, &cur); 410 411 rate64 *= cur.nf; 412 do_div(rate64, cur.nr); 413 do_div(rate64, cur.no); 414 415 return (unsigned long)rate64; 416 } 417 418 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, 419 const struct rockchip_pll_rate_table *rate) 420 { 421 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 422 struct clk_mux *pll_mux = &pll->pll_mux; 423 struct rockchip_pll_rate_table cur; 424 int rate_change_remuxed = 0; 425 int cur_parent; 426 int ret; 427 428 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", 429 __func__, rate->rate, rate->nr, rate->no, rate->nf); 430 431 rockchip_rk3066_pll_get_params(pll, &cur); 432 cur.rate = 0; 433 434 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 435 if (cur_parent == PLL_MODE_NORM) { 436 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 437 rate_change_remuxed = 1; 438 } 439 440 /* enter reset mode */ 441 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), 442 pll->reg_base + RK3066_PLLCON(3)); 443 444 /* update pll values */ 445 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, 446 RK3066_PLLCON0_NR_SHIFT) | 447 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, 448 RK3066_PLLCON0_OD_SHIFT), 449 pll->reg_base + RK3066_PLLCON(0)); 450 451 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, 452 RK3066_PLLCON1_NF_SHIFT), 453 pll->reg_base + RK3066_PLLCON(1)); 454 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, 455 RK3066_PLLCON2_NB_SHIFT), 456 pll->reg_base + RK3066_PLLCON(2)); 457 458 /* leave reset and wait the reset_delay */ 459 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), 460 pll->reg_base + RK3066_PLLCON(3)); 461 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); 462 463 /* wait for the pll to lock */ 464 ret = rockchip_pll_wait_lock(pll); 465 if (ret) { 466 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 467 __func__); 468 rockchip_rk3066_pll_set_params(pll, &cur); 469 } 470 471 if (rate_change_remuxed) 472 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 473 474 return ret; 475 } 476 477 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, 478 unsigned long prate) 479 { 480 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 481 const struct rockchip_pll_rate_table *rate; 482 483 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 484 __func__, clk_hw_get_name(hw), drate, prate); 485 486 /* Get required rate settings from table */ 487 rate = rockchip_get_pll_settings(pll, drate); 488 if (!rate) { 489 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 490 drate, clk_hw_get_name(hw)); 491 return -EINVAL; 492 } 493 494 return rockchip_rk3066_pll_set_params(pll, rate); 495 } 496 497 static int rockchip_rk3066_pll_enable(struct clk_hw *hw) 498 { 499 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 500 501 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), 502 pll->reg_base + RK3066_PLLCON(3)); 503 504 return 0; 505 } 506 507 static void rockchip_rk3066_pll_disable(struct clk_hw *hw) 508 { 509 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 510 511 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN, 512 RK3066_PLLCON3_PWRDOWN, 0), 513 pll->reg_base + RK3066_PLLCON(3)); 514 } 515 516 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw) 517 { 518 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 519 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); 520 521 return !(pllcon & RK3066_PLLCON3_PWRDOWN); 522 } 523 524 static void rockchip_rk3066_pll_init(struct clk_hw *hw) 525 { 526 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 527 const struct rockchip_pll_rate_table *rate; 528 struct rockchip_pll_rate_table cur; 529 unsigned long drate; 530 531 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 532 return; 533 534 drate = clk_hw_get_rate(hw); 535 rate = rockchip_get_pll_settings(pll, drate); 536 537 /* when no rate setting for the current rate, rely on clk_set_rate */ 538 if (!rate) 539 return; 540 541 rockchip_rk3066_pll_get_params(pll, &cur); 542 543 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", 544 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, 545 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); 546 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf 547 || rate->nb != cur.nb) { 548 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 549 __func__, clk_hw_get_name(hw)); 550 rockchip_rk3066_pll_set_params(pll, rate); 551 } 552 } 553 554 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { 555 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 556 .enable = rockchip_rk3066_pll_enable, 557 .disable = rockchip_rk3066_pll_disable, 558 .is_enabled = rockchip_rk3066_pll_is_enabled, 559 }; 560 561 static const struct clk_ops rockchip_rk3066_pll_clk_ops = { 562 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 563 .round_rate = rockchip_pll_round_rate, 564 .set_rate = rockchip_rk3066_pll_set_rate, 565 .enable = rockchip_rk3066_pll_enable, 566 .disable = rockchip_rk3066_pll_disable, 567 .is_enabled = rockchip_rk3066_pll_is_enabled, 568 .init = rockchip_rk3066_pll_init, 569 }; 570 571 /** 572 * PLL used in RK3399 573 */ 574 575 #define RK3399_PLLCON(i) (i * 0x4) 576 #define RK3399_PLLCON0_FBDIV_MASK 0xfff 577 #define RK3399_PLLCON0_FBDIV_SHIFT 0 578 #define RK3399_PLLCON1_REFDIV_MASK 0x3f 579 #define RK3399_PLLCON1_REFDIV_SHIFT 0 580 #define RK3399_PLLCON1_POSTDIV1_MASK 0x7 581 #define RK3399_PLLCON1_POSTDIV1_SHIFT 8 582 #define RK3399_PLLCON1_POSTDIV2_MASK 0x7 583 #define RK3399_PLLCON1_POSTDIV2_SHIFT 12 584 #define RK3399_PLLCON2_FRAC_MASK 0xffffff 585 #define RK3399_PLLCON2_FRAC_SHIFT 0 586 #define RK3399_PLLCON2_LOCK_STATUS BIT(31) 587 #define RK3399_PLLCON3_PWRDOWN BIT(0) 588 #define RK3399_PLLCON3_DSMPD_MASK 0x1 589 #define RK3399_PLLCON3_DSMPD_SHIFT 3 590 591 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) 592 { 593 u32 pllcon; 594 int delay = 24000000; 595 596 /* poll check the lock status in rk3399 xPLLCON2 */ 597 while (delay > 0) { 598 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); 599 if (pllcon & RK3399_PLLCON2_LOCK_STATUS) 600 return 0; 601 602 delay--; 603 } 604 605 pr_err("%s: timeout waiting for pll to lock\n", __func__); 606 return -ETIMEDOUT; 607 } 608 609 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, 610 struct rockchip_pll_rate_table *rate) 611 { 612 u32 pllcon; 613 614 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); 615 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) 616 & RK3399_PLLCON0_FBDIV_MASK); 617 618 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); 619 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) 620 & RK3399_PLLCON1_REFDIV_MASK); 621 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) 622 & RK3399_PLLCON1_POSTDIV1_MASK); 623 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) 624 & RK3399_PLLCON1_POSTDIV2_MASK); 625 626 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); 627 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) 628 & RK3399_PLLCON2_FRAC_MASK); 629 630 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); 631 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) 632 & RK3399_PLLCON3_DSMPD_MASK); 633 } 634 635 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw, 636 unsigned long prate) 637 { 638 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 639 struct rockchip_pll_rate_table cur; 640 u64 rate64 = prate; 641 642 rockchip_rk3399_pll_get_params(pll, &cur); 643 644 rate64 *= cur.fbdiv; 645 do_div(rate64, cur.refdiv); 646 647 if (cur.dsmpd == 0) { 648 /* fractional mode */ 649 u64 frac_rate64 = prate * cur.frac; 650 651 do_div(frac_rate64, cur.refdiv); 652 rate64 += frac_rate64 >> 24; 653 } 654 655 do_div(rate64, cur.postdiv1); 656 do_div(rate64, cur.postdiv2); 657 658 return (unsigned long)rate64; 659 } 660 661 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, 662 const struct rockchip_pll_rate_table *rate) 663 { 664 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 665 struct clk_mux *pll_mux = &pll->pll_mux; 666 struct rockchip_pll_rate_table cur; 667 u32 pllcon; 668 int rate_change_remuxed = 0; 669 int cur_parent; 670 int ret; 671 672 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 673 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, 674 rate->postdiv2, rate->dsmpd, rate->frac); 675 676 rockchip_rk3399_pll_get_params(pll, &cur); 677 cur.rate = 0; 678 679 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 680 if (cur_parent == PLL_MODE_NORM) { 681 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 682 rate_change_remuxed = 1; 683 } 684 685 /* update pll values */ 686 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, 687 RK3399_PLLCON0_FBDIV_SHIFT), 688 pll->reg_base + RK3399_PLLCON(0)); 689 690 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, 691 RK3399_PLLCON1_REFDIV_SHIFT) | 692 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, 693 RK3399_PLLCON1_POSTDIV1_SHIFT) | 694 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, 695 RK3399_PLLCON1_POSTDIV2_SHIFT), 696 pll->reg_base + RK3399_PLLCON(1)); 697 698 /* xPLL CON2 is not HIWORD_MASK */ 699 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); 700 pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT); 701 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; 702 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); 703 704 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, 705 RK3399_PLLCON3_DSMPD_SHIFT), 706 pll->reg_base + RK3399_PLLCON(3)); 707 708 /* wait for the pll to lock */ 709 ret = rockchip_rk3399_pll_wait_lock(pll); 710 if (ret) { 711 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 712 __func__); 713 rockchip_rk3399_pll_set_params(pll, &cur); 714 } 715 716 if (rate_change_remuxed) 717 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 718 719 return ret; 720 } 721 722 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, 723 unsigned long prate) 724 { 725 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 726 const struct rockchip_pll_rate_table *rate; 727 728 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 729 __func__, __clk_get_name(hw->clk), drate, prate); 730 731 /* Get required rate settings from table */ 732 rate = rockchip_get_pll_settings(pll, drate); 733 if (!rate) { 734 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 735 drate, __clk_get_name(hw->clk)); 736 return -EINVAL; 737 } 738 739 return rockchip_rk3399_pll_set_params(pll, rate); 740 } 741 742 static int rockchip_rk3399_pll_enable(struct clk_hw *hw) 743 { 744 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 745 746 writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), 747 pll->reg_base + RK3399_PLLCON(3)); 748 749 return 0; 750 } 751 752 static void rockchip_rk3399_pll_disable(struct clk_hw *hw) 753 { 754 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 755 756 writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, 757 RK3399_PLLCON3_PWRDOWN, 0), 758 pll->reg_base + RK3399_PLLCON(3)); 759 } 760 761 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw) 762 { 763 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 764 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); 765 766 return !(pllcon & RK3399_PLLCON3_PWRDOWN); 767 } 768 769 static void rockchip_rk3399_pll_init(struct clk_hw *hw) 770 { 771 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 772 const struct rockchip_pll_rate_table *rate; 773 struct rockchip_pll_rate_table cur; 774 unsigned long drate; 775 776 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 777 return; 778 779 drate = clk_hw_get_rate(hw); 780 rate = rockchip_get_pll_settings(pll, drate); 781 782 /* when no rate setting for the current rate, rely on clk_set_rate */ 783 if (!rate) 784 return; 785 786 rockchip_rk3399_pll_get_params(pll, &cur); 787 788 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), 789 drate); 790 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 791 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, 792 cur.dsmpd, cur.frac); 793 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 794 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, 795 rate->dsmpd, rate->frac); 796 797 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 798 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 799 rate->dsmpd != cur.dsmpd || 800 (!cur.dsmpd && (rate->frac != cur.frac))) { 801 struct clk *parent = clk_get_parent(hw->clk); 802 803 if (!parent) { 804 pr_warn("%s: parent of %s not available\n", 805 __func__, __clk_get_name(hw->clk)); 806 return; 807 } 808 809 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 810 __func__, __clk_get_name(hw->clk)); 811 rockchip_rk3399_pll_set_params(pll, rate); 812 } 813 } 814 815 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = { 816 .recalc_rate = rockchip_rk3399_pll_recalc_rate, 817 .enable = rockchip_rk3399_pll_enable, 818 .disable = rockchip_rk3399_pll_disable, 819 .is_enabled = rockchip_rk3399_pll_is_enabled, 820 }; 821 822 static const struct clk_ops rockchip_rk3399_pll_clk_ops = { 823 .recalc_rate = rockchip_rk3399_pll_recalc_rate, 824 .round_rate = rockchip_pll_round_rate, 825 .set_rate = rockchip_rk3399_pll_set_rate, 826 .enable = rockchip_rk3399_pll_enable, 827 .disable = rockchip_rk3399_pll_disable, 828 .is_enabled = rockchip_rk3399_pll_is_enabled, 829 .init = rockchip_rk3399_pll_init, 830 }; 831 832 /* 833 * Common registering of pll clocks 834 */ 835 836 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, 837 enum rockchip_pll_type pll_type, 838 const char *name, const char *const *parent_names, 839 u8 num_parents, int con_offset, int grf_lock_offset, 840 int lock_shift, int mode_offset, int mode_shift, 841 struct rockchip_pll_rate_table *rate_table, 842 unsigned long flags, u8 clk_pll_flags) 843 { 844 const char *pll_parents[3]; 845 struct clk_init_data init; 846 struct rockchip_clk_pll *pll; 847 struct clk_mux *pll_mux; 848 struct clk *pll_clk, *mux_clk; 849 char pll_name[20]; 850 851 if (num_parents != 2) { 852 pr_err("%s: needs two parent clocks\n", __func__); 853 return ERR_PTR(-EINVAL); 854 } 855 856 /* name the actual pll */ 857 snprintf(pll_name, sizeof(pll_name), "pll_%s", name); 858 859 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 860 if (!pll) 861 return ERR_PTR(-ENOMEM); 862 863 /* create the mux on top of the real pll */ 864 pll->pll_mux_ops = &clk_mux_ops; 865 pll_mux = &pll->pll_mux; 866 pll_mux->reg = ctx->reg_base + mode_offset; 867 pll_mux->shift = mode_shift; 868 pll_mux->mask = PLL_MODE_MASK; 869 pll_mux->flags = 0; 870 pll_mux->lock = &ctx->lock; 871 pll_mux->hw.init = &init; 872 873 if (pll_type == pll_rk3036 || 874 pll_type == pll_rk3066 || 875 pll_type == pll_rk3399) 876 pll_mux->flags |= CLK_MUX_HIWORD_MASK; 877 878 /* the actual muxing is xin24m, pll-output, xin32k */ 879 pll_parents[0] = parent_names[0]; 880 pll_parents[1] = pll_name; 881 pll_parents[2] = parent_names[1]; 882 883 init.name = name; 884 init.flags = CLK_SET_RATE_PARENT; 885 init.ops = pll->pll_mux_ops; 886 init.parent_names = pll_parents; 887 init.num_parents = ARRAY_SIZE(pll_parents); 888 889 mux_clk = clk_register(NULL, &pll_mux->hw); 890 if (IS_ERR(mux_clk)) 891 goto err_mux; 892 893 /* now create the actual pll */ 894 init.name = pll_name; 895 896 /* keep all plls untouched for now */ 897 init.flags = flags | CLK_IGNORE_UNUSED; 898 899 init.parent_names = &parent_names[0]; 900 init.num_parents = 1; 901 902 if (rate_table) { 903 int len; 904 905 /* find count of rates in rate_table */ 906 for (len = 0; rate_table[len].rate != 0; ) 907 len++; 908 909 pll->rate_count = len; 910 pll->rate_table = kmemdup(rate_table, 911 pll->rate_count * 912 sizeof(struct rockchip_pll_rate_table), 913 GFP_KERNEL); 914 WARN(!pll->rate_table, 915 "%s: could not allocate rate table for %s\n", 916 __func__, name); 917 } 918 919 switch (pll_type) { 920 case pll_rk3036: 921 if (!pll->rate_table || IS_ERR(ctx->grf)) 922 init.ops = &rockchip_rk3036_pll_clk_norate_ops; 923 else 924 init.ops = &rockchip_rk3036_pll_clk_ops; 925 break; 926 case pll_rk3066: 927 if (!pll->rate_table || IS_ERR(ctx->grf)) 928 init.ops = &rockchip_rk3066_pll_clk_norate_ops; 929 else 930 init.ops = &rockchip_rk3066_pll_clk_ops; 931 break; 932 case pll_rk3399: 933 if (!pll->rate_table) 934 init.ops = &rockchip_rk3399_pll_clk_norate_ops; 935 else 936 init.ops = &rockchip_rk3399_pll_clk_ops; 937 break; 938 default: 939 pr_warn("%s: Unknown pll type for pll clk %s\n", 940 __func__, name); 941 } 942 943 pll->hw.init = &init; 944 pll->type = pll_type; 945 pll->reg_base = ctx->reg_base + con_offset; 946 pll->lock_offset = grf_lock_offset; 947 pll->lock_shift = lock_shift; 948 pll->flags = clk_pll_flags; 949 pll->lock = &ctx->lock; 950 pll->ctx = ctx; 951 952 pll_clk = clk_register(NULL, &pll->hw); 953 if (IS_ERR(pll_clk)) { 954 pr_err("%s: failed to register pll clock %s : %ld\n", 955 __func__, name, PTR_ERR(pll_clk)); 956 goto err_pll; 957 } 958 959 return mux_clk; 960 961 err_pll: 962 clk_unregister(mux_clk); 963 mux_clk = pll_clk; 964 err_mux: 965 kfree(pll); 966 return mux_clk; 967 } 968