1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 7 * Author: Xing Zheng <zhengxing@rock-chips.com> 8 */ 9 10 #include <asm/div64.h> 11 #include <linux/slab.h> 12 #include <linux/io.h> 13 #include <linux/delay.h> 14 #include <linux/clk-provider.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include "clk.h" 18 19 #define PLL_MODE_MASK 0x3 20 #define PLL_MODE_SLOW 0x0 21 #define PLL_MODE_NORM 0x1 22 #define PLL_MODE_DEEP 0x2 23 #define PLL_RK3328_MODE_MASK 0x1 24 25 struct rockchip_clk_pll { 26 struct clk_hw hw; 27 28 struct clk_mux pll_mux; 29 const struct clk_ops *pll_mux_ops; 30 31 struct notifier_block clk_nb; 32 33 void __iomem *reg_base; 34 int lock_offset; 35 unsigned int lock_shift; 36 enum rockchip_pll_type type; 37 u8 flags; 38 const struct rockchip_pll_rate_table *rate_table; 39 unsigned int rate_count; 40 spinlock_t *lock; 41 42 struct rockchip_clk_provider *ctx; 43 }; 44 45 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw) 46 #define to_rockchip_clk_pll_nb(nb) \ 47 container_of(nb, struct rockchip_clk_pll, clk_nb) 48 49 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings( 50 struct rockchip_clk_pll *pll, unsigned long rate) 51 { 52 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 53 int i; 54 55 for (i = 0; i < pll->rate_count; i++) { 56 if (rate == rate_table[i].rate) 57 return &rate_table[i]; 58 } 59 60 return NULL; 61 } 62 63 static long rockchip_pll_round_rate(struct clk_hw *hw, 64 unsigned long drate, unsigned long *prate) 65 { 66 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 67 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 68 int i; 69 70 /* Assumming rate_table is in descending order */ 71 for (i = 0; i < pll->rate_count; i++) { 72 if (drate >= rate_table[i].rate) 73 return rate_table[i].rate; 74 } 75 76 /* return minimum supported value */ 77 return rate_table[i - 1].rate; 78 } 79 80 /* 81 * Wait for the pll to reach the locked state. 82 * The calling set_rate function is responsible for making sure the 83 * grf regmap is available. 84 */ 85 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) 86 { 87 struct regmap *grf = pll->ctx->grf; 88 unsigned int val; 89 int delay = 24000000, ret; 90 91 while (delay > 0) { 92 ret = regmap_read(grf, pll->lock_offset, &val); 93 if (ret) { 94 pr_err("%s: failed to read pll lock status: %d\n", 95 __func__, ret); 96 return ret; 97 } 98 99 if (val & BIT(pll->lock_shift)) 100 return 0; 101 delay--; 102 } 103 104 pr_err("%s: timeout waiting for pll to lock\n", __func__); 105 return -ETIMEDOUT; 106 } 107 108 /** 109 * PLL used in RK3036 110 */ 111 112 #define RK3036_PLLCON(i) (i * 0x4) 113 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 114 #define RK3036_PLLCON0_FBDIV_SHIFT 0 115 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 116 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 117 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 118 #define RK3036_PLLCON1_REFDIV_SHIFT 0 119 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 120 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 121 #define RK3036_PLLCON1_DSMPD_MASK 0x1 122 #define RK3036_PLLCON1_DSMPD_SHIFT 12 123 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 124 #define RK3036_PLLCON2_FRAC_SHIFT 0 125 126 #define RK3036_PLLCON1_PWRDOWN (1 << 13) 127 128 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, 129 struct rockchip_pll_rate_table *rate) 130 { 131 u32 pllcon; 132 133 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); 134 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) 135 & RK3036_PLLCON0_FBDIV_MASK); 136 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) 137 & RK3036_PLLCON0_POSTDIV1_MASK); 138 139 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); 140 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) 141 & RK3036_PLLCON1_REFDIV_MASK); 142 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) 143 & RK3036_PLLCON1_POSTDIV2_MASK); 144 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) 145 & RK3036_PLLCON1_DSMPD_MASK); 146 147 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 148 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) 149 & RK3036_PLLCON2_FRAC_MASK); 150 } 151 152 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, 153 unsigned long prate) 154 { 155 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 156 struct rockchip_pll_rate_table cur; 157 u64 rate64 = prate; 158 159 rockchip_rk3036_pll_get_params(pll, &cur); 160 161 rate64 *= cur.fbdiv; 162 do_div(rate64, cur.refdiv); 163 164 if (cur.dsmpd == 0) { 165 /* fractional mode */ 166 u64 frac_rate64 = prate * cur.frac; 167 168 do_div(frac_rate64, cur.refdiv); 169 rate64 += frac_rate64 >> 24; 170 } 171 172 do_div(rate64, cur.postdiv1); 173 do_div(rate64, cur.postdiv2); 174 175 return (unsigned long)rate64; 176 } 177 178 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, 179 const struct rockchip_pll_rate_table *rate) 180 { 181 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 182 struct clk_mux *pll_mux = &pll->pll_mux; 183 struct rockchip_pll_rate_table cur; 184 u32 pllcon; 185 int rate_change_remuxed = 0; 186 int cur_parent; 187 int ret; 188 189 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 190 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, 191 rate->postdiv2, rate->dsmpd, rate->frac); 192 193 rockchip_rk3036_pll_get_params(pll, &cur); 194 cur.rate = 0; 195 196 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 197 if (cur_parent == PLL_MODE_NORM) { 198 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 199 rate_change_remuxed = 1; 200 } 201 202 /* update pll values */ 203 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, 204 RK3036_PLLCON0_FBDIV_SHIFT) | 205 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, 206 RK3036_PLLCON0_POSTDIV1_SHIFT), 207 pll->reg_base + RK3036_PLLCON(0)); 208 209 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, 210 RK3036_PLLCON1_REFDIV_SHIFT) | 211 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, 212 RK3036_PLLCON1_POSTDIV2_SHIFT) | 213 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, 214 RK3036_PLLCON1_DSMPD_SHIFT), 215 pll->reg_base + RK3036_PLLCON(1)); 216 217 /* GPLL CON2 is not HIWORD_MASK */ 218 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 219 pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT); 220 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; 221 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); 222 223 /* wait for the pll to lock */ 224 ret = rockchip_pll_wait_lock(pll); 225 if (ret) { 226 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 227 __func__); 228 rockchip_rk3036_pll_set_params(pll, &cur); 229 } 230 231 if (rate_change_remuxed) 232 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 233 234 return ret; 235 } 236 237 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, 238 unsigned long prate) 239 { 240 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 241 const struct rockchip_pll_rate_table *rate; 242 243 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 244 __func__, __clk_get_name(hw->clk), drate, prate); 245 246 /* Get required rate settings from table */ 247 rate = rockchip_get_pll_settings(pll, drate); 248 if (!rate) { 249 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 250 drate, __clk_get_name(hw->clk)); 251 return -EINVAL; 252 } 253 254 return rockchip_rk3036_pll_set_params(pll, rate); 255 } 256 257 static int rockchip_rk3036_pll_enable(struct clk_hw *hw) 258 { 259 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 260 261 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), 262 pll->reg_base + RK3036_PLLCON(1)); 263 rockchip_pll_wait_lock(pll); 264 265 return 0; 266 } 267 268 static void rockchip_rk3036_pll_disable(struct clk_hw *hw) 269 { 270 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 271 272 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, 273 RK3036_PLLCON1_PWRDOWN, 0), 274 pll->reg_base + RK3036_PLLCON(1)); 275 } 276 277 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw) 278 { 279 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 280 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); 281 282 return !(pllcon & RK3036_PLLCON1_PWRDOWN); 283 } 284 285 static int rockchip_rk3036_pll_init(struct clk_hw *hw) 286 { 287 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 288 const struct rockchip_pll_rate_table *rate; 289 struct rockchip_pll_rate_table cur; 290 unsigned long drate; 291 292 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 293 return 0; 294 295 drate = clk_hw_get_rate(hw); 296 rate = rockchip_get_pll_settings(pll, drate); 297 298 /* when no rate setting for the current rate, rely on clk_set_rate */ 299 if (!rate) 300 return 0; 301 302 rockchip_rk3036_pll_get_params(pll, &cur); 303 304 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), 305 drate); 306 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 307 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, 308 cur.dsmpd, cur.frac); 309 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 310 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, 311 rate->dsmpd, rate->frac); 312 313 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 314 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 315 rate->dsmpd != cur.dsmpd || 316 (!cur.dsmpd && (rate->frac != cur.frac))) { 317 struct clk *parent = clk_get_parent(hw->clk); 318 319 if (!parent) { 320 pr_warn("%s: parent of %s not available\n", 321 __func__, __clk_get_name(hw->clk)); 322 return 0; 323 } 324 325 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 326 __func__, __clk_get_name(hw->clk)); 327 rockchip_rk3036_pll_set_params(pll, rate); 328 } 329 330 return 0; 331 } 332 333 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { 334 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 335 .enable = rockchip_rk3036_pll_enable, 336 .disable = rockchip_rk3036_pll_disable, 337 .is_enabled = rockchip_rk3036_pll_is_enabled, 338 }; 339 340 static const struct clk_ops rockchip_rk3036_pll_clk_ops = { 341 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 342 .round_rate = rockchip_pll_round_rate, 343 .set_rate = rockchip_rk3036_pll_set_rate, 344 .enable = rockchip_rk3036_pll_enable, 345 .disable = rockchip_rk3036_pll_disable, 346 .is_enabled = rockchip_rk3036_pll_is_enabled, 347 .init = rockchip_rk3036_pll_init, 348 }; 349 350 /** 351 * PLL used in RK3066, RK3188 and RK3288 352 */ 353 354 #define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1) 355 356 #define RK3066_PLLCON(i) (i * 0x4) 357 #define RK3066_PLLCON0_OD_MASK 0xf 358 #define RK3066_PLLCON0_OD_SHIFT 0 359 #define RK3066_PLLCON0_NR_MASK 0x3f 360 #define RK3066_PLLCON0_NR_SHIFT 8 361 #define RK3066_PLLCON1_NF_MASK 0x1fff 362 #define RK3066_PLLCON1_NF_SHIFT 0 363 #define RK3066_PLLCON2_NB_MASK 0xfff 364 #define RK3066_PLLCON2_NB_SHIFT 0 365 #define RK3066_PLLCON3_RESET (1 << 5) 366 #define RK3066_PLLCON3_PWRDOWN (1 << 1) 367 #define RK3066_PLLCON3_BYPASS (1 << 0) 368 369 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, 370 struct rockchip_pll_rate_table *rate) 371 { 372 u32 pllcon; 373 374 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); 375 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) 376 & RK3066_PLLCON0_NR_MASK) + 1; 377 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) 378 & RK3066_PLLCON0_OD_MASK) + 1; 379 380 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); 381 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) 382 & RK3066_PLLCON1_NF_MASK) + 1; 383 384 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); 385 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) 386 & RK3066_PLLCON2_NB_MASK) + 1; 387 } 388 389 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, 390 unsigned long prate) 391 { 392 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 393 struct rockchip_pll_rate_table cur; 394 u64 rate64 = prate; 395 u32 pllcon; 396 397 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); 398 if (pllcon & RK3066_PLLCON3_BYPASS) { 399 pr_debug("%s: pll %s is bypassed\n", __func__, 400 clk_hw_get_name(hw)); 401 return prate; 402 } 403 404 rockchip_rk3066_pll_get_params(pll, &cur); 405 406 rate64 *= cur.nf; 407 do_div(rate64, cur.nr); 408 do_div(rate64, cur.no); 409 410 return (unsigned long)rate64; 411 } 412 413 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, 414 const struct rockchip_pll_rate_table *rate) 415 { 416 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 417 struct clk_mux *pll_mux = &pll->pll_mux; 418 struct rockchip_pll_rate_table cur; 419 int rate_change_remuxed = 0; 420 int cur_parent; 421 int ret; 422 423 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", 424 __func__, rate->rate, rate->nr, rate->no, rate->nf); 425 426 rockchip_rk3066_pll_get_params(pll, &cur); 427 cur.rate = 0; 428 429 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 430 if (cur_parent == PLL_MODE_NORM) { 431 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 432 rate_change_remuxed = 1; 433 } 434 435 /* enter reset mode */ 436 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), 437 pll->reg_base + RK3066_PLLCON(3)); 438 439 /* update pll values */ 440 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, 441 RK3066_PLLCON0_NR_SHIFT) | 442 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, 443 RK3066_PLLCON0_OD_SHIFT), 444 pll->reg_base + RK3066_PLLCON(0)); 445 446 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, 447 RK3066_PLLCON1_NF_SHIFT), 448 pll->reg_base + RK3066_PLLCON(1)); 449 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, 450 RK3066_PLLCON2_NB_SHIFT), 451 pll->reg_base + RK3066_PLLCON(2)); 452 453 /* leave reset and wait the reset_delay */ 454 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), 455 pll->reg_base + RK3066_PLLCON(3)); 456 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); 457 458 /* wait for the pll to lock */ 459 ret = rockchip_pll_wait_lock(pll); 460 if (ret) { 461 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 462 __func__); 463 rockchip_rk3066_pll_set_params(pll, &cur); 464 } 465 466 if (rate_change_remuxed) 467 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 468 469 return ret; 470 } 471 472 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, 473 unsigned long prate) 474 { 475 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 476 const struct rockchip_pll_rate_table *rate; 477 478 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 479 __func__, clk_hw_get_name(hw), drate, prate); 480 481 /* Get required rate settings from table */ 482 rate = rockchip_get_pll_settings(pll, drate); 483 if (!rate) { 484 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 485 drate, clk_hw_get_name(hw)); 486 return -EINVAL; 487 } 488 489 return rockchip_rk3066_pll_set_params(pll, rate); 490 } 491 492 static int rockchip_rk3066_pll_enable(struct clk_hw *hw) 493 { 494 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 495 496 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), 497 pll->reg_base + RK3066_PLLCON(3)); 498 rockchip_pll_wait_lock(pll); 499 500 return 0; 501 } 502 503 static void rockchip_rk3066_pll_disable(struct clk_hw *hw) 504 { 505 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 506 507 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN, 508 RK3066_PLLCON3_PWRDOWN, 0), 509 pll->reg_base + RK3066_PLLCON(3)); 510 } 511 512 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw) 513 { 514 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 515 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); 516 517 return !(pllcon & RK3066_PLLCON3_PWRDOWN); 518 } 519 520 static int rockchip_rk3066_pll_init(struct clk_hw *hw) 521 { 522 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 523 const struct rockchip_pll_rate_table *rate; 524 struct rockchip_pll_rate_table cur; 525 unsigned long drate; 526 527 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 528 return 0; 529 530 drate = clk_hw_get_rate(hw); 531 rate = rockchip_get_pll_settings(pll, drate); 532 533 /* when no rate setting for the current rate, rely on clk_set_rate */ 534 if (!rate) 535 return 0; 536 537 rockchip_rk3066_pll_get_params(pll, &cur); 538 539 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", 540 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, 541 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); 542 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf 543 || rate->nb != cur.nb) { 544 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 545 __func__, clk_hw_get_name(hw)); 546 rockchip_rk3066_pll_set_params(pll, rate); 547 } 548 549 return 0; 550 } 551 552 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { 553 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 554 .enable = rockchip_rk3066_pll_enable, 555 .disable = rockchip_rk3066_pll_disable, 556 .is_enabled = rockchip_rk3066_pll_is_enabled, 557 }; 558 559 static const struct clk_ops rockchip_rk3066_pll_clk_ops = { 560 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 561 .round_rate = rockchip_pll_round_rate, 562 .set_rate = rockchip_rk3066_pll_set_rate, 563 .enable = rockchip_rk3066_pll_enable, 564 .disable = rockchip_rk3066_pll_disable, 565 .is_enabled = rockchip_rk3066_pll_is_enabled, 566 .init = rockchip_rk3066_pll_init, 567 }; 568 569 /** 570 * PLL used in RK3399 571 */ 572 573 #define RK3399_PLLCON(i) (i * 0x4) 574 #define RK3399_PLLCON0_FBDIV_MASK 0xfff 575 #define RK3399_PLLCON0_FBDIV_SHIFT 0 576 #define RK3399_PLLCON1_REFDIV_MASK 0x3f 577 #define RK3399_PLLCON1_REFDIV_SHIFT 0 578 #define RK3399_PLLCON1_POSTDIV1_MASK 0x7 579 #define RK3399_PLLCON1_POSTDIV1_SHIFT 8 580 #define RK3399_PLLCON1_POSTDIV2_MASK 0x7 581 #define RK3399_PLLCON1_POSTDIV2_SHIFT 12 582 #define RK3399_PLLCON2_FRAC_MASK 0xffffff 583 #define RK3399_PLLCON2_FRAC_SHIFT 0 584 #define RK3399_PLLCON2_LOCK_STATUS BIT(31) 585 #define RK3399_PLLCON3_PWRDOWN BIT(0) 586 #define RK3399_PLLCON3_DSMPD_MASK 0x1 587 #define RK3399_PLLCON3_DSMPD_SHIFT 3 588 589 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) 590 { 591 u32 pllcon; 592 int delay = 24000000; 593 594 /* poll check the lock status in rk3399 xPLLCON2 */ 595 while (delay > 0) { 596 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); 597 if (pllcon & RK3399_PLLCON2_LOCK_STATUS) 598 return 0; 599 600 delay--; 601 } 602 603 pr_err("%s: timeout waiting for pll to lock\n", __func__); 604 return -ETIMEDOUT; 605 } 606 607 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, 608 struct rockchip_pll_rate_table *rate) 609 { 610 u32 pllcon; 611 612 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); 613 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) 614 & RK3399_PLLCON0_FBDIV_MASK); 615 616 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); 617 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) 618 & RK3399_PLLCON1_REFDIV_MASK); 619 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) 620 & RK3399_PLLCON1_POSTDIV1_MASK); 621 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) 622 & RK3399_PLLCON1_POSTDIV2_MASK); 623 624 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); 625 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) 626 & RK3399_PLLCON2_FRAC_MASK); 627 628 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); 629 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) 630 & RK3399_PLLCON3_DSMPD_MASK); 631 } 632 633 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw, 634 unsigned long prate) 635 { 636 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 637 struct rockchip_pll_rate_table cur; 638 u64 rate64 = prate; 639 640 rockchip_rk3399_pll_get_params(pll, &cur); 641 642 rate64 *= cur.fbdiv; 643 do_div(rate64, cur.refdiv); 644 645 if (cur.dsmpd == 0) { 646 /* fractional mode */ 647 u64 frac_rate64 = prate * cur.frac; 648 649 do_div(frac_rate64, cur.refdiv); 650 rate64 += frac_rate64 >> 24; 651 } 652 653 do_div(rate64, cur.postdiv1); 654 do_div(rate64, cur.postdiv2); 655 656 return (unsigned long)rate64; 657 } 658 659 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, 660 const struct rockchip_pll_rate_table *rate) 661 { 662 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 663 struct clk_mux *pll_mux = &pll->pll_mux; 664 struct rockchip_pll_rate_table cur; 665 u32 pllcon; 666 int rate_change_remuxed = 0; 667 int cur_parent; 668 int ret; 669 670 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 671 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, 672 rate->postdiv2, rate->dsmpd, rate->frac); 673 674 rockchip_rk3399_pll_get_params(pll, &cur); 675 cur.rate = 0; 676 677 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 678 if (cur_parent == PLL_MODE_NORM) { 679 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 680 rate_change_remuxed = 1; 681 } 682 683 /* update pll values */ 684 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, 685 RK3399_PLLCON0_FBDIV_SHIFT), 686 pll->reg_base + RK3399_PLLCON(0)); 687 688 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, 689 RK3399_PLLCON1_REFDIV_SHIFT) | 690 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, 691 RK3399_PLLCON1_POSTDIV1_SHIFT) | 692 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, 693 RK3399_PLLCON1_POSTDIV2_SHIFT), 694 pll->reg_base + RK3399_PLLCON(1)); 695 696 /* xPLL CON2 is not HIWORD_MASK */ 697 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); 698 pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT); 699 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; 700 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); 701 702 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, 703 RK3399_PLLCON3_DSMPD_SHIFT), 704 pll->reg_base + RK3399_PLLCON(3)); 705 706 /* wait for the pll to lock */ 707 ret = rockchip_rk3399_pll_wait_lock(pll); 708 if (ret) { 709 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 710 __func__); 711 rockchip_rk3399_pll_set_params(pll, &cur); 712 } 713 714 if (rate_change_remuxed) 715 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 716 717 return ret; 718 } 719 720 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, 721 unsigned long prate) 722 { 723 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 724 const struct rockchip_pll_rate_table *rate; 725 726 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 727 __func__, __clk_get_name(hw->clk), drate, prate); 728 729 /* Get required rate settings from table */ 730 rate = rockchip_get_pll_settings(pll, drate); 731 if (!rate) { 732 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 733 drate, __clk_get_name(hw->clk)); 734 return -EINVAL; 735 } 736 737 return rockchip_rk3399_pll_set_params(pll, rate); 738 } 739 740 static int rockchip_rk3399_pll_enable(struct clk_hw *hw) 741 { 742 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 743 744 writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), 745 pll->reg_base + RK3399_PLLCON(3)); 746 rockchip_rk3399_pll_wait_lock(pll); 747 748 return 0; 749 } 750 751 static void rockchip_rk3399_pll_disable(struct clk_hw *hw) 752 { 753 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 754 755 writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, 756 RK3399_PLLCON3_PWRDOWN, 0), 757 pll->reg_base + RK3399_PLLCON(3)); 758 } 759 760 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw) 761 { 762 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 763 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); 764 765 return !(pllcon & RK3399_PLLCON3_PWRDOWN); 766 } 767 768 static int rockchip_rk3399_pll_init(struct clk_hw *hw) 769 { 770 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 771 const struct rockchip_pll_rate_table *rate; 772 struct rockchip_pll_rate_table cur; 773 unsigned long drate; 774 775 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 776 return 0; 777 778 drate = clk_hw_get_rate(hw); 779 rate = rockchip_get_pll_settings(pll, drate); 780 781 /* when no rate setting for the current rate, rely on clk_set_rate */ 782 if (!rate) 783 return 0; 784 785 rockchip_rk3399_pll_get_params(pll, &cur); 786 787 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), 788 drate); 789 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 790 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, 791 cur.dsmpd, cur.frac); 792 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 793 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, 794 rate->dsmpd, rate->frac); 795 796 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 797 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 798 rate->dsmpd != cur.dsmpd || 799 (!cur.dsmpd && (rate->frac != cur.frac))) { 800 struct clk *parent = clk_get_parent(hw->clk); 801 802 if (!parent) { 803 pr_warn("%s: parent of %s not available\n", 804 __func__, __clk_get_name(hw->clk)); 805 return 0; 806 } 807 808 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 809 __func__, __clk_get_name(hw->clk)); 810 rockchip_rk3399_pll_set_params(pll, rate); 811 } 812 813 return 0; 814 } 815 816 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = { 817 .recalc_rate = rockchip_rk3399_pll_recalc_rate, 818 .enable = rockchip_rk3399_pll_enable, 819 .disable = rockchip_rk3399_pll_disable, 820 .is_enabled = rockchip_rk3399_pll_is_enabled, 821 }; 822 823 static const struct clk_ops rockchip_rk3399_pll_clk_ops = { 824 .recalc_rate = rockchip_rk3399_pll_recalc_rate, 825 .round_rate = rockchip_pll_round_rate, 826 .set_rate = rockchip_rk3399_pll_set_rate, 827 .enable = rockchip_rk3399_pll_enable, 828 .disable = rockchip_rk3399_pll_disable, 829 .is_enabled = rockchip_rk3399_pll_is_enabled, 830 .init = rockchip_rk3399_pll_init, 831 }; 832 833 /* 834 * Common registering of pll clocks 835 */ 836 837 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, 838 enum rockchip_pll_type pll_type, 839 const char *name, const char *const *parent_names, 840 u8 num_parents, int con_offset, int grf_lock_offset, 841 int lock_shift, int mode_offset, int mode_shift, 842 struct rockchip_pll_rate_table *rate_table, 843 unsigned long flags, u8 clk_pll_flags) 844 { 845 const char *pll_parents[3]; 846 struct clk_init_data init; 847 struct rockchip_clk_pll *pll; 848 struct clk_mux *pll_mux; 849 struct clk *pll_clk, *mux_clk; 850 char pll_name[20]; 851 852 if ((pll_type != pll_rk3328 && num_parents != 2) || 853 (pll_type == pll_rk3328 && num_parents != 1)) { 854 pr_err("%s: needs two parent clocks\n", __func__); 855 return ERR_PTR(-EINVAL); 856 } 857 858 /* name the actual pll */ 859 snprintf(pll_name, sizeof(pll_name), "pll_%s", name); 860 861 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 862 if (!pll) 863 return ERR_PTR(-ENOMEM); 864 865 /* create the mux on top of the real pll */ 866 pll->pll_mux_ops = &clk_mux_ops; 867 pll_mux = &pll->pll_mux; 868 pll_mux->reg = ctx->reg_base + mode_offset; 869 pll_mux->shift = mode_shift; 870 if (pll_type == pll_rk3328) 871 pll_mux->mask = PLL_RK3328_MODE_MASK; 872 else 873 pll_mux->mask = PLL_MODE_MASK; 874 pll_mux->flags = 0; 875 pll_mux->lock = &ctx->lock; 876 pll_mux->hw.init = &init; 877 878 if (pll_type == pll_rk3036 || 879 pll_type == pll_rk3066 || 880 pll_type == pll_rk3328 || 881 pll_type == pll_rk3399) 882 pll_mux->flags |= CLK_MUX_HIWORD_MASK; 883 884 /* the actual muxing is xin24m, pll-output, xin32k */ 885 pll_parents[0] = parent_names[0]; 886 pll_parents[1] = pll_name; 887 pll_parents[2] = parent_names[1]; 888 889 init.name = name; 890 init.flags = CLK_SET_RATE_PARENT; 891 init.ops = pll->pll_mux_ops; 892 init.parent_names = pll_parents; 893 if (pll_type == pll_rk3328) 894 init.num_parents = 2; 895 else 896 init.num_parents = ARRAY_SIZE(pll_parents); 897 898 mux_clk = clk_register(NULL, &pll_mux->hw); 899 if (IS_ERR(mux_clk)) 900 goto err_mux; 901 902 /* now create the actual pll */ 903 init.name = pll_name; 904 905 /* keep all plls untouched for now */ 906 init.flags = flags | CLK_IGNORE_UNUSED; 907 908 init.parent_names = &parent_names[0]; 909 init.num_parents = 1; 910 911 if (rate_table) { 912 int len; 913 914 /* find count of rates in rate_table */ 915 for (len = 0; rate_table[len].rate != 0; ) 916 len++; 917 918 pll->rate_count = len; 919 pll->rate_table = kmemdup(rate_table, 920 pll->rate_count * 921 sizeof(struct rockchip_pll_rate_table), 922 GFP_KERNEL); 923 WARN(!pll->rate_table, 924 "%s: could not allocate rate table for %s\n", 925 __func__, name); 926 } 927 928 switch (pll_type) { 929 case pll_rk3036: 930 case pll_rk3328: 931 if (!pll->rate_table || IS_ERR(ctx->grf)) 932 init.ops = &rockchip_rk3036_pll_clk_norate_ops; 933 else 934 init.ops = &rockchip_rk3036_pll_clk_ops; 935 break; 936 case pll_rk3066: 937 if (!pll->rate_table || IS_ERR(ctx->grf)) 938 init.ops = &rockchip_rk3066_pll_clk_norate_ops; 939 else 940 init.ops = &rockchip_rk3066_pll_clk_ops; 941 break; 942 case pll_rk3399: 943 if (!pll->rate_table) 944 init.ops = &rockchip_rk3399_pll_clk_norate_ops; 945 else 946 init.ops = &rockchip_rk3399_pll_clk_ops; 947 break; 948 default: 949 pr_warn("%s: Unknown pll type for pll clk %s\n", 950 __func__, name); 951 } 952 953 pll->hw.init = &init; 954 pll->type = pll_type; 955 pll->reg_base = ctx->reg_base + con_offset; 956 pll->lock_offset = grf_lock_offset; 957 pll->lock_shift = lock_shift; 958 pll->flags = clk_pll_flags; 959 pll->lock = &ctx->lock; 960 pll->ctx = ctx; 961 962 pll_clk = clk_register(NULL, &pll->hw); 963 if (IS_ERR(pll_clk)) { 964 pr_err("%s: failed to register pll clock %s : %ld\n", 965 __func__, name, PTR_ERR(pll_clk)); 966 goto err_pll; 967 } 968 969 return mux_clk; 970 971 err_pll: 972 clk_unregister(mux_clk); 973 mux_clk = pll_clk; 974 err_mux: 975 kfree(pll); 976 return mux_clk; 977 } 978