1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 6 * Author: Xing Zheng <zhengxing@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <asm/div64.h> 20 #include <linux/slab.h> 21 #include <linux/io.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/regmap.h> 25 #include <linux/clk.h> 26 #include "clk.h" 27 28 #define PLL_MODE_MASK 0x3 29 #define PLL_MODE_SLOW 0x0 30 #define PLL_MODE_NORM 0x1 31 #define PLL_MODE_DEEP 0x2 32 33 struct rockchip_clk_pll { 34 struct clk_hw hw; 35 36 struct clk_mux pll_mux; 37 const struct clk_ops *pll_mux_ops; 38 39 struct notifier_block clk_nb; 40 41 void __iomem *reg_base; 42 int lock_offset; 43 unsigned int lock_shift; 44 enum rockchip_pll_type type; 45 u8 flags; 46 const struct rockchip_pll_rate_table *rate_table; 47 unsigned int rate_count; 48 spinlock_t *lock; 49 }; 50 51 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw) 52 #define to_rockchip_clk_pll_nb(nb) \ 53 container_of(nb, struct rockchip_clk_pll, clk_nb) 54 55 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings( 56 struct rockchip_clk_pll *pll, unsigned long rate) 57 { 58 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 59 int i; 60 61 for (i = 0; i < pll->rate_count; i++) { 62 if (rate == rate_table[i].rate) 63 return &rate_table[i]; 64 } 65 66 return NULL; 67 } 68 69 static long rockchip_pll_round_rate(struct clk_hw *hw, 70 unsigned long drate, unsigned long *prate) 71 { 72 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 73 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 74 int i; 75 76 /* Assumming rate_table is in descending order */ 77 for (i = 0; i < pll->rate_count; i++) { 78 if (drate >= rate_table[i].rate) 79 return rate_table[i].rate; 80 } 81 82 /* return minimum supported value */ 83 return rate_table[i - 1].rate; 84 } 85 86 /* 87 * Wait for the pll to reach the locked state. 88 * The calling set_rate function is responsible for making sure the 89 * grf regmap is available. 90 */ 91 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) 92 { 93 struct regmap *grf = rockchip_clk_get_grf(); 94 unsigned int val; 95 int delay = 24000000, ret; 96 97 if (IS_ERR(grf)) { 98 pr_err("%s: grf regmap not available\n", __func__); 99 return PTR_ERR(grf); 100 } 101 102 while (delay > 0) { 103 ret = regmap_read(grf, pll->lock_offset, &val); 104 if (ret) { 105 pr_err("%s: failed to read pll lock status: %d\n", 106 __func__, ret); 107 return ret; 108 } 109 110 if (val & BIT(pll->lock_shift)) 111 return 0; 112 delay--; 113 } 114 115 pr_err("%s: timeout waiting for pll to lock\n", __func__); 116 return -ETIMEDOUT; 117 } 118 119 /** 120 * PLL used in RK3036 121 */ 122 123 #define RK3036_PLLCON(i) (i * 0x4) 124 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 125 #define RK3036_PLLCON0_FBDIV_SHIFT 0 126 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 127 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 128 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 129 #define RK3036_PLLCON1_REFDIV_SHIFT 0 130 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 131 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 132 #define RK3036_PLLCON1_DSMPD_MASK 0x1 133 #define RK3036_PLLCON1_DSMPD_SHIFT 12 134 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 135 #define RK3036_PLLCON2_FRAC_SHIFT 0 136 137 #define RK3036_PLLCON1_PWRDOWN (1 << 13) 138 139 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, 140 struct rockchip_pll_rate_table *rate) 141 { 142 u32 pllcon; 143 144 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); 145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) 146 & RK3036_PLLCON0_FBDIV_MASK); 147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) 148 & RK3036_PLLCON0_POSTDIV1_MASK); 149 150 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); 151 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) 152 & RK3036_PLLCON1_REFDIV_MASK); 153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) 154 & RK3036_PLLCON1_POSTDIV2_MASK); 155 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) 156 & RK3036_PLLCON1_DSMPD_MASK); 157 158 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 159 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) 160 & RK3036_PLLCON2_FRAC_MASK); 161 } 162 163 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, 164 unsigned long prate) 165 { 166 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 167 struct rockchip_pll_rate_table cur; 168 u64 rate64 = prate; 169 170 rockchip_rk3036_pll_get_params(pll, &cur); 171 172 rate64 *= cur.fbdiv; 173 do_div(rate64, cur.refdiv); 174 175 if (cur.dsmpd == 0) { 176 /* fractional mode */ 177 u64 frac_rate64 = prate * cur.frac; 178 179 do_div(frac_rate64, cur.refdiv); 180 rate64 += frac_rate64 >> 24; 181 } 182 183 do_div(rate64, cur.postdiv1); 184 do_div(rate64, cur.postdiv2); 185 186 return (unsigned long)rate64; 187 } 188 189 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, 190 const struct rockchip_pll_rate_table *rate) 191 { 192 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 193 struct clk_mux *pll_mux = &pll->pll_mux; 194 struct rockchip_pll_rate_table cur; 195 u32 pllcon; 196 int rate_change_remuxed = 0; 197 int cur_parent; 198 int ret; 199 200 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, 202 rate->postdiv2, rate->dsmpd, rate->frac); 203 204 rockchip_rk3036_pll_get_params(pll, &cur); 205 cur.rate = 0; 206 207 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 208 if (cur_parent == PLL_MODE_NORM) { 209 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 210 rate_change_remuxed = 1; 211 } 212 213 /* update pll values */ 214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, 215 RK3036_PLLCON0_FBDIV_SHIFT) | 216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, 217 RK3036_PLLCON0_POSTDIV1_SHIFT), 218 pll->reg_base + RK3036_PLLCON(0)); 219 220 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, 221 RK3036_PLLCON1_REFDIV_SHIFT) | 222 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, 223 RK3036_PLLCON1_POSTDIV2_SHIFT) | 224 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, 225 RK3036_PLLCON1_DSMPD_SHIFT), 226 pll->reg_base + RK3036_PLLCON(1)); 227 228 /* GPLL CON2 is not HIWORD_MASK */ 229 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 230 pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT); 231 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; 232 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); 233 234 /* wait for the pll to lock */ 235 ret = rockchip_pll_wait_lock(pll); 236 if (ret) { 237 pr_warn("%s: pll update unsucessful, trying to restore old params\n", 238 __func__); 239 rockchip_rk3036_pll_set_params(pll, &cur); 240 } 241 242 if (rate_change_remuxed) 243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 244 245 return ret; 246 } 247 248 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, 249 unsigned long prate) 250 { 251 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 252 const struct rockchip_pll_rate_table *rate; 253 unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate); 254 struct regmap *grf = rockchip_clk_get_grf(); 255 256 if (IS_ERR(grf)) { 257 pr_debug("%s: grf regmap not available, aborting rate change\n", 258 __func__); 259 return PTR_ERR(grf); 260 } 261 262 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", 263 __func__, __clk_get_name(hw->clk), old_rate, drate, prate); 264 265 /* Get required rate settings from table */ 266 rate = rockchip_get_pll_settings(pll, drate); 267 if (!rate) { 268 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 269 drate, __clk_get_name(hw->clk)); 270 return -EINVAL; 271 } 272 273 return rockchip_rk3036_pll_set_params(pll, rate); 274 } 275 276 static int rockchip_rk3036_pll_enable(struct clk_hw *hw) 277 { 278 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 279 280 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), 281 pll->reg_base + RK3036_PLLCON(1)); 282 283 return 0; 284 } 285 286 static void rockchip_rk3036_pll_disable(struct clk_hw *hw) 287 { 288 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 289 290 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, 291 RK3036_PLLCON1_PWRDOWN, 0), 292 pll->reg_base + RK3036_PLLCON(1)); 293 } 294 295 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw) 296 { 297 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 298 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); 299 300 return !(pllcon & RK3036_PLLCON1_PWRDOWN); 301 } 302 303 static void rockchip_rk3036_pll_init(struct clk_hw *hw) 304 { 305 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 306 const struct rockchip_pll_rate_table *rate; 307 struct rockchip_pll_rate_table cur; 308 unsigned long drate; 309 310 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 311 return; 312 313 drate = clk_hw_get_rate(hw); 314 rate = rockchip_get_pll_settings(pll, drate); 315 316 /* when no rate setting for the current rate, rely on clk_set_rate */ 317 if (!rate) 318 return; 319 320 rockchip_rk3036_pll_get_params(pll, &cur); 321 322 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), 323 drate); 324 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 325 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, 326 cur.dsmpd, cur.frac); 327 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 328 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, 329 rate->dsmpd, rate->frac); 330 331 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 332 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 333 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) { 334 struct clk *parent = clk_get_parent(hw->clk); 335 336 if (!parent) { 337 pr_warn("%s: parent of %s not available\n", 338 __func__, __clk_get_name(hw->clk)); 339 return; 340 } 341 342 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 343 __func__, __clk_get_name(hw->clk)); 344 rockchip_rk3036_pll_set_params(pll, rate); 345 } 346 } 347 348 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { 349 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 350 .enable = rockchip_rk3036_pll_enable, 351 .disable = rockchip_rk3036_pll_disable, 352 .is_enabled = rockchip_rk3036_pll_is_enabled, 353 }; 354 355 static const struct clk_ops rockchip_rk3036_pll_clk_ops = { 356 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 357 .round_rate = rockchip_pll_round_rate, 358 .set_rate = rockchip_rk3036_pll_set_rate, 359 .enable = rockchip_rk3036_pll_enable, 360 .disable = rockchip_rk3036_pll_disable, 361 .is_enabled = rockchip_rk3036_pll_is_enabled, 362 .init = rockchip_rk3036_pll_init, 363 }; 364 365 /** 366 * PLL used in RK3066, RK3188 and RK3288 367 */ 368 369 #define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1) 370 371 #define RK3066_PLLCON(i) (i * 0x4) 372 #define RK3066_PLLCON0_OD_MASK 0xf 373 #define RK3066_PLLCON0_OD_SHIFT 0 374 #define RK3066_PLLCON0_NR_MASK 0x3f 375 #define RK3066_PLLCON0_NR_SHIFT 8 376 #define RK3066_PLLCON1_NF_MASK 0x1fff 377 #define RK3066_PLLCON1_NF_SHIFT 0 378 #define RK3066_PLLCON2_NB_MASK 0xfff 379 #define RK3066_PLLCON2_NB_SHIFT 0 380 #define RK3066_PLLCON3_RESET (1 << 5) 381 #define RK3066_PLLCON3_PWRDOWN (1 << 1) 382 #define RK3066_PLLCON3_BYPASS (1 << 0) 383 384 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, 385 struct rockchip_pll_rate_table *rate) 386 { 387 u32 pllcon; 388 389 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); 390 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) 391 & RK3066_PLLCON0_NR_MASK) + 1; 392 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) 393 & RK3066_PLLCON0_OD_MASK) + 1; 394 395 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); 396 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) 397 & RK3066_PLLCON1_NF_MASK) + 1; 398 399 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); 400 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) 401 & RK3066_PLLCON2_NB_MASK) + 1; 402 } 403 404 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, 405 unsigned long prate) 406 { 407 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 408 struct rockchip_pll_rate_table cur; 409 u64 rate64 = prate; 410 u32 pllcon; 411 412 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); 413 if (pllcon & RK3066_PLLCON3_BYPASS) { 414 pr_debug("%s: pll %s is bypassed\n", __func__, 415 clk_hw_get_name(hw)); 416 return prate; 417 } 418 419 rockchip_rk3066_pll_get_params(pll, &cur); 420 421 rate64 *= cur.nf; 422 do_div(rate64, cur.nr); 423 do_div(rate64, cur.no); 424 425 return (unsigned long)rate64; 426 } 427 428 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, 429 const struct rockchip_pll_rate_table *rate) 430 { 431 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 432 struct clk_mux *pll_mux = &pll->pll_mux; 433 struct rockchip_pll_rate_table cur; 434 int rate_change_remuxed = 0; 435 int cur_parent; 436 int ret; 437 438 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", 439 __func__, rate->rate, rate->nr, rate->no, rate->nf); 440 441 rockchip_rk3066_pll_get_params(pll, &cur); 442 cur.rate = 0; 443 444 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 445 if (cur_parent == PLL_MODE_NORM) { 446 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 447 rate_change_remuxed = 1; 448 } 449 450 /* enter reset mode */ 451 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), 452 pll->reg_base + RK3066_PLLCON(3)); 453 454 /* update pll values */ 455 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, 456 RK3066_PLLCON0_NR_SHIFT) | 457 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, 458 RK3066_PLLCON0_OD_SHIFT), 459 pll->reg_base + RK3066_PLLCON(0)); 460 461 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, 462 RK3066_PLLCON1_NF_SHIFT), 463 pll->reg_base + RK3066_PLLCON(1)); 464 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, 465 RK3066_PLLCON2_NB_SHIFT), 466 pll->reg_base + RK3066_PLLCON(2)); 467 468 /* leave reset and wait the reset_delay */ 469 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), 470 pll->reg_base + RK3066_PLLCON(3)); 471 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); 472 473 /* wait for the pll to lock */ 474 ret = rockchip_pll_wait_lock(pll); 475 if (ret) { 476 pr_warn("%s: pll update unsucessful, trying to restore old params\n", 477 __func__); 478 rockchip_rk3066_pll_set_params(pll, &cur); 479 } 480 481 if (rate_change_remuxed) 482 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 483 484 return ret; 485 } 486 487 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, 488 unsigned long prate) 489 { 490 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 491 const struct rockchip_pll_rate_table *rate; 492 unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); 493 struct regmap *grf = rockchip_clk_get_grf(); 494 495 if (IS_ERR(grf)) { 496 pr_debug("%s: grf regmap not available, aborting rate change\n", 497 __func__); 498 return PTR_ERR(grf); 499 } 500 501 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", 502 __func__, clk_hw_get_name(hw), old_rate, drate, prate); 503 504 /* Get required rate settings from table */ 505 rate = rockchip_get_pll_settings(pll, drate); 506 if (!rate) { 507 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 508 drate, clk_hw_get_name(hw)); 509 return -EINVAL; 510 } 511 512 return rockchip_rk3066_pll_set_params(pll, rate); 513 } 514 515 static int rockchip_rk3066_pll_enable(struct clk_hw *hw) 516 { 517 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 518 519 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), 520 pll->reg_base + RK3066_PLLCON(3)); 521 522 return 0; 523 } 524 525 static void rockchip_rk3066_pll_disable(struct clk_hw *hw) 526 { 527 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 528 529 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN, 530 RK3066_PLLCON3_PWRDOWN, 0), 531 pll->reg_base + RK3066_PLLCON(3)); 532 } 533 534 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw) 535 { 536 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 537 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); 538 539 return !(pllcon & RK3066_PLLCON3_PWRDOWN); 540 } 541 542 static void rockchip_rk3066_pll_init(struct clk_hw *hw) 543 { 544 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 545 const struct rockchip_pll_rate_table *rate; 546 struct rockchip_pll_rate_table cur; 547 unsigned long drate; 548 549 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 550 return; 551 552 drate = clk_hw_get_rate(hw); 553 rate = rockchip_get_pll_settings(pll, drate); 554 555 /* when no rate setting for the current rate, rely on clk_set_rate */ 556 if (!rate) 557 return; 558 559 rockchip_rk3066_pll_get_params(pll, &cur); 560 561 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", 562 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, 563 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); 564 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf 565 || rate->nb != cur.nb) { 566 struct regmap *grf = rockchip_clk_get_grf(); 567 568 if (IS_ERR(grf)) 569 return; 570 571 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 572 __func__, clk_hw_get_name(hw)); 573 rockchip_rk3066_pll_set_params(pll, rate); 574 } 575 } 576 577 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { 578 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 579 .enable = rockchip_rk3066_pll_enable, 580 .disable = rockchip_rk3066_pll_disable, 581 .is_enabled = rockchip_rk3066_pll_is_enabled, 582 }; 583 584 static const struct clk_ops rockchip_rk3066_pll_clk_ops = { 585 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 586 .round_rate = rockchip_pll_round_rate, 587 .set_rate = rockchip_rk3066_pll_set_rate, 588 .enable = rockchip_rk3066_pll_enable, 589 .disable = rockchip_rk3066_pll_disable, 590 .is_enabled = rockchip_rk3066_pll_is_enabled, 591 .init = rockchip_rk3066_pll_init, 592 }; 593 594 /* 595 * Common registering of pll clocks 596 */ 597 598 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, 599 const char *name, const char *const *parent_names, 600 u8 num_parents, void __iomem *base, int con_offset, 601 int grf_lock_offset, int lock_shift, int mode_offset, 602 int mode_shift, struct rockchip_pll_rate_table *rate_table, 603 u8 clk_pll_flags, spinlock_t *lock) 604 { 605 const char *pll_parents[3]; 606 struct clk_init_data init; 607 struct rockchip_clk_pll *pll; 608 struct clk_mux *pll_mux; 609 struct clk *pll_clk, *mux_clk; 610 char pll_name[20]; 611 612 if (num_parents != 2) { 613 pr_err("%s: needs two parent clocks\n", __func__); 614 return ERR_PTR(-EINVAL); 615 } 616 617 /* name the actual pll */ 618 snprintf(pll_name, sizeof(pll_name), "pll_%s", name); 619 620 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 621 if (!pll) 622 return ERR_PTR(-ENOMEM); 623 624 /* create the mux on top of the real pll */ 625 pll->pll_mux_ops = &clk_mux_ops; 626 pll_mux = &pll->pll_mux; 627 pll_mux->reg = base + mode_offset; 628 pll_mux->shift = mode_shift; 629 pll_mux->mask = PLL_MODE_MASK; 630 pll_mux->flags = 0; 631 pll_mux->lock = lock; 632 pll_mux->hw.init = &init; 633 634 if (pll_type == pll_rk3036 || pll_type == pll_rk3066) 635 pll_mux->flags |= CLK_MUX_HIWORD_MASK; 636 637 /* the actual muxing is xin24m, pll-output, xin32k */ 638 pll_parents[0] = parent_names[0]; 639 pll_parents[1] = pll_name; 640 pll_parents[2] = parent_names[1]; 641 642 init.name = name; 643 init.flags = CLK_SET_RATE_PARENT; 644 init.ops = pll->pll_mux_ops; 645 init.parent_names = pll_parents; 646 init.num_parents = ARRAY_SIZE(pll_parents); 647 648 mux_clk = clk_register(NULL, &pll_mux->hw); 649 if (IS_ERR(mux_clk)) 650 goto err_mux; 651 652 /* now create the actual pll */ 653 init.name = pll_name; 654 655 /* keep all plls untouched for now */ 656 init.flags = CLK_IGNORE_UNUSED; 657 658 init.parent_names = &parent_names[0]; 659 init.num_parents = 1; 660 661 if (rate_table) { 662 int len; 663 664 /* find count of rates in rate_table */ 665 for (len = 0; rate_table[len].rate != 0; ) 666 len++; 667 668 pll->rate_count = len; 669 pll->rate_table = kmemdup(rate_table, 670 pll->rate_count * 671 sizeof(struct rockchip_pll_rate_table), 672 GFP_KERNEL); 673 WARN(!pll->rate_table, 674 "%s: could not allocate rate table for %s\n", 675 __func__, name); 676 } 677 678 switch (pll_type) { 679 case pll_rk3036: 680 if (!pll->rate_table) 681 init.ops = &rockchip_rk3036_pll_clk_norate_ops; 682 else 683 init.ops = &rockchip_rk3036_pll_clk_ops; 684 break; 685 case pll_rk3066: 686 if (!pll->rate_table) 687 init.ops = &rockchip_rk3066_pll_clk_norate_ops; 688 else 689 init.ops = &rockchip_rk3066_pll_clk_ops; 690 break; 691 default: 692 pr_warn("%s: Unknown pll type for pll clk %s\n", 693 __func__, name); 694 } 695 696 pll->hw.init = &init; 697 pll->type = pll_type; 698 pll->reg_base = base + con_offset; 699 pll->lock_offset = grf_lock_offset; 700 pll->lock_shift = lock_shift; 701 pll->flags = clk_pll_flags; 702 pll->lock = lock; 703 704 pll_clk = clk_register(NULL, &pll->hw); 705 if (IS_ERR(pll_clk)) { 706 pr_err("%s: failed to register pll clock %s : %ld\n", 707 __func__, name, PTR_ERR(pll_clk)); 708 goto err_pll; 709 } 710 711 return mux_clk; 712 713 err_pll: 714 clk_unregister(mux_clk); 715 mux_clk = pll_clk; 716 err_mux: 717 kfree(pll); 718 return mux_clk; 719 } 720