1 /* 2 * Copyright 2014 Google, Inc 3 * Author: Alexandru M Stan <amstan@chromium.org> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/slab.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include "clk.h" 22 23 struct rockchip_mmc_clock { 24 struct clk_hw hw; 25 void __iomem *reg; 26 int id; 27 int shift; 28 }; 29 30 #define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw) 31 32 #define RK3288_MMC_CLKGEN_DIV 2 33 34 static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, 35 unsigned long parent_rate) 36 { 37 return parent_rate / RK3288_MMC_CLKGEN_DIV; 38 } 39 40 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 41 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 42 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 43 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 44 #define ROCKCHIP_MMC_INIT_STATE_RESET 0x1 45 #define ROCKCHIP_MMC_INIT_STATE_SHIFT 1 46 47 #define PSECS_PER_SEC 1000000000000LL 48 49 /* 50 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 51 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 52 */ 53 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 54 55 static int rockchip_mmc_get_phase(struct clk_hw *hw) 56 { 57 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); 58 unsigned long rate = clk_get_rate(hw->clk); 59 u32 raw_value; 60 u16 degrees; 61 u32 delay_num = 0; 62 63 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); 64 65 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 66 67 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 68 /* degrees/delaynum * 10000 */ 69 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 70 36 * (rate / 1000000); 71 72 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 73 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 74 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 75 } 76 77 return degrees % 360; 78 } 79 80 static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) 81 { 82 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw); 83 unsigned long rate = clk_get_rate(hw->clk); 84 u8 nineties, remainder; 85 u8 delay_num; 86 u32 raw_value; 87 u32 delay; 88 89 nineties = degrees / 90; 90 remainder = (degrees % 90); 91 92 /* 93 * Due to the inexact nature of the "fine" delay, we might 94 * actually go non-monotonic. We don't go _too_ monotonic 95 * though, so we should be OK. Here are options of how we may 96 * work: 97 * 98 * Ideally we end up with: 99 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0 100 * 101 * On one extreme (if delay is actually 44ps): 102 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0 103 * The other (if delay is actually 77ps): 104 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90 105 * 106 * It's possible we might make a delay that is up to 25 107 * degrees off from what we think we're making. That's OK 108 * though because we should be REALLY far from any bad range. 109 */ 110 111 /* 112 * Convert to delay; do a little extra work to make sure we 113 * don't overflow 32-bit / 64-bit numbers. 114 */ 115 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 116 delay *= remainder; 117 delay = DIV_ROUND_CLOSEST(delay, 118 (rate / 1000) * 36 * 119 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 120 121 delay_num = (u8) min_t(u32, delay, 255); 122 123 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 124 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 125 raw_value |= nineties; 126 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), 127 mmc_clock->reg); 128 129 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", 130 clk_hw_get_name(hw), degrees, delay_num, 131 mmc_clock->reg, raw_value>>(mmc_clock->shift), 132 rockchip_mmc_get_phase(hw) 133 ); 134 135 return 0; 136 } 137 138 static const struct clk_ops rockchip_mmc_clk_ops = { 139 .recalc_rate = rockchip_mmc_recalc, 140 .get_phase = rockchip_mmc_get_phase, 141 .set_phase = rockchip_mmc_set_phase, 142 }; 143 144 struct clk *rockchip_clk_register_mmc(const char *name, 145 const char *const *parent_names, u8 num_parents, 146 void __iomem *reg, int shift) 147 { 148 struct clk_init_data init; 149 struct rockchip_mmc_clock *mmc_clock; 150 struct clk *clk; 151 152 mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL); 153 if (!mmc_clock) 154 return ERR_PTR(-ENOMEM); 155 156 init.name = name; 157 init.num_parents = num_parents; 158 init.parent_names = parent_names; 159 init.ops = &rockchip_mmc_clk_ops; 160 161 mmc_clock->hw.init = &init; 162 mmc_clock->reg = reg; 163 mmc_clock->shift = shift; 164 165 /* 166 * Assert init_state to soft reset the CLKGEN 167 * for mmc tuning phase and degree 168 */ 169 if (mmc_clock->shift == ROCKCHIP_MMC_INIT_STATE_SHIFT) 170 writel(HIWORD_UPDATE(ROCKCHIP_MMC_INIT_STATE_RESET, 171 ROCKCHIP_MMC_INIT_STATE_RESET, 172 mmc_clock->shift), mmc_clock->reg); 173 174 clk = clk_register(NULL, &mmc_clock->hw); 175 if (IS_ERR(clk)) 176 kfree(mmc_clock); 177 178 return clk; 179 } 180