1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * based on clk/samsung/clk-cpu.c 7 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 8 * Author: Thomas Abraham <thomas.ab@samsung.com> 9 * 10 * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs. 11 * The CPU clock is typically derived from a hierarchy of clock 12 * blocks which includes mux and divider blocks. There are a number of other 13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI 14 * clock for CPU domain. The rates of these auxiliary clocks are related to the 15 * CPU clock rate and this relation is usually specified in the hardware manual 16 * of the SoC or supplied after the SoC characterization. 17 * 18 * The below implementation of the CPU clock allows the rate changes of the CPU 19 * clock and the corresponding rate changes of the auxillary clocks of the CPU 20 * domain. The platform clock driver provides a clock register configuration 21 * for each configurable rate which is then used to program the clock hardware 22 * registers to acheive a fast co-oridinated rate change for all the CPU domain 23 * clocks. 24 * 25 * On a rate change request for the CPU clock, the rate change is propagated 26 * upto the PLL supplying the clock to the CPU domain clock blocks. While the 27 * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an 28 * alternate clock source. If required, the alternate clock source is divided 29 * down in order to keep the output clock rate within the previous OPP limits. 30 */ 31 32 #include <linux/of.h> 33 #include <linux/slab.h> 34 #include <linux/io.h> 35 #include <linux/clk.h> 36 #include <linux/clk-provider.h> 37 #include "clk.h" 38 39 /** 40 * struct rockchip_cpuclk: information about clock supplied to a CPU core. 41 * @hw: handle between ccf and cpu clock. 42 * @alt_parent: alternate parent clock to use when switching the speed 43 * of the primary parent clock. 44 * @reg_base: base register for cpu-clock values. 45 * @clk_nb: clock notifier registered for changes in clock speed of the 46 * primary parent clock. 47 * @rate_count: number of rates in the rate_table 48 * @rate_table: pll-rates and their associated dividers 49 * @reg_data: cpu-specific register settings 50 * @lock: clock lock 51 */ 52 struct rockchip_cpuclk { 53 struct clk_hw hw; 54 struct clk *alt_parent; 55 void __iomem *reg_base; 56 struct notifier_block clk_nb; 57 unsigned int rate_count; 58 struct rockchip_cpuclk_rate_table *rate_table; 59 const struct rockchip_cpuclk_reg_data *reg_data; 60 spinlock_t *lock; 61 }; 62 63 #define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw) 64 #define to_rockchip_cpuclk_nb(nb) \ 65 container_of(nb, struct rockchip_cpuclk, clk_nb) 66 67 static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings( 68 struct rockchip_cpuclk *cpuclk, unsigned long rate) 69 { 70 const struct rockchip_cpuclk_rate_table *rate_table = 71 cpuclk->rate_table; 72 int i; 73 74 for (i = 0; i < cpuclk->rate_count; i++) { 75 if (rate == rate_table[i].prate) 76 return &rate_table[i]; 77 } 78 79 return NULL; 80 } 81 82 static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw, 83 unsigned long parent_rate) 84 { 85 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); 86 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; 87 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); 88 89 clksel0 >>= reg_data->div_core_shift; 90 clksel0 &= reg_data->div_core_mask; 91 return parent_rate / (clksel0 + 1); 92 } 93 94 static const struct clk_ops rockchip_cpuclk_ops = { 95 .recalc_rate = rockchip_cpuclk_recalc_rate, 96 }; 97 98 static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, 99 const struct rockchip_cpuclk_rate_table *rate) 100 { 101 int i; 102 103 /* alternate parent is active now. set the dividers */ 104 for (i = 0; i < ARRAY_SIZE(rate->divs); i++) { 105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; 106 107 if (!clksel->reg) 108 continue; 109 110 pr_debug("%s: setting reg 0x%x to 0x%x\n", 111 __func__, clksel->reg, clksel->val); 112 writel(clksel->val, cpuclk->reg_base + clksel->reg); 113 } 114 } 115 116 static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, 117 struct clk_notifier_data *ndata) 118 { 119 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; 120 const struct rockchip_cpuclk_rate_table *rate; 121 unsigned long alt_prate, alt_div; 122 unsigned long flags; 123 124 /* check validity of the new rate */ 125 rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate); 126 if (!rate) { 127 pr_err("%s: Invalid rate : %lu for cpuclk\n", 128 __func__, ndata->new_rate); 129 return -EINVAL; 130 } 131 132 alt_prate = clk_get_rate(cpuclk->alt_parent); 133 134 spin_lock_irqsave(cpuclk->lock, flags); 135 136 /* 137 * If the old parent clock speed is less than the clock speed 138 * of the alternate parent, then it should be ensured that at no point 139 * the armclk speed is more than the old_rate until the dividers are 140 * set. 141 */ 142 if (alt_prate > ndata->old_rate) { 143 /* calculate dividers */ 144 alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1; 145 if (alt_div > reg_data->div_core_mask) { 146 pr_warn("%s: limiting alt-divider %lu to %d\n", 147 __func__, alt_div, reg_data->div_core_mask); 148 alt_div = reg_data->div_core_mask; 149 } 150 151 /* 152 * Change parents and add dividers in a single transaction. 153 * 154 * NOTE: we do this in a single transaction so we're never 155 * dividing the primary parent by the extra dividers that were 156 * needed for the alt. 157 */ 158 pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n", 159 __func__, alt_div, alt_prate, ndata->old_rate); 160 161 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, 162 reg_data->div_core_shift) | 163 HIWORD_UPDATE(reg_data->mux_core_alt, 164 reg_data->mux_core_mask, 165 reg_data->mux_core_shift), 166 cpuclk->reg_base + reg_data->core_reg); 167 } else { 168 /* select alternate parent */ 169 writel(HIWORD_UPDATE(reg_data->mux_core_alt, 170 reg_data->mux_core_mask, 171 reg_data->mux_core_shift), 172 cpuclk->reg_base + reg_data->core_reg); 173 } 174 175 spin_unlock_irqrestore(cpuclk->lock, flags); 176 return 0; 177 } 178 179 static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, 180 struct clk_notifier_data *ndata) 181 { 182 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; 183 const struct rockchip_cpuclk_rate_table *rate; 184 unsigned long flags; 185 186 rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate); 187 if (!rate) { 188 pr_err("%s: Invalid rate : %lu for cpuclk\n", 189 __func__, ndata->new_rate); 190 return -EINVAL; 191 } 192 193 spin_lock_irqsave(cpuclk->lock, flags); 194 195 if (ndata->old_rate < ndata->new_rate) 196 rockchip_cpuclk_set_dividers(cpuclk, rate); 197 198 /* 199 * post-rate change event, re-mux to primary parent and remove dividers. 200 * 201 * NOTE: we do this in a single transaction so we're never dividing the 202 * primary parent by the extra dividers that were needed for the alt. 203 */ 204 205 writel(HIWORD_UPDATE(0, reg_data->div_core_mask, 206 reg_data->div_core_shift) | 207 HIWORD_UPDATE(reg_data->mux_core_main, 208 reg_data->mux_core_mask, 209 reg_data->mux_core_shift), 210 cpuclk->reg_base + reg_data->core_reg); 211 212 if (ndata->old_rate > ndata->new_rate) 213 rockchip_cpuclk_set_dividers(cpuclk, rate); 214 215 spin_unlock_irqrestore(cpuclk->lock, flags); 216 return 0; 217 } 218 219 /* 220 * This clock notifier is called when the frequency of the parent clock 221 * of cpuclk is to be changed. This notifier handles the setting up all 222 * the divider clocks, remux to temporary parent and handling the safe 223 * frequency levels when using temporary parent. 224 */ 225 static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb, 226 unsigned long event, void *data) 227 { 228 struct clk_notifier_data *ndata = data; 229 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb); 230 int ret = 0; 231 232 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", 233 __func__, event, ndata->old_rate, ndata->new_rate); 234 if (event == PRE_RATE_CHANGE) 235 ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata); 236 else if (event == POST_RATE_CHANGE) 237 ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata); 238 239 return notifier_from_errno(ret); 240 } 241 242 struct clk *rockchip_clk_register_cpuclk(const char *name, 243 const char *const *parent_names, u8 num_parents, 244 const struct rockchip_cpuclk_reg_data *reg_data, 245 const struct rockchip_cpuclk_rate_table *rates, 246 int nrates, void __iomem *reg_base, spinlock_t *lock) 247 { 248 struct rockchip_cpuclk *cpuclk; 249 struct clk_init_data init; 250 struct clk *clk, *cclk; 251 int ret; 252 253 if (num_parents < 2) { 254 pr_err("%s: needs at least two parent clocks\n", __func__); 255 return ERR_PTR(-EINVAL); 256 } 257 258 cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); 259 if (!cpuclk) 260 return ERR_PTR(-ENOMEM); 261 262 init.name = name; 263 init.parent_names = &parent_names[reg_data->mux_core_main]; 264 init.num_parents = 1; 265 init.ops = &rockchip_cpuclk_ops; 266 267 /* only allow rate changes when we have a rate table */ 268 init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; 269 270 /* disallow automatic parent changes by ccf */ 271 init.flags |= CLK_SET_RATE_NO_REPARENT; 272 273 init.flags |= CLK_GET_RATE_NOCACHE; 274 275 cpuclk->reg_base = reg_base; 276 cpuclk->lock = lock; 277 cpuclk->reg_data = reg_data; 278 cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb; 279 cpuclk->hw.init = &init; 280 281 cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]); 282 if (!cpuclk->alt_parent) { 283 pr_err("%s: could not lookup alternate parent: (%d)\n", 284 __func__, reg_data->mux_core_alt); 285 ret = -EINVAL; 286 goto free_cpuclk; 287 } 288 289 ret = clk_prepare_enable(cpuclk->alt_parent); 290 if (ret) { 291 pr_err("%s: could not enable alternate parent\n", 292 __func__); 293 goto free_cpuclk; 294 } 295 296 clk = __clk_lookup(parent_names[reg_data->mux_core_main]); 297 if (!clk) { 298 pr_err("%s: could not lookup parent clock: (%d) %s\n", 299 __func__, reg_data->mux_core_main, 300 parent_names[reg_data->mux_core_main]); 301 ret = -EINVAL; 302 goto free_alt_parent; 303 } 304 305 ret = clk_notifier_register(clk, &cpuclk->clk_nb); 306 if (ret) { 307 pr_err("%s: failed to register clock notifier for %s\n", 308 __func__, name); 309 goto free_alt_parent; 310 } 311 312 if (nrates > 0) { 313 cpuclk->rate_count = nrates; 314 cpuclk->rate_table = kmemdup(rates, 315 sizeof(*rates) * nrates, 316 GFP_KERNEL); 317 if (!cpuclk->rate_table) { 318 ret = -ENOMEM; 319 goto unregister_notifier; 320 } 321 } 322 323 cclk = clk_register(NULL, &cpuclk->hw); 324 if (IS_ERR(cclk)) { 325 pr_err("%s: could not register cpuclk %s\n", __func__, name); 326 ret = PTR_ERR(cclk); 327 goto free_rate_table; 328 } 329 330 return cclk; 331 332 free_rate_table: 333 kfree(cpuclk->rate_table); 334 unregister_notifier: 335 clk_notifier_unregister(clk, &cpuclk->clk_nb); 336 free_alt_parent: 337 clk_disable_unprepare(cpuclk->alt_parent); 338 free_cpuclk: 339 kfree(cpuclk); 340 return ERR_PTR(ret); 341 } 342