1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __RENESAS_RZG2L_CPG_H__ 10 #define __RENESAS_RZG2L_CPG_H__ 11 12 #define CPG_PL2_DDIV (0x204) 13 #define CPG_PL3A_DDIV (0x208) 14 15 /* n = 0/1/2 for PLL1/4/6 */ 16 #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) 17 #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) 18 19 #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) 20 21 #define DDIV_PACK(offset, bitpos, size) \ 22 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 23 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) 24 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) 25 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) 26 27 /** 28 * Definitions of CPG Core Clocks 29 * 30 * These include: 31 * - Clock outputs exported to DT 32 * - External input clocks 33 * - Internal CPG clocks 34 */ 35 struct cpg_core_clk { 36 const char *name; 37 unsigned int id; 38 unsigned int parent; 39 unsigned int div; 40 unsigned int mult; 41 unsigned int type; 42 unsigned int conf; 43 const struct clk_div_table *dtable; 44 const char * const *parent_names; 45 int flag; 46 int num_parents; 47 }; 48 49 enum clk_types { 50 /* Generic */ 51 CLK_TYPE_IN, /* External Clock Input */ 52 CLK_TYPE_FF, /* Fixed Factor Clock */ 53 CLK_TYPE_SAM_PLL, 54 55 /* Clock with divider */ 56 CLK_TYPE_DIV, 57 }; 58 59 #define DEF_TYPE(_name, _id, _type...) \ 60 { .name = _name, .id = _id, .type = _type } 61 #define DEF_BASE(_name, _id, _type, _parent...) \ 62 DEF_TYPE(_name, _id, _type, .parent = _parent) 63 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 64 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 65 #define DEF_INPUT(_name, _id) \ 66 DEF_TYPE(_name, _id, CLK_TYPE_IN) 67 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 68 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 69 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ 70 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 71 .parent = _parent, .dtable = _dtable, .flag = _flag) 72 73 /** 74 * struct rzg2l_mod_clk - Module Clocks definitions 75 * 76 * @name: handle between common and hardware-specific interfaces 77 * @id: clock index in array containing all Core and Module Clocks 78 * @parent: id of parent clock 79 * @off: register offset 80 * @bit: ON/MON bit 81 */ 82 struct rzg2l_mod_clk { 83 const char *name; 84 unsigned int id; 85 unsigned int parent; 86 u16 off; 87 u8 bit; 88 }; 89 90 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ 91 { \ 92 .name = _name, \ 93 .id = MOD_CLK_BASE + (_id), \ 94 .parent = (_parent), \ 95 .off = (_off), \ 96 .bit = (_bit), \ 97 } 98 99 /** 100 * struct rzg2l_reset - Reset definitions 101 * 102 * @off: register offset 103 * @bit: reset bit 104 */ 105 struct rzg2l_reset { 106 u16 off; 107 u8 bit; 108 }; 109 110 #define DEF_RST(_id, _off, _bit) \ 111 [_id] = { \ 112 .off = (_off), \ 113 .bit = (_bit) \ 114 } 115 116 /** 117 * struct rzg2l_cpg_info - SoC-specific CPG Description 118 * 119 * @core_clks: Array of Core Clock definitions 120 * @num_core_clks: Number of entries in core_clks[] 121 * @last_dt_core_clk: ID of the last Core Clock exported to DT 122 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 123 * 124 * @mod_clks: Array of Module Clock definitions 125 * @num_mod_clks: Number of entries in mod_clks[] 126 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 127 * 128 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 129 * should not be disabled without a knowledgeable driver 130 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 131 */ 132 struct rzg2l_cpg_info { 133 /* Core Clocks */ 134 const struct cpg_core_clk *core_clks; 135 unsigned int num_core_clks; 136 unsigned int last_dt_core_clk; 137 unsigned int num_total_core_clks; 138 139 /* Module Clocks */ 140 const struct rzg2l_mod_clk *mod_clks; 141 unsigned int num_mod_clks; 142 unsigned int num_hw_mod_clks; 143 144 /* Resets */ 145 const struct rzg2l_reset *resets; 146 unsigned int num_resets; 147 148 /* Critical Module Clocks that should not be disabled */ 149 const unsigned int *crit_mod_clks; 150 unsigned int num_crit_mod_clks; 151 }; 152 153 extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 154 155 #endif 156