1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __RENESAS_RZG2L_CPG_H__ 10 #define __RENESAS_RZG2L_CPG_H__ 11 12 #define CPG_PL1_DDIV (0x200) 13 #define CPG_PL2_DDIV (0x204) 14 #define CPG_PL3A_DDIV (0x208) 15 #define CPG_PL6_DDIV (0x210) 16 #define CPG_PL2SDHI_DSEL (0x218) 17 #define CPG_CLKSTATUS (0x280) 18 #define CPG_PL3_SSEL (0x408) 19 #define CPG_PL6_SSEL (0x414) 20 #define CPG_PL6_ETH_SSEL (0x418) 21 22 #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) 23 #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) 24 25 #define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000 26 27 /* n = 0/1/2 for PLL1/4/6 */ 28 #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) 29 #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) 30 31 #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) 32 33 #define DDIV_PACK(offset, bitpos, size) \ 34 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 35 #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) 36 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) 37 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) 38 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) 39 #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) 40 #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) 41 42 #define SEL_PLL_PACK(offset, bitpos, size) \ 43 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 44 45 #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) 46 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) 47 #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) 48 49 #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) 50 #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) 51 52 /** 53 * Definitions of CPG Core Clocks 54 * 55 * These include: 56 * - Clock outputs exported to DT 57 * - External input clocks 58 * - Internal CPG clocks 59 */ 60 struct cpg_core_clk { 61 const char *name; 62 unsigned int id; 63 unsigned int parent; 64 unsigned int div; 65 unsigned int mult; 66 unsigned int type; 67 unsigned int conf; 68 const struct clk_div_table *dtable; 69 const char * const *parent_names; 70 int flag; 71 int mux_flags; 72 int num_parents; 73 }; 74 75 enum clk_types { 76 /* Generic */ 77 CLK_TYPE_IN, /* External Clock Input */ 78 CLK_TYPE_FF, /* Fixed Factor Clock */ 79 CLK_TYPE_SAM_PLL, 80 81 /* Clock with divider */ 82 CLK_TYPE_DIV, 83 84 /* Clock with clock source selector */ 85 CLK_TYPE_MUX, 86 87 /* Clock with SD clock source selector */ 88 CLK_TYPE_SD_MUX, 89 }; 90 91 #define DEF_TYPE(_name, _id, _type...) \ 92 { .name = _name, .id = _id, .type = _type } 93 #define DEF_BASE(_name, _id, _type, _parent...) \ 94 DEF_TYPE(_name, _id, _type, .parent = _parent) 95 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 96 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 97 #define DEF_INPUT(_name, _id) \ 98 DEF_TYPE(_name, _id, CLK_TYPE_IN) 99 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 100 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 101 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ 102 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 103 .parent = _parent, .dtable = _dtable, .flag = _flag) 104 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \ 105 _mux_flags) \ 106 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 107 .parent_names = _parent_names, .num_parents = _num_parents, \ 108 .flag = _flag, .mux_flags = _mux_flags) 109 #define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \ 110 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ 111 .parent_names = _parent_names, .num_parents = _num_parents) 112 113 /** 114 * struct rzg2l_mod_clk - Module Clocks definitions 115 * 116 * @name: handle between common and hardware-specific interfaces 117 * @id: clock index in array containing all Core and Module Clocks 118 * @parent: id of parent clock 119 * @off: register offset 120 * @bit: ON/MON bit 121 * @is_coupled: flag to indicate coupled clock 122 */ 123 struct rzg2l_mod_clk { 124 const char *name; 125 unsigned int id; 126 unsigned int parent; 127 u16 off; 128 u8 bit; 129 bool is_coupled; 130 }; 131 132 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ 133 { \ 134 .name = _name, \ 135 .id = MOD_CLK_BASE + (_id), \ 136 .parent = (_parent), \ 137 .off = (_off), \ 138 .bit = (_bit), \ 139 .is_coupled = (_is_coupled), \ 140 } 141 142 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ 143 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) 144 145 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ 146 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) 147 148 /** 149 * struct rzg2l_reset - Reset definitions 150 * 151 * @off: register offset 152 * @bit: reset bit 153 */ 154 struct rzg2l_reset { 155 u16 off; 156 u8 bit; 157 }; 158 159 #define DEF_RST(_id, _off, _bit) \ 160 [_id] = { \ 161 .off = (_off), \ 162 .bit = (_bit) \ 163 } 164 165 /** 166 * struct rzg2l_cpg_info - SoC-specific CPG Description 167 * 168 * @core_clks: Array of Core Clock definitions 169 * @num_core_clks: Number of entries in core_clks[] 170 * @last_dt_core_clk: ID of the last Core Clock exported to DT 171 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 172 * 173 * @mod_clks: Array of Module Clock definitions 174 * @num_mod_clks: Number of entries in mod_clks[] 175 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 176 * 177 * @resets: Array of Module Reset definitions 178 * @num_resets: Number of entries in resets[] 179 * 180 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 181 * should not be disabled without a knowledgeable driver 182 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 183 */ 184 struct rzg2l_cpg_info { 185 /* Core Clocks */ 186 const struct cpg_core_clk *core_clks; 187 unsigned int num_core_clks; 188 unsigned int last_dt_core_clk; 189 unsigned int num_total_core_clks; 190 191 /* Module Clocks */ 192 const struct rzg2l_mod_clk *mod_clks; 193 unsigned int num_mod_clks; 194 unsigned int num_hw_mod_clks; 195 196 /* Resets */ 197 const struct rzg2l_reset *resets; 198 unsigned int num_resets; 199 200 /* Critical Module Clocks that should not be disabled */ 201 const unsigned int *crit_mod_clks; 202 unsigned int num_crit_mod_clks; 203 }; 204 205 extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 206 extern const struct rzg2l_cpg_info r9a07g054_cpg_info; 207 208 #endif 209