1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __RENESAS_RZG2L_CPG_H__ 10 #define __RENESAS_RZG2L_CPG_H__ 11 12 #define CPG_PL2_DDIV (0x204) 13 #define CPG_PL3A_DDIV (0x208) 14 #define CPG_PL2SDHI_DSEL (0x218) 15 #define CPG_CLKSTATUS (0x280) 16 #define CPG_PL3_SSEL (0x408) 17 #define CPG_PL6_ETH_SSEL (0x418) 18 19 #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) 20 #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) 21 22 #define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000 23 24 /* n = 0/1/2 for PLL1/4/6 */ 25 #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) 26 #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) 27 28 #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) 29 30 #define DDIV_PACK(offset, bitpos, size) \ 31 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 32 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) 33 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) 34 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) 35 #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) 36 37 #define SEL_PLL_PACK(offset, bitpos, size) \ 38 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 39 40 #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) 41 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) 42 43 #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) 44 #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) 45 46 /** 47 * Definitions of CPG Core Clocks 48 * 49 * These include: 50 * - Clock outputs exported to DT 51 * - External input clocks 52 * - Internal CPG clocks 53 */ 54 struct cpg_core_clk { 55 const char *name; 56 unsigned int id; 57 unsigned int parent; 58 unsigned int div; 59 unsigned int mult; 60 unsigned int type; 61 unsigned int conf; 62 const struct clk_div_table *dtable; 63 const char * const *parent_names; 64 int flag; 65 int mux_flags; 66 int num_parents; 67 }; 68 69 enum clk_types { 70 /* Generic */ 71 CLK_TYPE_IN, /* External Clock Input */ 72 CLK_TYPE_FF, /* Fixed Factor Clock */ 73 CLK_TYPE_SAM_PLL, 74 75 /* Clock with divider */ 76 CLK_TYPE_DIV, 77 78 /* Clock with clock source selector */ 79 CLK_TYPE_MUX, 80 81 /* Clock with SD clock source selector */ 82 CLK_TYPE_SD_MUX, 83 }; 84 85 #define DEF_TYPE(_name, _id, _type...) \ 86 { .name = _name, .id = _id, .type = _type } 87 #define DEF_BASE(_name, _id, _type, _parent...) \ 88 DEF_TYPE(_name, _id, _type, .parent = _parent) 89 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 90 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 91 #define DEF_INPUT(_name, _id) \ 92 DEF_TYPE(_name, _id, CLK_TYPE_IN) 93 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 94 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 95 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ 96 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 97 .parent = _parent, .dtable = _dtable, .flag = _flag) 98 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \ 99 _mux_flags) \ 100 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 101 .parent_names = _parent_names, .num_parents = _num_parents, \ 102 .flag = _flag, .mux_flags = _mux_flags) 103 #define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \ 104 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ 105 .parent_names = _parent_names, .num_parents = _num_parents) 106 107 /** 108 * struct rzg2l_mod_clk - Module Clocks definitions 109 * 110 * @name: handle between common and hardware-specific interfaces 111 * @id: clock index in array containing all Core and Module Clocks 112 * @parent: id of parent clock 113 * @off: register offset 114 * @bit: ON/MON bit 115 * @is_coupled: flag to indicate coupled clock 116 */ 117 struct rzg2l_mod_clk { 118 const char *name; 119 unsigned int id; 120 unsigned int parent; 121 u16 off; 122 u8 bit; 123 bool is_coupled; 124 }; 125 126 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ 127 { \ 128 .name = _name, \ 129 .id = MOD_CLK_BASE + (_id), \ 130 .parent = (_parent), \ 131 .off = (_off), \ 132 .bit = (_bit), \ 133 .is_coupled = (_is_coupled), \ 134 } 135 136 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ 137 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) 138 139 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ 140 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) 141 142 /** 143 * struct rzg2l_reset - Reset definitions 144 * 145 * @off: register offset 146 * @bit: reset bit 147 */ 148 struct rzg2l_reset { 149 u16 off; 150 u8 bit; 151 }; 152 153 #define DEF_RST(_id, _off, _bit) \ 154 [_id] = { \ 155 .off = (_off), \ 156 .bit = (_bit) \ 157 } 158 159 /** 160 * struct rzg2l_cpg_info - SoC-specific CPG Description 161 * 162 * @core_clks: Array of Core Clock definitions 163 * @num_core_clks: Number of entries in core_clks[] 164 * @last_dt_core_clk: ID of the last Core Clock exported to DT 165 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 166 * 167 * @mod_clks: Array of Module Clock definitions 168 * @num_mod_clks: Number of entries in mod_clks[] 169 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 170 * 171 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 172 * should not be disabled without a knowledgeable driver 173 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 174 */ 175 struct rzg2l_cpg_info { 176 /* Core Clocks */ 177 const struct cpg_core_clk *core_clks; 178 unsigned int num_core_clks; 179 unsigned int last_dt_core_clk; 180 unsigned int num_total_core_clks; 181 182 /* Module Clocks */ 183 const struct rzg2l_mod_clk *mod_clks; 184 unsigned int num_mod_clks; 185 unsigned int num_hw_mod_clks; 186 187 /* Resets */ 188 const struct rzg2l_reset *resets; 189 unsigned int num_resets; 190 191 /* Critical Module Clocks that should not be disabled */ 192 const unsigned int *crit_mod_clks; 193 unsigned int num_crit_mod_clks; 194 }; 195 196 extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 197 198 #endif 199