1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __RENESAS_RZG2L_CPG_H__ 10 #define __RENESAS_RZG2L_CPG_H__ 11 12 #define CPG_SIPLL5_STBY (0x140) 13 #define CPG_SIPLL5_CLK1 (0x144) 14 #define CPG_SIPLL5_CLK3 (0x14C) 15 #define CPG_SIPLL5_CLK4 (0x150) 16 #define CPG_SIPLL5_CLK5 (0x154) 17 #define CPG_SIPLL5_MON (0x15C) 18 #define CPG_PL1_DDIV (0x200) 19 #define CPG_PL2_DDIV (0x204) 20 #define CPG_PL3A_DDIV (0x208) 21 #define CPG_PL6_DDIV (0x210) 22 #define CPG_PL2SDHI_DSEL (0x218) 23 #define CPG_CLKSTATUS (0x280) 24 #define CPG_PL3_SSEL (0x408) 25 #define CPG_PL6_SSEL (0x414) 26 #define CPG_PL6_ETH_SSEL (0x418) 27 #define CPG_PL5_SDIV (0x420) 28 #define CPG_RST_MON (0x680) 29 #define CPG_OTHERFUNC1_REG (0xBE8) 30 31 #define CPG_SIPLL5_STBY_RESETB BIT(0) 32 #define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) 33 #define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18) 34 #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20) 35 #define CPG_SIPLL5_CLK1_POSTDIV1_WEN BIT(16) 36 #define CPG_SIPLL5_CLK1_POSTDIV2_WEN BIT(20) 37 #define CPG_SIPLL5_CLK1_REFDIV_WEN BIT(24) 38 #define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) 39 #define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) 40 41 #define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) 42 43 #define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) 44 #define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) 45 46 #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) 47 #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) 48 49 #define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000 50 51 /* n = 0/1/2 for PLL1/4/6 */ 52 #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) 53 #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) 54 55 #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) 56 57 #define DDIV_PACK(offset, bitpos, size) \ 58 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 59 #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) 60 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) 61 #define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2) 62 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) 63 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) 64 #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) 65 #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) 66 67 #define SEL_PLL_PACK(offset, bitpos, size) \ 68 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 69 70 #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) 71 #define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1) 72 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) 73 #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) 74 75 #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) 76 #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) 77 78 #define EXTAL_FREQ_IN_MEGA_HZ (24) 79 80 /** 81 * Definitions of CPG Core Clocks 82 * 83 * These include: 84 * - Clock outputs exported to DT 85 * - External input clocks 86 * - Internal CPG clocks 87 */ 88 struct cpg_core_clk { 89 const char *name; 90 unsigned int id; 91 unsigned int parent; 92 unsigned int div; 93 unsigned int mult; 94 unsigned int type; 95 unsigned int conf; 96 const struct clk_div_table *dtable; 97 const char * const *parent_names; 98 int flag; 99 int mux_flags; 100 int num_parents; 101 }; 102 103 enum clk_types { 104 /* Generic */ 105 CLK_TYPE_IN, /* External Clock Input */ 106 CLK_TYPE_FF, /* Fixed Factor Clock */ 107 CLK_TYPE_SAM_PLL, 108 109 /* Clock with divider */ 110 CLK_TYPE_DIV, 111 112 /* Clock with clock source selector */ 113 CLK_TYPE_MUX, 114 115 /* Clock with SD clock source selector */ 116 CLK_TYPE_SD_MUX, 117 118 /* Clock for SIPLL5 */ 119 CLK_TYPE_SIPLL5, 120 121 /* Clock for PLL5_4 clock source selector */ 122 CLK_TYPE_PLL5_4_MUX, 123 124 /* Clock for DSI divider */ 125 CLK_TYPE_DSI_DIV, 126 127 }; 128 129 #define DEF_TYPE(_name, _id, _type...) \ 130 { .name = _name, .id = _id, .type = _type } 131 #define DEF_BASE(_name, _id, _type, _parent...) \ 132 DEF_TYPE(_name, _id, _type, .parent = _parent) 133 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 134 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 135 #define DEF_INPUT(_name, _id) \ 136 DEF_TYPE(_name, _id, CLK_TYPE_IN) 137 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 138 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 139 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ 140 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 141 .parent = _parent, .dtable = _dtable, \ 142 .flag = CLK_DIVIDER_HIWORD_MASK) 143 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ 144 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 145 .parent = _parent, .dtable = _dtable, \ 146 .flag = CLK_DIVIDER_READ_ONLY) 147 #define DEF_MUX(_name, _id, _conf, _parent_names) \ 148 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 149 .parent_names = _parent_names, \ 150 .num_parents = ARRAY_SIZE(_parent_names), \ 151 .mux_flags = CLK_MUX_HIWORD_MASK) 152 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ 153 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 154 .parent_names = _parent_names, \ 155 .num_parents = ARRAY_SIZE(_parent_names), \ 156 .mux_flags = CLK_MUX_READ_ONLY) 157 #define DEF_SD_MUX(_name, _id, _conf, _parent_names) \ 158 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ 159 .parent_names = _parent_names, \ 160 .num_parents = ARRAY_SIZE(_parent_names)) 161 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ 162 DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) 163 #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ 164 DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ 165 .parent_names = _parent_names, \ 166 .num_parents = ARRAY_SIZE(_parent_names)) 167 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ 168 DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) 169 170 /** 171 * struct rzg2l_mod_clk - Module Clocks definitions 172 * 173 * @name: handle between common and hardware-specific interfaces 174 * @id: clock index in array containing all Core and Module Clocks 175 * @parent: id of parent clock 176 * @off: register offset 177 * @bit: ON/MON bit 178 * @is_coupled: flag to indicate coupled clock 179 */ 180 struct rzg2l_mod_clk { 181 const char *name; 182 unsigned int id; 183 unsigned int parent; 184 u16 off; 185 u8 bit; 186 bool is_coupled; 187 }; 188 189 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ 190 { \ 191 .name = _name, \ 192 .id = MOD_CLK_BASE + (_id), \ 193 .parent = (_parent), \ 194 .off = (_off), \ 195 .bit = (_bit), \ 196 .is_coupled = (_is_coupled), \ 197 } 198 199 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ 200 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) 201 202 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ 203 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) 204 205 /** 206 * struct rzg2l_reset - Reset definitions 207 * 208 * @off: register offset 209 * @bit: reset bit 210 * @monbit: monitor bit in CPG_RST_MON register, -1 if none 211 */ 212 struct rzg2l_reset { 213 u16 off; 214 u8 bit; 215 s8 monbit; 216 }; 217 218 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ 219 [_id] = { \ 220 .off = (_off), \ 221 .bit = (_bit), \ 222 .monbit = (_monbit) \ 223 } 224 #define DEF_RST(_id, _off, _bit) \ 225 DEF_RST_MON(_id, _off, _bit, -1) 226 227 /** 228 * struct rzg2l_cpg_info - SoC-specific CPG Description 229 * 230 * @core_clks: Array of Core Clock definitions 231 * @num_core_clks: Number of entries in core_clks[] 232 * @last_dt_core_clk: ID of the last Core Clock exported to DT 233 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 234 * 235 * @mod_clks: Array of Module Clock definitions 236 * @num_mod_clks: Number of entries in mod_clks[] 237 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 238 * 239 * @resets: Array of Module Reset definitions 240 * @num_resets: Number of entries in resets[] 241 * 242 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 243 * should not be disabled without a knowledgeable driver 244 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 245 * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers 246 */ 247 struct rzg2l_cpg_info { 248 /* Core Clocks */ 249 const struct cpg_core_clk *core_clks; 250 unsigned int num_core_clks; 251 unsigned int last_dt_core_clk; 252 unsigned int num_total_core_clks; 253 254 /* Module Clocks */ 255 const struct rzg2l_mod_clk *mod_clks; 256 unsigned int num_mod_clks; 257 unsigned int num_hw_mod_clks; 258 259 /* No PM Module Clocks */ 260 const unsigned int *no_pm_mod_clks; 261 unsigned int num_no_pm_mod_clks; 262 263 /* Resets */ 264 const struct rzg2l_reset *resets; 265 unsigned int num_resets; 266 267 /* Critical Module Clocks that should not be disabled */ 268 const unsigned int *crit_mod_clks; 269 unsigned int num_crit_mod_clks; 270 271 bool has_clk_mon_regs; 272 }; 273 274 extern const struct rzg2l_cpg_info r9a07g043_cpg_info; 275 extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 276 extern const struct rzg2l_cpg_info r9a07g054_cpg_info; 277 extern const struct rzg2l_cpg_info r9a09g011_cpg_info; 278 279 #endif 280