1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ/G2L Clock Pulse Generator 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 * 7 */ 8 9 #ifndef __RENESAS_RZG2L_CPG_H__ 10 #define __RENESAS_RZG2L_CPG_H__ 11 12 #define CPG_SIPLL5_STBY (0x140) 13 #define CPG_SIPLL5_CLK1 (0x144) 14 #define CPG_SIPLL5_CLK3 (0x14C) 15 #define CPG_SIPLL5_CLK4 (0x150) 16 #define CPG_SIPLL5_CLK5 (0x154) 17 #define CPG_SIPLL5_MON (0x15C) 18 #define CPG_PL1_DDIV (0x200) 19 #define CPG_PL2_DDIV (0x204) 20 #define CPG_PL3A_DDIV (0x208) 21 #define CPG_PL6_DDIV (0x210) 22 #define CPG_PL2SDHI_DSEL (0x218) 23 #define CPG_CLKSTATUS (0x280) 24 #define CPG_PL3_SSEL (0x408) 25 #define CPG_PL6_SSEL (0x414) 26 #define CPG_PL6_ETH_SSEL (0x418) 27 #define CPG_PL5_SDIV (0x420) 28 #define CPG_RST_MON (0x680) 29 #define CPG_OTHERFUNC1_REG (0xBE8) 30 31 #define CPG_SIPLL5_STBY_RESETB BIT(0) 32 #define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) 33 #define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18) 34 #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20) 35 #define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) 36 #define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) 37 38 #define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) 39 40 #define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) 41 #define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) 42 43 #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) 44 #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) 45 46 #define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000 47 48 /* n = 0/1/2 for PLL1/4/6 */ 49 #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) 50 #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) 51 52 #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) 53 54 #define DDIV_PACK(offset, bitpos, size) \ 55 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 56 #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) 57 #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) 58 #define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2) 59 #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) 60 #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) 61 #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) 62 #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) 63 64 #define SEL_PLL_PACK(offset, bitpos, size) \ 65 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) 66 67 #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) 68 #define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1) 69 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) 70 #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) 71 72 #define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2) 73 #define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2) 74 75 #define EXTAL_FREQ_IN_MEGA_HZ (24) 76 77 /** 78 * Definitions of CPG Core Clocks 79 * 80 * These include: 81 * - Clock outputs exported to DT 82 * - External input clocks 83 * - Internal CPG clocks 84 */ 85 struct cpg_core_clk { 86 const char *name; 87 unsigned int id; 88 unsigned int parent; 89 unsigned int div; 90 unsigned int mult; 91 unsigned int type; 92 unsigned int conf; 93 const struct clk_div_table *dtable; 94 const char * const *parent_names; 95 int flag; 96 int mux_flags; 97 int num_parents; 98 }; 99 100 enum clk_types { 101 /* Generic */ 102 CLK_TYPE_IN, /* External Clock Input */ 103 CLK_TYPE_FF, /* Fixed Factor Clock */ 104 CLK_TYPE_SAM_PLL, 105 106 /* Clock with divider */ 107 CLK_TYPE_DIV, 108 109 /* Clock with clock source selector */ 110 CLK_TYPE_MUX, 111 112 /* Clock with SD clock source selector */ 113 CLK_TYPE_SD_MUX, 114 115 /* Clock for SIPLL5 */ 116 CLK_TYPE_SIPLL5, 117 118 /* Clock for PLL5_4 clock source selector */ 119 CLK_TYPE_PLL5_4_MUX, 120 121 /* Clock for DSI divider */ 122 CLK_TYPE_DSI_DIV, 123 124 }; 125 126 #define DEF_TYPE(_name, _id, _type...) \ 127 { .name = _name, .id = _id, .type = _type } 128 #define DEF_BASE(_name, _id, _type, _parent...) \ 129 DEF_TYPE(_name, _id, _type, .parent = _parent) 130 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 131 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 132 #define DEF_INPUT(_name, _id) \ 133 DEF_TYPE(_name, _id, CLK_TYPE_IN) 134 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 135 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 136 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ 137 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 138 .parent = _parent, .dtable = _dtable, \ 139 .flag = CLK_DIVIDER_HIWORD_MASK) 140 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ 141 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ 142 .parent = _parent, .dtable = _dtable, \ 143 .flag = CLK_DIVIDER_READ_ONLY) 144 #define DEF_MUX(_name, _id, _conf, _parent_names) \ 145 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 146 .parent_names = _parent_names, \ 147 .num_parents = ARRAY_SIZE(_parent_names), \ 148 .mux_flags = CLK_MUX_HIWORD_MASK) 149 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ 150 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ 151 .parent_names = _parent_names, \ 152 .num_parents = ARRAY_SIZE(_parent_names), \ 153 .mux_flags = CLK_MUX_READ_ONLY) 154 #define DEF_SD_MUX(_name, _id, _conf, _parent_names) \ 155 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \ 156 .parent_names = _parent_names, \ 157 .num_parents = ARRAY_SIZE(_parent_names)) 158 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ 159 DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) 160 #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ 161 DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ 162 .parent_names = _parent_names, \ 163 .num_parents = ARRAY_SIZE(_parent_names)) 164 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ 165 DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) 166 167 /** 168 * struct rzg2l_mod_clk - Module Clocks definitions 169 * 170 * @name: handle between common and hardware-specific interfaces 171 * @id: clock index in array containing all Core and Module Clocks 172 * @parent: id of parent clock 173 * @off: register offset 174 * @bit: ON/MON bit 175 * @is_coupled: flag to indicate coupled clock 176 */ 177 struct rzg2l_mod_clk { 178 const char *name; 179 unsigned int id; 180 unsigned int parent; 181 u16 off; 182 u8 bit; 183 bool is_coupled; 184 }; 185 186 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ 187 { \ 188 .name = _name, \ 189 .id = MOD_CLK_BASE + (_id), \ 190 .parent = (_parent), \ 191 .off = (_off), \ 192 .bit = (_bit), \ 193 .is_coupled = (_is_coupled), \ 194 } 195 196 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ 197 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) 198 199 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ 200 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) 201 202 /** 203 * struct rzg2l_reset - Reset definitions 204 * 205 * @off: register offset 206 * @bit: reset bit 207 * @monbit: monitor bit in CPG_RST_MON register, -1 if none 208 */ 209 struct rzg2l_reset { 210 u16 off; 211 u8 bit; 212 s8 monbit; 213 }; 214 215 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ 216 [_id] = { \ 217 .off = (_off), \ 218 .bit = (_bit), \ 219 .monbit = (_monbit) \ 220 } 221 #define DEF_RST(_id, _off, _bit) \ 222 DEF_RST_MON(_id, _off, _bit, -1) 223 224 /** 225 * struct rzg2l_cpg_info - SoC-specific CPG Description 226 * 227 * @core_clks: Array of Core Clock definitions 228 * @num_core_clks: Number of entries in core_clks[] 229 * @last_dt_core_clk: ID of the last Core Clock exported to DT 230 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 231 * 232 * @mod_clks: Array of Module Clock definitions 233 * @num_mod_clks: Number of entries in mod_clks[] 234 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 235 * 236 * @resets: Array of Module Reset definitions 237 * @num_resets: Number of entries in resets[] 238 * 239 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that 240 * should not be disabled without a knowledgeable driver 241 * @num_crit_mod_clks: Number of entries in crit_mod_clks[] 242 * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers 243 */ 244 struct rzg2l_cpg_info { 245 /* Core Clocks */ 246 const struct cpg_core_clk *core_clks; 247 unsigned int num_core_clks; 248 unsigned int last_dt_core_clk; 249 unsigned int num_total_core_clks; 250 251 /* Module Clocks */ 252 const struct rzg2l_mod_clk *mod_clks; 253 unsigned int num_mod_clks; 254 unsigned int num_hw_mod_clks; 255 256 /* No PM Module Clocks */ 257 const unsigned int *no_pm_mod_clks; 258 unsigned int num_no_pm_mod_clks; 259 260 /* Resets */ 261 const struct rzg2l_reset *resets; 262 unsigned int num_resets; 263 264 /* Critical Module Clocks that should not be disabled */ 265 const unsigned int *crit_mod_clks; 266 unsigned int num_crit_mod_clks; 267 268 bool has_clk_mon_regs; 269 }; 270 271 extern const struct rzg2l_cpg_info r9a07g043_cpg_info; 272 extern const struct rzg2l_cpg_info r9a07g044_cpg_info; 273 extern const struct rzg2l_cpg_info r9a07g054_cpg_info; 274 extern const struct rzg2l_cpg_info r9a09g011_cpg_info; 275 276 #endif 277