1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
4  *
5  * Copyright (C) 2015 Glider bvba
6  *
7  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
8  *
9  * Copyright (C) 2013 Ideas On Board SPRL
10  * Copyright (C) 2015 Renesas Electronics Corp.
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_clock.h>
26 #include <linux/pm_domain.h>
27 #include <linux/psci.h>
28 #include <linux/reset-controller.h>
29 #include <linux/slab.h>
30 
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
35 
36 #ifdef DEBUG
37 #define WARN_DEBUG(x)	WARN_ON(x)
38 #else
39 #define WARN_DEBUG(x)	do { } while (0)
40 #endif
41 
42 
43 /*
44  * Module Standby and Software Reset register offets.
45  *
46  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47  * R-Car Gen2, R-Car Gen3, and RZ/G1.
48  * These are NOT valid for R-Car Gen1 and RZ/A1!
49  */
50 
51 /*
52  * Module Stop Status Register offsets
53  */
54 
55 static const u16 mstpsr[] = {
56 	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
57 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
58 };
59 
60 static const u16 mstpsr_for_v3u[] = {
61 	0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62 	0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
63 };
64 
65 /*
66  * System Module Stop Control Register offsets
67  */
68 
69 static const u16 smstpcr[] = {
70 	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
71 	0x990, 0x994, 0x998, 0x99C,
72 };
73 
74 static const u16 mstpcr_for_v3u[] = {
75 	0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
76 	0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
77 };
78 
79 /*
80  * Standby Control Register offsets (RZ/A)
81  * Base address is FRQCR register
82  */
83 
84 static const u16 stbcr[] = {
85 	0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
86 	0x424, 0x428, 0x42C,
87 };
88 
89 /*
90  * Software Reset Register offsets
91  */
92 
93 static const u16 srcr[] = {
94 	0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
95 	0x920, 0x924, 0x928, 0x92C,
96 };
97 
98 static const u16 srcr_for_v3u[] = {
99 	0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
100 	0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
101 };
102 
103 /* Realtime Module Stop Control Register offsets */
104 #define RMSTPCR(i)	(smstpcr[i] - 0x20)
105 
106 /* Modem Module Stop Control Register offsets (r8a73a4) */
107 #define MMSTPCR(i)	(smstpcr[i] + 0x20)
108 
109 /* Software Reset Clearing Register offsets */
110 
111 static const u16 srstclr[] = {
112 	0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
113 	0x960, 0x964, 0x968, 0x96C,
114 };
115 
116 static const u16 srstclr_for_v3u[] = {
117 	0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
118 	0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
119 };
120 
121 /**
122  * Clock Pulse Generator / Module Standby and Software Reset Private Data
123  *
124  * @rcdev: Optional reset controller entity
125  * @dev: CPG/MSSR device
126  * @base: CPG/MSSR register block base address
127  * @reg_layout: CPG/MSSR register layout
128  * @rmw_lock: protects RMW register accesses
129  * @np: Device node in DT for this CPG/MSSR module
130  * @num_core_clks: Number of Core Clocks in clks[]
131  * @num_mod_clks: Number of Module Clocks in clks[]
132  * @last_dt_core_clk: ID of the last Core Clock exported to DT
133  * @notifiers: Notifier chain to save/restore clock state for system resume
134  * @status_regs: Pointer to status registers array
135  * @control_regs: Pointer to control registers array
136  * @reset_regs: Pointer to reset registers array
137  * @reset_clear_regs:  Pointer to reset clearing registers array
138  * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
139  * @smstpcr_saved[].val: Saved values of SMSTPCR[]
140  * @clks: Array containing all Core and Module Clocks
141  */
142 struct cpg_mssr_priv {
143 #ifdef CONFIG_RESET_CONTROLLER
144 	struct reset_controller_dev rcdev;
145 #endif
146 	struct device *dev;
147 	void __iomem *base;
148 	enum clk_reg_layout reg_layout;
149 	spinlock_t rmw_lock;
150 	struct device_node *np;
151 
152 	unsigned int num_core_clks;
153 	unsigned int num_mod_clks;
154 	unsigned int last_dt_core_clk;
155 
156 	struct raw_notifier_head notifiers;
157 	const u16 *status_regs;
158 	const u16 *control_regs;
159 	const u16 *reset_regs;
160 	const u16 *reset_clear_regs;
161 	struct {
162 		u32 mask;
163 		u32 val;
164 	} smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
165 
166 	struct clk *clks[];
167 };
168 
169 static struct cpg_mssr_priv *cpg_mssr_priv;
170 
171 /**
172  * struct mstp_clock - MSTP gating clock
173  * @hw: handle between common and hardware-specific interfaces
174  * @index: MSTP clock number
175  * @priv: CPG/MSSR private data
176  */
177 struct mstp_clock {
178 	struct clk_hw hw;
179 	u32 index;
180 	struct cpg_mssr_priv *priv;
181 };
182 
183 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
184 
185 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
186 {
187 	struct mstp_clock *clock = to_mstp_clock(hw);
188 	struct cpg_mssr_priv *priv = clock->priv;
189 	unsigned int reg = clock->index / 32;
190 	unsigned int bit = clock->index % 32;
191 	struct device *dev = priv->dev;
192 	u32 bitmask = BIT(bit);
193 	unsigned long flags;
194 	unsigned int i;
195 	u32 value;
196 
197 	dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
198 		enable ? "ON" : "OFF");
199 	spin_lock_irqsave(&priv->rmw_lock, flags);
200 
201 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
202 		value = readb(priv->base + priv->control_regs[reg]);
203 		if (enable)
204 			value &= ~bitmask;
205 		else
206 			value |= bitmask;
207 		writeb(value, priv->base + priv->control_regs[reg]);
208 
209 		/* dummy read to ensure write has completed */
210 		readb(priv->base + priv->control_regs[reg]);
211 		barrier_data(priv->base + priv->control_regs[reg]);
212 	} else {
213 		value = readl(priv->base + priv->control_regs[reg]);
214 		if (enable)
215 			value &= ~bitmask;
216 		else
217 			value |= bitmask;
218 		writel(value, priv->base + priv->control_regs[reg]);
219 	}
220 
221 	spin_unlock_irqrestore(&priv->rmw_lock, flags);
222 
223 	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
224 		return 0;
225 
226 	for (i = 1000; i > 0; --i) {
227 		if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
228 			break;
229 		cpu_relax();
230 	}
231 
232 	if (!i) {
233 		dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
234 			priv->base + priv->control_regs[reg], bit);
235 		return -ETIMEDOUT;
236 	}
237 
238 	return 0;
239 }
240 
241 static int cpg_mstp_clock_enable(struct clk_hw *hw)
242 {
243 	return cpg_mstp_clock_endisable(hw, true);
244 }
245 
246 static void cpg_mstp_clock_disable(struct clk_hw *hw)
247 {
248 	cpg_mstp_clock_endisable(hw, false);
249 }
250 
251 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
252 {
253 	struct mstp_clock *clock = to_mstp_clock(hw);
254 	struct cpg_mssr_priv *priv = clock->priv;
255 	u32 value;
256 
257 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
258 		value = readb(priv->base + priv->control_regs[clock->index / 32]);
259 	else
260 		value = readl(priv->base + priv->status_regs[clock->index / 32]);
261 
262 	return !(value & BIT(clock->index % 32));
263 }
264 
265 static const struct clk_ops cpg_mstp_clock_ops = {
266 	.enable = cpg_mstp_clock_enable,
267 	.disable = cpg_mstp_clock_disable,
268 	.is_enabled = cpg_mstp_clock_is_enabled,
269 };
270 
271 static
272 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
273 					 void *data)
274 {
275 	unsigned int clkidx = clkspec->args[1];
276 	struct cpg_mssr_priv *priv = data;
277 	struct device *dev = priv->dev;
278 	unsigned int idx;
279 	const char *type;
280 	struct clk *clk;
281 	int range_check;
282 
283 	switch (clkspec->args[0]) {
284 	case CPG_CORE:
285 		type = "core";
286 		if (clkidx > priv->last_dt_core_clk) {
287 			dev_err(dev, "Invalid %s clock index %u\n", type,
288 			       clkidx);
289 			return ERR_PTR(-EINVAL);
290 		}
291 		clk = priv->clks[clkidx];
292 		break;
293 
294 	case CPG_MOD:
295 		type = "module";
296 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
297 			idx = MOD_CLK_PACK_10(clkidx);
298 			range_check = 7 - (clkidx % 10);
299 		} else {
300 			idx = MOD_CLK_PACK(clkidx);
301 			range_check = 31 - (clkidx % 100);
302 		}
303 		if (range_check < 0 || idx >= priv->num_mod_clks) {
304 			dev_err(dev, "Invalid %s clock index %u\n", type,
305 				clkidx);
306 			return ERR_PTR(-EINVAL);
307 		}
308 		clk = priv->clks[priv->num_core_clks + idx];
309 		break;
310 
311 	default:
312 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
313 		return ERR_PTR(-EINVAL);
314 	}
315 
316 	if (IS_ERR(clk))
317 		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
318 		       PTR_ERR(clk));
319 	else
320 		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
321 			clkspec->args[0], clkspec->args[1], clk,
322 			clk_get_rate(clk));
323 	return clk;
324 }
325 
326 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
327 					      const struct cpg_mssr_info *info,
328 					      struct cpg_mssr_priv *priv)
329 {
330 	struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
331 	struct device *dev = priv->dev;
332 	unsigned int id = core->id, div = core->div;
333 	const char *parent_name;
334 
335 	WARN_DEBUG(id >= priv->num_core_clks);
336 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
337 
338 	if (!core->name) {
339 		/* Skip NULLified clock */
340 		return;
341 	}
342 
343 	switch (core->type) {
344 	case CLK_TYPE_IN:
345 		clk = of_clk_get_by_name(priv->np, core->name);
346 		break;
347 
348 	case CLK_TYPE_FF:
349 	case CLK_TYPE_DIV6P1:
350 	case CLK_TYPE_DIV6_RO:
351 		WARN_DEBUG(core->parent >= priv->num_core_clks);
352 		parent = priv->clks[core->parent];
353 		if (IS_ERR(parent)) {
354 			clk = parent;
355 			goto fail;
356 		}
357 
358 		parent_name = __clk_get_name(parent);
359 
360 		if (core->type == CLK_TYPE_DIV6_RO)
361 			/* Multiply with the DIV6 register value */
362 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;
363 
364 		if (core->type == CLK_TYPE_DIV6P1) {
365 			clk = cpg_div6_register(core->name, 1, &parent_name,
366 						priv->base + core->offset,
367 						&priv->notifiers);
368 		} else {
369 			clk = clk_register_fixed_factor(NULL, core->name,
370 							parent_name, 0,
371 							core->mult, div);
372 		}
373 		break;
374 
375 	case CLK_TYPE_FR:
376 		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
377 					      core->mult);
378 		break;
379 
380 	default:
381 		if (info->cpg_clk_register)
382 			clk = info->cpg_clk_register(dev, core, info,
383 						     priv->clks, priv->base,
384 						     &priv->notifiers);
385 		else
386 			dev_err(dev, "%s has unsupported core clock type %u\n",
387 				core->name, core->type);
388 		break;
389 	}
390 
391 	if (IS_ERR_OR_NULL(clk))
392 		goto fail;
393 
394 	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
395 	priv->clks[id] = clk;
396 	return;
397 
398 fail:
399 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
400 		core->name, PTR_ERR(clk));
401 }
402 
403 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
404 					     const struct cpg_mssr_info *info,
405 					     struct cpg_mssr_priv *priv)
406 {
407 	struct mstp_clock *clock = NULL;
408 	struct device *dev = priv->dev;
409 	unsigned int id = mod->id;
410 	struct clk_init_data init;
411 	struct clk *parent, *clk;
412 	const char *parent_name;
413 	unsigned int i;
414 
415 	WARN_DEBUG(id < priv->num_core_clks);
416 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
417 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
418 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
419 
420 	if (!mod->name) {
421 		/* Skip NULLified clock */
422 		return;
423 	}
424 
425 	parent = priv->clks[mod->parent];
426 	if (IS_ERR(parent)) {
427 		clk = parent;
428 		goto fail;
429 	}
430 
431 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
432 	if (!clock) {
433 		clk = ERR_PTR(-ENOMEM);
434 		goto fail;
435 	}
436 
437 	init.name = mod->name;
438 	init.ops = &cpg_mstp_clock_ops;
439 	init.flags = CLK_SET_RATE_PARENT;
440 	parent_name = __clk_get_name(parent);
441 	init.parent_names = &parent_name;
442 	init.num_parents = 1;
443 
444 	clock->index = id - priv->num_core_clks;
445 	clock->priv = priv;
446 	clock->hw.init = &init;
447 
448 	for (i = 0; i < info->num_crit_mod_clks; i++)
449 		if (id == info->crit_mod_clks[i] &&
450 		    cpg_mstp_clock_is_enabled(&clock->hw)) {
451 			dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
452 				mod->name);
453 			init.flags |= CLK_IS_CRITICAL;
454 			break;
455 		}
456 
457 	clk = clk_register(NULL, &clock->hw);
458 	if (IS_ERR(clk))
459 		goto fail;
460 
461 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
462 	priv->clks[id] = clk;
463 	priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
464 	return;
465 
466 fail:
467 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
468 		mod->name, PTR_ERR(clk));
469 	kfree(clock);
470 }
471 
472 struct cpg_mssr_clk_domain {
473 	struct generic_pm_domain genpd;
474 	unsigned int num_core_pm_clks;
475 	unsigned int core_pm_clks[];
476 };
477 
478 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
479 
480 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
481 			       struct cpg_mssr_clk_domain *pd)
482 {
483 	unsigned int i;
484 
485 	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
486 		return false;
487 
488 	switch (clkspec->args[0]) {
489 	case CPG_CORE:
490 		for (i = 0; i < pd->num_core_pm_clks; i++)
491 			if (clkspec->args[1] == pd->core_pm_clks[i])
492 				return true;
493 		return false;
494 
495 	case CPG_MOD:
496 		return true;
497 
498 	default:
499 		return false;
500 	}
501 }
502 
503 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
504 {
505 	struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
506 	struct device_node *np = dev->of_node;
507 	struct of_phandle_args clkspec;
508 	struct clk *clk;
509 	int i = 0;
510 	int error;
511 
512 	if (!pd) {
513 		dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
514 		return -EPROBE_DEFER;
515 	}
516 
517 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
518 					   &clkspec)) {
519 		if (cpg_mssr_is_pm_clk(&clkspec, pd))
520 			goto found;
521 
522 		of_node_put(clkspec.np);
523 		i++;
524 	}
525 
526 	return 0;
527 
528 found:
529 	clk = of_clk_get_from_provider(&clkspec);
530 	of_node_put(clkspec.np);
531 
532 	if (IS_ERR(clk))
533 		return PTR_ERR(clk);
534 
535 	error = pm_clk_create(dev);
536 	if (error)
537 		goto fail_put;
538 
539 	error = pm_clk_add_clk(dev, clk);
540 	if (error)
541 		goto fail_destroy;
542 
543 	return 0;
544 
545 fail_destroy:
546 	pm_clk_destroy(dev);
547 fail_put:
548 	clk_put(clk);
549 	return error;
550 }
551 
552 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
553 {
554 	if (!pm_clk_no_clocks(dev))
555 		pm_clk_destroy(dev);
556 }
557 
558 static int __init cpg_mssr_add_clk_domain(struct device *dev,
559 					  const unsigned int *core_pm_clks,
560 					  unsigned int num_core_pm_clks)
561 {
562 	struct device_node *np = dev->of_node;
563 	struct generic_pm_domain *genpd;
564 	struct cpg_mssr_clk_domain *pd;
565 	size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
566 
567 	pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
568 	if (!pd)
569 		return -ENOMEM;
570 
571 	pd->num_core_pm_clks = num_core_pm_clks;
572 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
573 
574 	genpd = &pd->genpd;
575 	genpd->name = np->name;
576 	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
577 		       GENPD_FLAG_ACTIVE_WAKEUP;
578 	genpd->attach_dev = cpg_mssr_attach_dev;
579 	genpd->detach_dev = cpg_mssr_detach_dev;
580 	pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
581 	cpg_mssr_clk_domain = pd;
582 
583 	of_genpd_add_provider_simple(np, genpd);
584 	return 0;
585 }
586 
587 #ifdef CONFIG_RESET_CONTROLLER
588 
589 #define rcdev_to_priv(x)	container_of(x, struct cpg_mssr_priv, rcdev)
590 
591 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
592 			  unsigned long id)
593 {
594 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
595 	unsigned int reg = id / 32;
596 	unsigned int bit = id % 32;
597 	u32 bitmask = BIT(bit);
598 
599 	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
600 
601 	/* Reset module */
602 	writel(bitmask, priv->base + priv->reset_regs[reg]);
603 
604 	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
605 	udelay(35);
606 
607 	/* Release module from reset state */
608 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
609 
610 	return 0;
611 }
612 
613 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
614 {
615 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
616 	unsigned int reg = id / 32;
617 	unsigned int bit = id % 32;
618 	u32 bitmask = BIT(bit);
619 
620 	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
621 
622 	writel(bitmask, priv->base + priv->reset_regs[reg]);
623 	return 0;
624 }
625 
626 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
627 			     unsigned long id)
628 {
629 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
630 	unsigned int reg = id / 32;
631 	unsigned int bit = id % 32;
632 	u32 bitmask = BIT(bit);
633 
634 	dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
635 
636 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
637 	return 0;
638 }
639 
640 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
641 			   unsigned long id)
642 {
643 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
644 	unsigned int reg = id / 32;
645 	unsigned int bit = id % 32;
646 	u32 bitmask = BIT(bit);
647 
648 	return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
649 }
650 
651 static const struct reset_control_ops cpg_mssr_reset_ops = {
652 	.reset = cpg_mssr_reset,
653 	.assert = cpg_mssr_assert,
654 	.deassert = cpg_mssr_deassert,
655 	.status = cpg_mssr_status,
656 };
657 
658 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
659 				const struct of_phandle_args *reset_spec)
660 {
661 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
662 	unsigned int unpacked = reset_spec->args[0];
663 	unsigned int idx = MOD_CLK_PACK(unpacked);
664 
665 	if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
666 		dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
667 		return -EINVAL;
668 	}
669 
670 	return idx;
671 }
672 
673 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
674 {
675 	priv->rcdev.ops = &cpg_mssr_reset_ops;
676 	priv->rcdev.of_node = priv->dev->of_node;
677 	priv->rcdev.of_reset_n_cells = 1;
678 	priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
679 	priv->rcdev.nr_resets = priv->num_mod_clks;
680 	return devm_reset_controller_register(priv->dev, &priv->rcdev);
681 }
682 
683 #else /* !CONFIG_RESET_CONTROLLER */
684 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
685 {
686 	return 0;
687 }
688 #endif /* !CONFIG_RESET_CONTROLLER */
689 
690 
691 static const struct of_device_id cpg_mssr_match[] = {
692 #ifdef CONFIG_CLK_R7S9210
693 	{
694 		.compatible = "renesas,r7s9210-cpg-mssr",
695 		.data = &r7s9210_cpg_mssr_info,
696 	},
697 #endif
698 #ifdef CONFIG_CLK_R8A7742
699 	{
700 		.compatible = "renesas,r8a7742-cpg-mssr",
701 		.data = &r8a7742_cpg_mssr_info,
702 	},
703 #endif
704 #ifdef CONFIG_CLK_R8A7743
705 	{
706 		.compatible = "renesas,r8a7743-cpg-mssr",
707 		.data = &r8a7743_cpg_mssr_info,
708 	},
709 	/* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
710 	{
711 		.compatible = "renesas,r8a7744-cpg-mssr",
712 		.data = &r8a7743_cpg_mssr_info,
713 	},
714 #endif
715 #ifdef CONFIG_CLK_R8A7745
716 	{
717 		.compatible = "renesas,r8a7745-cpg-mssr",
718 		.data = &r8a7745_cpg_mssr_info,
719 	},
720 #endif
721 #ifdef CONFIG_CLK_R8A77470
722 	{
723 		.compatible = "renesas,r8a77470-cpg-mssr",
724 		.data = &r8a77470_cpg_mssr_info,
725 	},
726 #endif
727 #ifdef CONFIG_CLK_R8A774A1
728 	{
729 		.compatible = "renesas,r8a774a1-cpg-mssr",
730 		.data = &r8a774a1_cpg_mssr_info,
731 	},
732 #endif
733 #ifdef CONFIG_CLK_R8A774B1
734 	{
735 		.compatible = "renesas,r8a774b1-cpg-mssr",
736 		.data = &r8a774b1_cpg_mssr_info,
737 	},
738 #endif
739 #ifdef CONFIG_CLK_R8A774C0
740 	{
741 		.compatible = "renesas,r8a774c0-cpg-mssr",
742 		.data = &r8a774c0_cpg_mssr_info,
743 	},
744 #endif
745 #ifdef CONFIG_CLK_R8A774E1
746 	{
747 		.compatible = "renesas,r8a774e1-cpg-mssr",
748 		.data = &r8a774e1_cpg_mssr_info,
749 	},
750 #endif
751 #ifdef CONFIG_CLK_R8A7790
752 	{
753 		.compatible = "renesas,r8a7790-cpg-mssr",
754 		.data = &r8a7790_cpg_mssr_info,
755 	},
756 #endif
757 #ifdef CONFIG_CLK_R8A7791
758 	{
759 		.compatible = "renesas,r8a7791-cpg-mssr",
760 		.data = &r8a7791_cpg_mssr_info,
761 	},
762 	/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
763 	{
764 		.compatible = "renesas,r8a7793-cpg-mssr",
765 		.data = &r8a7791_cpg_mssr_info,
766 	},
767 #endif
768 #ifdef CONFIG_CLK_R8A7792
769 	{
770 		.compatible = "renesas,r8a7792-cpg-mssr",
771 		.data = &r8a7792_cpg_mssr_info,
772 	},
773 #endif
774 #ifdef CONFIG_CLK_R8A7794
775 	{
776 		.compatible = "renesas,r8a7794-cpg-mssr",
777 		.data = &r8a7794_cpg_mssr_info,
778 	},
779 #endif
780 #ifdef CONFIG_CLK_R8A7795
781 	{
782 		.compatible = "renesas,r8a7795-cpg-mssr",
783 		.data = &r8a7795_cpg_mssr_info,
784 	},
785 #endif
786 #ifdef CONFIG_CLK_R8A77960
787 	{
788 		.compatible = "renesas,r8a7796-cpg-mssr",
789 		.data = &r8a7796_cpg_mssr_info,
790 	},
791 #endif
792 #ifdef CONFIG_CLK_R8A77961
793 	{
794 		.compatible = "renesas,r8a77961-cpg-mssr",
795 		.data = &r8a7796_cpg_mssr_info,
796 	},
797 #endif
798 #ifdef CONFIG_CLK_R8A77965
799 	{
800 		.compatible = "renesas,r8a77965-cpg-mssr",
801 		.data = &r8a77965_cpg_mssr_info,
802 	},
803 #endif
804 #ifdef CONFIG_CLK_R8A77970
805 	{
806 		.compatible = "renesas,r8a77970-cpg-mssr",
807 		.data = &r8a77970_cpg_mssr_info,
808 	},
809 #endif
810 #ifdef CONFIG_CLK_R8A77980
811 	{
812 		.compatible = "renesas,r8a77980-cpg-mssr",
813 		.data = &r8a77980_cpg_mssr_info,
814 	},
815 #endif
816 #ifdef CONFIG_CLK_R8A77990
817 	{
818 		.compatible = "renesas,r8a77990-cpg-mssr",
819 		.data = &r8a77990_cpg_mssr_info,
820 	},
821 #endif
822 #ifdef CONFIG_CLK_R8A77995
823 	{
824 		.compatible = "renesas,r8a77995-cpg-mssr",
825 		.data = &r8a77995_cpg_mssr_info,
826 	},
827 #endif
828 #ifdef CONFIG_CLK_R8A779A0
829 	{
830 		.compatible = "renesas,r8a779a0-cpg-mssr",
831 		.data = &r8a779a0_cpg_mssr_info,
832 	},
833 #endif
834 	{ /* sentinel */ }
835 };
836 
837 static void cpg_mssr_del_clk_provider(void *data)
838 {
839 	of_clk_del_provider(data);
840 }
841 
842 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
843 static int cpg_mssr_suspend_noirq(struct device *dev)
844 {
845 	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
846 	unsigned int reg;
847 
848 	/* This is the best we can do to check for the presence of PSCI */
849 	if (!psci_ops.cpu_suspend)
850 		return 0;
851 
852 	/* Save module registers with bits under our control */
853 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
854 		if (priv->smstpcr_saved[reg].mask)
855 			priv->smstpcr_saved[reg].val =
856 				priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
857 				readb(priv->base + priv->control_regs[reg]) :
858 				readl(priv->base + priv->control_regs[reg]);
859 	}
860 
861 	/* Save core clocks */
862 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
863 
864 	return 0;
865 }
866 
867 static int cpg_mssr_resume_noirq(struct device *dev)
868 {
869 	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
870 	unsigned int reg, i;
871 	u32 mask, oldval, newval;
872 
873 	/* This is the best we can do to check for the presence of PSCI */
874 	if (!psci_ops.cpu_suspend)
875 		return 0;
876 
877 	/* Restore core clocks */
878 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
879 
880 	/* Restore module clocks */
881 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
882 		mask = priv->smstpcr_saved[reg].mask;
883 		if (!mask)
884 			continue;
885 
886 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
887 			oldval = readb(priv->base + priv->control_regs[reg]);
888 		else
889 			oldval = readl(priv->base + priv->control_regs[reg]);
890 		newval = oldval & ~mask;
891 		newval |= priv->smstpcr_saved[reg].val & mask;
892 		if (newval == oldval)
893 			continue;
894 
895 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
896 			writeb(newval, priv->base + priv->control_regs[reg]);
897 			/* dummy read to ensure write has completed */
898 			readb(priv->base + priv->control_regs[reg]);
899 			barrier_data(priv->base + priv->control_regs[reg]);
900 			continue;
901 		} else
902 			writel(newval, priv->base + priv->control_regs[reg]);
903 
904 		/* Wait until enabled clocks are really enabled */
905 		mask &= ~priv->smstpcr_saved[reg].val;
906 		if (!mask)
907 			continue;
908 
909 		for (i = 1000; i > 0; --i) {
910 			oldval = readl(priv->base + priv->status_regs[reg]);
911 			if (!(oldval & mask))
912 				break;
913 			cpu_relax();
914 		}
915 
916 		if (!i)
917 			dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
918 				 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
919 				 "STB" : "SMSTP", reg, oldval & mask);
920 	}
921 
922 	return 0;
923 }
924 
925 static const struct dev_pm_ops cpg_mssr_pm = {
926 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
927 				      cpg_mssr_resume_noirq)
928 };
929 #define DEV_PM_OPS	&cpg_mssr_pm
930 #else
931 #define DEV_PM_OPS	NULL
932 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
933 
934 static int __init cpg_mssr_common_init(struct device *dev,
935 				       struct device_node *np,
936 				       const struct cpg_mssr_info *info)
937 {
938 	struct cpg_mssr_priv *priv;
939 	unsigned int nclks, i;
940 	int error;
941 
942 	if (info->init) {
943 		error = info->init(dev);
944 		if (error)
945 			return error;
946 	}
947 
948 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;
949 	priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
950 	if (!priv)
951 		return -ENOMEM;
952 
953 	priv->np = np;
954 	priv->dev = dev;
955 	spin_lock_init(&priv->rmw_lock);
956 
957 	priv->base = of_iomap(np, 0);
958 	if (!priv->base) {
959 		error = -ENOMEM;
960 		goto out_err;
961 	}
962 
963 	cpg_mssr_priv = priv;
964 	priv->num_core_clks = info->num_total_core_clks;
965 	priv->num_mod_clks = info->num_hw_mod_clks;
966 	priv->last_dt_core_clk = info->last_dt_core_clk;
967 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
968 	priv->reg_layout = info->reg_layout;
969 	if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
970 		priv->status_regs = mstpsr;
971 		priv->control_regs = smstpcr;
972 		priv->reset_regs = srcr;
973 		priv->reset_clear_regs = srstclr;
974 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
975 		priv->control_regs = stbcr;
976 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
977 		priv->status_regs = mstpsr_for_v3u;
978 		priv->control_regs = mstpcr_for_v3u;
979 		priv->reset_regs = srcr_for_v3u;
980 		priv->reset_clear_regs = srstclr_for_v3u;
981 	} else {
982 		error = -EINVAL;
983 		goto out_err;
984 	}
985 
986 	for (i = 0; i < nclks; i++)
987 		priv->clks[i] = ERR_PTR(-ENOENT);
988 
989 	error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
990 	if (error)
991 		goto out_err;
992 
993 	return 0;
994 
995 out_err:
996 	if (priv->base)
997 		iounmap(priv->base);
998 	kfree(priv);
999 
1000 	return error;
1001 }
1002 
1003 void __init cpg_mssr_early_init(struct device_node *np,
1004 				const struct cpg_mssr_info *info)
1005 {
1006 	int error;
1007 	int i;
1008 
1009 	error = cpg_mssr_common_init(NULL, np, info);
1010 	if (error)
1011 		return;
1012 
1013 	for (i = 0; i < info->num_early_core_clks; i++)
1014 		cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
1015 					   cpg_mssr_priv);
1016 
1017 	for (i = 0; i < info->num_early_mod_clks; i++)
1018 		cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
1019 					  cpg_mssr_priv);
1020 
1021 }
1022 
1023 static int __init cpg_mssr_probe(struct platform_device *pdev)
1024 {
1025 	struct device *dev = &pdev->dev;
1026 	struct device_node *np = dev->of_node;
1027 	const struct cpg_mssr_info *info;
1028 	struct cpg_mssr_priv *priv;
1029 	unsigned int i;
1030 	int error;
1031 
1032 	info = of_device_get_match_data(dev);
1033 
1034 	if (!cpg_mssr_priv) {
1035 		error = cpg_mssr_common_init(dev, dev->of_node, info);
1036 		if (error)
1037 			return error;
1038 	}
1039 
1040 	priv = cpg_mssr_priv;
1041 	priv->dev = dev;
1042 	dev_set_drvdata(dev, priv);
1043 
1044 	for (i = 0; i < info->num_core_clks; i++)
1045 		cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
1046 
1047 	for (i = 0; i < info->num_mod_clks; i++)
1048 		cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
1049 
1050 	error = devm_add_action_or_reset(dev,
1051 					 cpg_mssr_del_clk_provider,
1052 					 np);
1053 	if (error)
1054 		return error;
1055 
1056 	error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
1057 					info->num_core_pm_clks);
1058 	if (error)
1059 		return error;
1060 
1061 	/* Reset Controller not supported for Standby Control SoCs */
1062 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1063 		return 0;
1064 
1065 	error = cpg_mssr_reset_controller_register(priv);
1066 	if (error)
1067 		return error;
1068 
1069 	return 0;
1070 }
1071 
1072 static struct platform_driver cpg_mssr_driver = {
1073 	.driver		= {
1074 		.name	= "renesas-cpg-mssr",
1075 		.of_match_table = cpg_mssr_match,
1076 		.pm = DEV_PM_OPS,
1077 	},
1078 };
1079 
1080 static int __init cpg_mssr_init(void)
1081 {
1082 	return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
1083 }
1084 
1085 subsys_initcall(cpg_mssr_init);
1086 
1087 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
1088 				   unsigned int num_core_clks,
1089 				   unsigned int first_clk,
1090 				   unsigned int last_clk)
1091 {
1092 	unsigned int i;
1093 
1094 	for (i = 0; i < num_core_clks; i++)
1095 		if (core_clks[i].id >= first_clk &&
1096 		    core_clks[i].id <= last_clk)
1097 			core_clks[i].name = NULL;
1098 }
1099 
1100 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
1101 			     unsigned int num_mod_clks,
1102 			     const unsigned int *clks, unsigned int n)
1103 {
1104 	unsigned int i, j;
1105 
1106 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1107 		if (mod_clks[i].id == clks[j]) {
1108 			mod_clks[i].name = NULL;
1109 			j++;
1110 		}
1111 }
1112 
1113 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
1114 			      unsigned int num_mod_clks,
1115 			      const struct mssr_mod_reparent *clks,
1116 			      unsigned int n)
1117 {
1118 	unsigned int i, j;
1119 
1120 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1121 		if (mod_clks[i].id == clks[j].clk) {
1122 			mod_clks[i].parent = clks[j].parent;
1123 			j++;
1124 		}
1125 }
1126 
1127 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
1128 MODULE_LICENSE("GPL v2");
1129