1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2015 Glider bvba 6 * 7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 8 * 9 * Copyright (C) 2013 Ideas On Board SPRL 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk/renesas.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_clock.h> 26 #include <linux/pm_domain.h> 27 #include <linux/psci.h> 28 #include <linux/reset-controller.h> 29 #include <linux/slab.h> 30 31 #include <dt-bindings/clock/renesas-cpg-mssr.h> 32 33 #include "renesas-cpg-mssr.h" 34 #include "clk-div6.h" 35 36 #ifdef DEBUG 37 #define WARN_DEBUG(x) WARN_ON(x) 38 #else 39 #define WARN_DEBUG(x) do { } while (0) 40 #endif 41 42 43 /* 44 * Module Standby and Software Reset register offets. 45 * 46 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 47 * R-Car Gen2, R-Car Gen3, and RZ/G1. 48 * These are NOT valid for R-Car Gen1 and RZ/A1! 49 */ 50 51 /* 52 * Module Stop Status Register offsets 53 */ 54 55 static const u16 mstpsr[] = { 56 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 57 0x9A0, 0x9A4, 0x9A8, 0x9AC, 58 }; 59 60 #define MSTPSR(i) mstpsr[i] 61 62 63 /* 64 * System Module Stop Control Register offsets 65 */ 66 67 static const u16 smstpcr[] = { 68 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 69 0x990, 0x994, 0x998, 0x99C, 70 }; 71 72 #define SMSTPCR(i) smstpcr[i] 73 74 /* 75 * Standby Control Register offsets (RZ/A) 76 * Base address is FRQCR register 77 */ 78 79 static const u16 stbcr[] = { 80 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420, 81 0x424, 0x428, 0x42C, 82 }; 83 84 #define STBCR(i) stbcr[i] 85 86 /* 87 * Software Reset Register offsets 88 */ 89 90 static const u16 srcr[] = { 91 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 92 0x920, 0x924, 0x928, 0x92C, 93 }; 94 95 #define SRCR(i) srcr[i] 96 97 98 /* Realtime Module Stop Control Register offsets */ 99 #define RMSTPCR(i) (smstpcr[i] - 0x20) 100 101 /* Modem Module Stop Control Register offsets (r8a73a4) */ 102 #define MMSTPCR(i) (smstpcr[i] + 0x20) 103 104 /* Software Reset Clearing Register offsets */ 105 #define SRSTCLR(i) (0x940 + (i) * 4) 106 107 108 /** 109 * Clock Pulse Generator / Module Standby and Software Reset Private Data 110 * 111 * @rcdev: Optional reset controller entity 112 * @dev: CPG/MSSR device 113 * @base: CPG/MSSR register block base address 114 * @rmw_lock: protects RMW register accesses 115 * @np: Device node in DT for this CPG/MSSR module 116 * @num_core_clks: Number of Core Clocks in clks[] 117 * @num_mod_clks: Number of Module Clocks in clks[] 118 * @last_dt_core_clk: ID of the last Core Clock exported to DT 119 * @stbyctrl: This device has Standby Control Registers 120 * @notifiers: Notifier chain to save/restore clock state for system resume 121 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control 122 * @smstpcr_saved[].val: Saved values of SMSTPCR[] 123 * @clks: Array containing all Core and Module Clocks 124 */ 125 struct cpg_mssr_priv { 126 #ifdef CONFIG_RESET_CONTROLLER 127 struct reset_controller_dev rcdev; 128 #endif 129 struct device *dev; 130 void __iomem *base; 131 spinlock_t rmw_lock; 132 struct device_node *np; 133 134 unsigned int num_core_clks; 135 unsigned int num_mod_clks; 136 unsigned int last_dt_core_clk; 137 bool stbyctrl; 138 139 struct raw_notifier_head notifiers; 140 struct { 141 u32 mask; 142 u32 val; 143 } smstpcr_saved[ARRAY_SIZE(smstpcr)]; 144 145 struct clk *clks[]; 146 }; 147 148 static struct cpg_mssr_priv *cpg_mssr_priv; 149 150 /** 151 * struct mstp_clock - MSTP gating clock 152 * @hw: handle between common and hardware-specific interfaces 153 * @index: MSTP clock number 154 * @priv: CPG/MSSR private data 155 */ 156 struct mstp_clock { 157 struct clk_hw hw; 158 u32 index; 159 struct cpg_mssr_priv *priv; 160 }; 161 162 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) 163 164 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 165 { 166 struct mstp_clock *clock = to_mstp_clock(hw); 167 struct cpg_mssr_priv *priv = clock->priv; 168 unsigned int reg = clock->index / 32; 169 unsigned int bit = clock->index % 32; 170 struct device *dev = priv->dev; 171 u32 bitmask = BIT(bit); 172 unsigned long flags; 173 unsigned int i; 174 u32 value; 175 176 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 177 enable ? "ON" : "OFF"); 178 spin_lock_irqsave(&priv->rmw_lock, flags); 179 180 if (priv->stbyctrl) { 181 value = readb(priv->base + STBCR(reg)); 182 if (enable) 183 value &= ~bitmask; 184 else 185 value |= bitmask; 186 writeb(value, priv->base + STBCR(reg)); 187 188 /* dummy read to ensure write has completed */ 189 readb(priv->base + STBCR(reg)); 190 barrier_data(priv->base + STBCR(reg)); 191 } else { 192 value = readl(priv->base + SMSTPCR(reg)); 193 if (enable) 194 value &= ~bitmask; 195 else 196 value |= bitmask; 197 writel(value, priv->base + SMSTPCR(reg)); 198 } 199 200 spin_unlock_irqrestore(&priv->rmw_lock, flags); 201 202 if (!enable || priv->stbyctrl) 203 return 0; 204 205 for (i = 1000; i > 0; --i) { 206 if (!(readl(priv->base + MSTPSR(reg)) & bitmask)) 207 break; 208 cpu_relax(); 209 } 210 211 if (!i) { 212 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 213 priv->base + SMSTPCR(reg), bit); 214 return -ETIMEDOUT; 215 } 216 217 return 0; 218 } 219 220 static int cpg_mstp_clock_enable(struct clk_hw *hw) 221 { 222 return cpg_mstp_clock_endisable(hw, true); 223 } 224 225 static void cpg_mstp_clock_disable(struct clk_hw *hw) 226 { 227 cpg_mstp_clock_endisable(hw, false); 228 } 229 230 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 231 { 232 struct mstp_clock *clock = to_mstp_clock(hw); 233 struct cpg_mssr_priv *priv = clock->priv; 234 u32 value; 235 236 if (priv->stbyctrl) 237 value = readb(priv->base + STBCR(clock->index / 32)); 238 else 239 value = readl(priv->base + MSTPSR(clock->index / 32)); 240 241 return !(value & BIT(clock->index % 32)); 242 } 243 244 static const struct clk_ops cpg_mstp_clock_ops = { 245 .enable = cpg_mstp_clock_enable, 246 .disable = cpg_mstp_clock_disable, 247 .is_enabled = cpg_mstp_clock_is_enabled, 248 }; 249 250 static 251 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 252 void *data) 253 { 254 unsigned int clkidx = clkspec->args[1]; 255 struct cpg_mssr_priv *priv = data; 256 struct device *dev = priv->dev; 257 unsigned int idx; 258 const char *type; 259 struct clk *clk; 260 int range_check; 261 262 switch (clkspec->args[0]) { 263 case CPG_CORE: 264 type = "core"; 265 if (clkidx > priv->last_dt_core_clk) { 266 dev_err(dev, "Invalid %s clock index %u\n", type, 267 clkidx); 268 return ERR_PTR(-EINVAL); 269 } 270 clk = priv->clks[clkidx]; 271 break; 272 273 case CPG_MOD: 274 type = "module"; 275 if (priv->stbyctrl) { 276 idx = MOD_CLK_PACK_10(clkidx); 277 range_check = 7 - (clkidx % 10); 278 } else { 279 idx = MOD_CLK_PACK(clkidx); 280 range_check = 31 - (clkidx % 100); 281 } 282 if (range_check < 0 || idx >= priv->num_mod_clks) { 283 dev_err(dev, "Invalid %s clock index %u\n", type, 284 clkidx); 285 return ERR_PTR(-EINVAL); 286 } 287 clk = priv->clks[priv->num_core_clks + idx]; 288 break; 289 290 default: 291 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); 292 return ERR_PTR(-EINVAL); 293 } 294 295 if (IS_ERR(clk)) 296 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, 297 PTR_ERR(clk)); 298 else 299 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", 300 clkspec->args[0], clkspec->args[1], clk, 301 clk_get_rate(clk)); 302 return clk; 303 } 304 305 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 306 const struct cpg_mssr_info *info, 307 struct cpg_mssr_priv *priv) 308 { 309 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; 310 struct device *dev = priv->dev; 311 unsigned int id = core->id, div = core->div; 312 const char *parent_name; 313 314 WARN_DEBUG(id >= priv->num_core_clks); 315 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 316 317 if (!core->name) { 318 /* Skip NULLified clock */ 319 return; 320 } 321 322 switch (core->type) { 323 case CLK_TYPE_IN: 324 clk = of_clk_get_by_name(priv->np, core->name); 325 break; 326 327 case CLK_TYPE_FF: 328 case CLK_TYPE_DIV6P1: 329 case CLK_TYPE_DIV6_RO: 330 WARN_DEBUG(core->parent >= priv->num_core_clks); 331 parent = priv->clks[core->parent]; 332 if (IS_ERR(parent)) { 333 clk = parent; 334 goto fail; 335 } 336 337 parent_name = __clk_get_name(parent); 338 339 if (core->type == CLK_TYPE_DIV6_RO) 340 /* Multiply with the DIV6 register value */ 341 div *= (readl(priv->base + core->offset) & 0x3f) + 1; 342 343 if (core->type == CLK_TYPE_DIV6P1) { 344 clk = cpg_div6_register(core->name, 1, &parent_name, 345 priv->base + core->offset, 346 &priv->notifiers); 347 } else { 348 clk = clk_register_fixed_factor(NULL, core->name, 349 parent_name, 0, 350 core->mult, div); 351 } 352 break; 353 354 case CLK_TYPE_FR: 355 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, 356 core->mult); 357 break; 358 359 default: 360 if (info->cpg_clk_register) 361 clk = info->cpg_clk_register(dev, core, info, 362 priv->clks, priv->base, 363 &priv->notifiers); 364 else 365 dev_err(dev, "%s has unsupported core clock type %u\n", 366 core->name, core->type); 367 break; 368 } 369 370 if (IS_ERR_OR_NULL(clk)) 371 goto fail; 372 373 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 374 priv->clks[id] = clk; 375 return; 376 377 fail: 378 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", 379 core->name, PTR_ERR(clk)); 380 } 381 382 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 383 const struct cpg_mssr_info *info, 384 struct cpg_mssr_priv *priv) 385 { 386 struct mstp_clock *clock = NULL; 387 struct device *dev = priv->dev; 388 unsigned int id = mod->id; 389 struct clk_init_data init; 390 struct clk *parent, *clk; 391 const char *parent_name; 392 unsigned int i; 393 394 WARN_DEBUG(id < priv->num_core_clks); 395 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 396 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 397 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 398 399 if (!mod->name) { 400 /* Skip NULLified clock */ 401 return; 402 } 403 404 parent = priv->clks[mod->parent]; 405 if (IS_ERR(parent)) { 406 clk = parent; 407 goto fail; 408 } 409 410 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 411 if (!clock) { 412 clk = ERR_PTR(-ENOMEM); 413 goto fail; 414 } 415 416 init.name = mod->name; 417 init.ops = &cpg_mstp_clock_ops; 418 init.flags = CLK_SET_RATE_PARENT; 419 parent_name = __clk_get_name(parent); 420 init.parent_names = &parent_name; 421 init.num_parents = 1; 422 423 clock->index = id - priv->num_core_clks; 424 clock->priv = priv; 425 clock->hw.init = &init; 426 427 for (i = 0; i < info->num_crit_mod_clks; i++) 428 if (id == info->crit_mod_clks[i] && 429 cpg_mstp_clock_is_enabled(&clock->hw)) { 430 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", 431 mod->name); 432 init.flags |= CLK_IS_CRITICAL; 433 break; 434 } 435 436 clk = clk_register(NULL, &clock->hw); 437 if (IS_ERR(clk)) 438 goto fail; 439 440 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 441 priv->clks[id] = clk; 442 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); 443 return; 444 445 fail: 446 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", 447 mod->name, PTR_ERR(clk)); 448 kfree(clock); 449 } 450 451 struct cpg_mssr_clk_domain { 452 struct generic_pm_domain genpd; 453 unsigned int num_core_pm_clks; 454 unsigned int core_pm_clks[]; 455 }; 456 457 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; 458 459 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, 460 struct cpg_mssr_clk_domain *pd) 461 { 462 unsigned int i; 463 464 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) 465 return false; 466 467 switch (clkspec->args[0]) { 468 case CPG_CORE: 469 for (i = 0; i < pd->num_core_pm_clks; i++) 470 if (clkspec->args[1] == pd->core_pm_clks[i]) 471 return true; 472 return false; 473 474 case CPG_MOD: 475 return true; 476 477 default: 478 return false; 479 } 480 } 481 482 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) 483 { 484 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; 485 struct device_node *np = dev->of_node; 486 struct of_phandle_args clkspec; 487 struct clk *clk; 488 int i = 0; 489 int error; 490 491 if (!pd) { 492 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); 493 return -EPROBE_DEFER; 494 } 495 496 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 497 &clkspec)) { 498 if (cpg_mssr_is_pm_clk(&clkspec, pd)) 499 goto found; 500 501 of_node_put(clkspec.np); 502 i++; 503 } 504 505 return 0; 506 507 found: 508 clk = of_clk_get_from_provider(&clkspec); 509 of_node_put(clkspec.np); 510 511 if (IS_ERR(clk)) 512 return PTR_ERR(clk); 513 514 error = pm_clk_create(dev); 515 if (error) 516 goto fail_put; 517 518 error = pm_clk_add_clk(dev, clk); 519 if (error) 520 goto fail_destroy; 521 522 return 0; 523 524 fail_destroy: 525 pm_clk_destroy(dev); 526 fail_put: 527 clk_put(clk); 528 return error; 529 } 530 531 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) 532 { 533 if (!pm_clk_no_clocks(dev)) 534 pm_clk_destroy(dev); 535 } 536 537 static int __init cpg_mssr_add_clk_domain(struct device *dev, 538 const unsigned int *core_pm_clks, 539 unsigned int num_core_pm_clks) 540 { 541 struct device_node *np = dev->of_node; 542 struct generic_pm_domain *genpd; 543 struct cpg_mssr_clk_domain *pd; 544 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); 545 546 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); 547 if (!pd) 548 return -ENOMEM; 549 550 pd->num_core_pm_clks = num_core_pm_clks; 551 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); 552 553 genpd = &pd->genpd; 554 genpd->name = np->name; 555 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | 556 GENPD_FLAG_ACTIVE_WAKEUP; 557 genpd->attach_dev = cpg_mssr_attach_dev; 558 genpd->detach_dev = cpg_mssr_detach_dev; 559 pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 560 cpg_mssr_clk_domain = pd; 561 562 of_genpd_add_provider_simple(np, genpd); 563 return 0; 564 } 565 566 #ifdef CONFIG_RESET_CONTROLLER 567 568 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) 569 570 static int cpg_mssr_reset(struct reset_controller_dev *rcdev, 571 unsigned long id) 572 { 573 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 574 unsigned int reg = id / 32; 575 unsigned int bit = id % 32; 576 u32 bitmask = BIT(bit); 577 578 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 579 580 /* Reset module */ 581 writel(bitmask, priv->base + SRCR(reg)); 582 583 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 584 udelay(35); 585 586 /* Release module from reset state */ 587 writel(bitmask, priv->base + SRSTCLR(reg)); 588 589 return 0; 590 } 591 592 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) 593 { 594 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 595 unsigned int reg = id / 32; 596 unsigned int bit = id % 32; 597 u32 bitmask = BIT(bit); 598 599 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 600 601 writel(bitmask, priv->base + SRCR(reg)); 602 return 0; 603 } 604 605 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, 606 unsigned long id) 607 { 608 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 609 unsigned int reg = id / 32; 610 unsigned int bit = id % 32; 611 u32 bitmask = BIT(bit); 612 613 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 614 615 writel(bitmask, priv->base + SRSTCLR(reg)); 616 return 0; 617 } 618 619 static int cpg_mssr_status(struct reset_controller_dev *rcdev, 620 unsigned long id) 621 { 622 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 623 unsigned int reg = id / 32; 624 unsigned int bit = id % 32; 625 u32 bitmask = BIT(bit); 626 627 return !!(readl(priv->base + SRCR(reg)) & bitmask); 628 } 629 630 static const struct reset_control_ops cpg_mssr_reset_ops = { 631 .reset = cpg_mssr_reset, 632 .assert = cpg_mssr_assert, 633 .deassert = cpg_mssr_deassert, 634 .status = cpg_mssr_status, 635 }; 636 637 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, 638 const struct of_phandle_args *reset_spec) 639 { 640 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 641 unsigned int unpacked = reset_spec->args[0]; 642 unsigned int idx = MOD_CLK_PACK(unpacked); 643 644 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { 645 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); 646 return -EINVAL; 647 } 648 649 return idx; 650 } 651 652 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 653 { 654 priv->rcdev.ops = &cpg_mssr_reset_ops; 655 priv->rcdev.of_node = priv->dev->of_node; 656 priv->rcdev.of_reset_n_cells = 1; 657 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; 658 priv->rcdev.nr_resets = priv->num_mod_clks; 659 return devm_reset_controller_register(priv->dev, &priv->rcdev); 660 } 661 662 #else /* !CONFIG_RESET_CONTROLLER */ 663 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 664 { 665 return 0; 666 } 667 #endif /* !CONFIG_RESET_CONTROLLER */ 668 669 670 static const struct of_device_id cpg_mssr_match[] = { 671 #ifdef CONFIG_CLK_R7S9210 672 { 673 .compatible = "renesas,r7s9210-cpg-mssr", 674 .data = &r7s9210_cpg_mssr_info, 675 }, 676 #endif 677 #ifdef CONFIG_CLK_R8A7742 678 { 679 .compatible = "renesas,r8a7742-cpg-mssr", 680 .data = &r8a7742_cpg_mssr_info, 681 }, 682 #endif 683 #ifdef CONFIG_CLK_R8A7743 684 { 685 .compatible = "renesas,r8a7743-cpg-mssr", 686 .data = &r8a7743_cpg_mssr_info, 687 }, 688 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */ 689 { 690 .compatible = "renesas,r8a7744-cpg-mssr", 691 .data = &r8a7743_cpg_mssr_info, 692 }, 693 #endif 694 #ifdef CONFIG_CLK_R8A7745 695 { 696 .compatible = "renesas,r8a7745-cpg-mssr", 697 .data = &r8a7745_cpg_mssr_info, 698 }, 699 #endif 700 #ifdef CONFIG_CLK_R8A77470 701 { 702 .compatible = "renesas,r8a77470-cpg-mssr", 703 .data = &r8a77470_cpg_mssr_info, 704 }, 705 #endif 706 #ifdef CONFIG_CLK_R8A774A1 707 { 708 .compatible = "renesas,r8a774a1-cpg-mssr", 709 .data = &r8a774a1_cpg_mssr_info, 710 }, 711 #endif 712 #ifdef CONFIG_CLK_R8A774B1 713 { 714 .compatible = "renesas,r8a774b1-cpg-mssr", 715 .data = &r8a774b1_cpg_mssr_info, 716 }, 717 #endif 718 #ifdef CONFIG_CLK_R8A774C0 719 { 720 .compatible = "renesas,r8a774c0-cpg-mssr", 721 .data = &r8a774c0_cpg_mssr_info, 722 }, 723 #endif 724 #ifdef CONFIG_CLK_R8A774E1 725 { 726 .compatible = "renesas,r8a774e1-cpg-mssr", 727 .data = &r8a774e1_cpg_mssr_info, 728 }, 729 #endif 730 #ifdef CONFIG_CLK_R8A7790 731 { 732 .compatible = "renesas,r8a7790-cpg-mssr", 733 .data = &r8a7790_cpg_mssr_info, 734 }, 735 #endif 736 #ifdef CONFIG_CLK_R8A7791 737 { 738 .compatible = "renesas,r8a7791-cpg-mssr", 739 .data = &r8a7791_cpg_mssr_info, 740 }, 741 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ 742 { 743 .compatible = "renesas,r8a7793-cpg-mssr", 744 .data = &r8a7791_cpg_mssr_info, 745 }, 746 #endif 747 #ifdef CONFIG_CLK_R8A7792 748 { 749 .compatible = "renesas,r8a7792-cpg-mssr", 750 .data = &r8a7792_cpg_mssr_info, 751 }, 752 #endif 753 #ifdef CONFIG_CLK_R8A7794 754 { 755 .compatible = "renesas,r8a7794-cpg-mssr", 756 .data = &r8a7794_cpg_mssr_info, 757 }, 758 #endif 759 #ifdef CONFIG_CLK_R8A7795 760 { 761 .compatible = "renesas,r8a7795-cpg-mssr", 762 .data = &r8a7795_cpg_mssr_info, 763 }, 764 #endif 765 #ifdef CONFIG_CLK_R8A77960 766 { 767 .compatible = "renesas,r8a7796-cpg-mssr", 768 .data = &r8a7796_cpg_mssr_info, 769 }, 770 #endif 771 #ifdef CONFIG_CLK_R8A77961 772 { 773 .compatible = "renesas,r8a77961-cpg-mssr", 774 .data = &r8a7796_cpg_mssr_info, 775 }, 776 #endif 777 #ifdef CONFIG_CLK_R8A77965 778 { 779 .compatible = "renesas,r8a77965-cpg-mssr", 780 .data = &r8a77965_cpg_mssr_info, 781 }, 782 #endif 783 #ifdef CONFIG_CLK_R8A77970 784 { 785 .compatible = "renesas,r8a77970-cpg-mssr", 786 .data = &r8a77970_cpg_mssr_info, 787 }, 788 #endif 789 #ifdef CONFIG_CLK_R8A77980 790 { 791 .compatible = "renesas,r8a77980-cpg-mssr", 792 .data = &r8a77980_cpg_mssr_info, 793 }, 794 #endif 795 #ifdef CONFIG_CLK_R8A77990 796 { 797 .compatible = "renesas,r8a77990-cpg-mssr", 798 .data = &r8a77990_cpg_mssr_info, 799 }, 800 #endif 801 #ifdef CONFIG_CLK_R8A77995 802 { 803 .compatible = "renesas,r8a77995-cpg-mssr", 804 .data = &r8a77995_cpg_mssr_info, 805 }, 806 #endif 807 { /* sentinel */ } 808 }; 809 810 static void cpg_mssr_del_clk_provider(void *data) 811 { 812 of_clk_del_provider(data); 813 } 814 815 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 816 static int cpg_mssr_suspend_noirq(struct device *dev) 817 { 818 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 819 unsigned int reg; 820 821 /* This is the best we can do to check for the presence of PSCI */ 822 if (!psci_ops.cpu_suspend) 823 return 0; 824 825 /* Save module registers with bits under our control */ 826 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 827 if (priv->smstpcr_saved[reg].mask) 828 priv->smstpcr_saved[reg].val = priv->stbyctrl ? 829 readb(priv->base + STBCR(reg)) : 830 readl(priv->base + SMSTPCR(reg)); 831 } 832 833 /* Save core clocks */ 834 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); 835 836 return 0; 837 } 838 839 static int cpg_mssr_resume_noirq(struct device *dev) 840 { 841 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 842 unsigned int reg, i; 843 u32 mask, oldval, newval; 844 845 /* This is the best we can do to check for the presence of PSCI */ 846 if (!psci_ops.cpu_suspend) 847 return 0; 848 849 /* Restore core clocks */ 850 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); 851 852 /* Restore module clocks */ 853 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 854 mask = priv->smstpcr_saved[reg].mask; 855 if (!mask) 856 continue; 857 858 if (priv->stbyctrl) 859 oldval = readb(priv->base + STBCR(reg)); 860 else 861 oldval = readl(priv->base + SMSTPCR(reg)); 862 newval = oldval & ~mask; 863 newval |= priv->smstpcr_saved[reg].val & mask; 864 if (newval == oldval) 865 continue; 866 867 if (priv->stbyctrl) { 868 writeb(newval, priv->base + STBCR(reg)); 869 /* dummy read to ensure write has completed */ 870 readb(priv->base + STBCR(reg)); 871 barrier_data(priv->base + STBCR(reg)); 872 continue; 873 } else 874 writel(newval, priv->base + SMSTPCR(reg)); 875 876 /* Wait until enabled clocks are really enabled */ 877 mask &= ~priv->smstpcr_saved[reg].val; 878 if (!mask) 879 continue; 880 881 for (i = 1000; i > 0; --i) { 882 oldval = readl(priv->base + MSTPSR(reg)); 883 if (!(oldval & mask)) 884 break; 885 cpu_relax(); 886 } 887 888 if (!i) 889 dev_warn(dev, "Failed to enable %s%u[0x%x]\n", 890 priv->stbyctrl ? "STB" : "SMSTP", reg, 891 oldval & mask); 892 } 893 894 return 0; 895 } 896 897 static const struct dev_pm_ops cpg_mssr_pm = { 898 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq, 899 cpg_mssr_resume_noirq) 900 }; 901 #define DEV_PM_OPS &cpg_mssr_pm 902 #else 903 #define DEV_PM_OPS NULL 904 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 905 906 static int __init cpg_mssr_common_init(struct device *dev, 907 struct device_node *np, 908 const struct cpg_mssr_info *info) 909 { 910 struct cpg_mssr_priv *priv; 911 unsigned int nclks, i; 912 int error; 913 914 if (info->init) { 915 error = info->init(dev); 916 if (error) 917 return error; 918 } 919 920 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 921 priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL); 922 if (!priv) 923 return -ENOMEM; 924 925 priv->np = np; 926 priv->dev = dev; 927 spin_lock_init(&priv->rmw_lock); 928 929 priv->base = of_iomap(np, 0); 930 if (!priv->base) { 931 error = -ENOMEM; 932 goto out_err; 933 } 934 935 cpg_mssr_priv = priv; 936 priv->num_core_clks = info->num_total_core_clks; 937 priv->num_mod_clks = info->num_hw_mod_clks; 938 priv->last_dt_core_clk = info->last_dt_core_clk; 939 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 940 priv->stbyctrl = info->stbyctrl; 941 942 for (i = 0; i < nclks; i++) 943 priv->clks[i] = ERR_PTR(-ENOENT); 944 945 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); 946 if (error) 947 goto out_err; 948 949 return 0; 950 951 out_err: 952 if (priv->base) 953 iounmap(priv->base); 954 kfree(priv); 955 956 return error; 957 } 958 959 void __init cpg_mssr_early_init(struct device_node *np, 960 const struct cpg_mssr_info *info) 961 { 962 int error; 963 int i; 964 965 error = cpg_mssr_common_init(NULL, np, info); 966 if (error) 967 return; 968 969 for (i = 0; i < info->num_early_core_clks; i++) 970 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, 971 cpg_mssr_priv); 972 973 for (i = 0; i < info->num_early_mod_clks; i++) 974 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, 975 cpg_mssr_priv); 976 977 } 978 979 static int __init cpg_mssr_probe(struct platform_device *pdev) 980 { 981 struct device *dev = &pdev->dev; 982 struct device_node *np = dev->of_node; 983 const struct cpg_mssr_info *info; 984 struct cpg_mssr_priv *priv; 985 unsigned int i; 986 int error; 987 988 info = of_device_get_match_data(dev); 989 990 if (!cpg_mssr_priv) { 991 error = cpg_mssr_common_init(dev, dev->of_node, info); 992 if (error) 993 return error; 994 } 995 996 priv = cpg_mssr_priv; 997 priv->dev = dev; 998 dev_set_drvdata(dev, priv); 999 1000 for (i = 0; i < info->num_core_clks; i++) 1001 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 1002 1003 for (i = 0; i < info->num_mod_clks; i++) 1004 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 1005 1006 error = devm_add_action_or_reset(dev, 1007 cpg_mssr_del_clk_provider, 1008 np); 1009 if (error) 1010 return error; 1011 1012 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, 1013 info->num_core_pm_clks); 1014 if (error) 1015 return error; 1016 1017 /* Reset Controller not supported for Standby Control SoCs */ 1018 if (info->stbyctrl) 1019 return 0; 1020 1021 error = cpg_mssr_reset_controller_register(priv); 1022 if (error) 1023 return error; 1024 1025 return 0; 1026 } 1027 1028 static struct platform_driver cpg_mssr_driver = { 1029 .driver = { 1030 .name = "renesas-cpg-mssr", 1031 .of_match_table = cpg_mssr_match, 1032 .pm = DEV_PM_OPS, 1033 }, 1034 }; 1035 1036 static int __init cpg_mssr_init(void) 1037 { 1038 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); 1039 } 1040 1041 subsys_initcall(cpg_mssr_init); 1042 1043 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks, 1044 unsigned int num_core_clks, 1045 unsigned int first_clk, 1046 unsigned int last_clk) 1047 { 1048 unsigned int i; 1049 1050 for (i = 0; i < num_core_clks; i++) 1051 if (core_clks[i].id >= first_clk && 1052 core_clks[i].id <= last_clk) 1053 core_clks[i].name = NULL; 1054 } 1055 1056 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 1057 unsigned int num_mod_clks, 1058 const unsigned int *clks, unsigned int n) 1059 { 1060 unsigned int i, j; 1061 1062 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1063 if (mod_clks[i].id == clks[j]) { 1064 mod_clks[i].name = NULL; 1065 j++; 1066 } 1067 } 1068 1069 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks, 1070 unsigned int num_mod_clks, 1071 const struct mssr_mod_reparent *clks, 1072 unsigned int n) 1073 { 1074 unsigned int i, j; 1075 1076 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1077 if (mod_clks[i].id == clks[j].clk) { 1078 mod_clks[i].parent = clks[j].parent; 1079 j++; 1080 } 1081 } 1082 1083 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 1084 MODULE_LICENSE("GPL v2"); 1085