1 /* 2 * Renesas Clock Pulse Generator / Module Standby and Software Reset 3 * 4 * Copyright (C) 2015 Glider bvba 5 * 6 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 7 * 8 * Copyright (C) 2013 Ideas On Board SPRL 9 * Copyright (C) 2015 Renesas Electronics Corp. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; version 2 of the License. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/clk/renesas.h> 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/init.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/module.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_clock.h> 28 #include <linux/pm_domain.h> 29 #include <linux/psci.h> 30 #include <linux/reset-controller.h> 31 #include <linux/slab.h> 32 33 #include <dt-bindings/clock/renesas-cpg-mssr.h> 34 35 #include "renesas-cpg-mssr.h" 36 #include "clk-div6.h" 37 38 #ifdef DEBUG 39 #define WARN_DEBUG(x) WARN_ON(x) 40 #else 41 #define WARN_DEBUG(x) do { } while (0) 42 #endif 43 44 45 /* 46 * Module Standby and Software Reset register offets. 47 * 48 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 49 * R-Car Gen2, R-Car Gen3, and RZ/G1. 50 * These are NOT valid for R-Car Gen1 and RZ/A1! 51 */ 52 53 /* 54 * Module Stop Status Register offsets 55 */ 56 57 static const u16 mstpsr[] = { 58 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 59 0x9A0, 0x9A4, 0x9A8, 0x9AC, 60 }; 61 62 #define MSTPSR(i) mstpsr[i] 63 64 65 /* 66 * System Module Stop Control Register offsets 67 */ 68 69 static const u16 smstpcr[] = { 70 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 71 0x990, 0x994, 0x998, 0x99C, 72 }; 73 74 #define SMSTPCR(i) smstpcr[i] 75 76 77 /* 78 * Software Reset Register offsets 79 */ 80 81 static const u16 srcr[] = { 82 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 83 0x920, 0x924, 0x928, 0x92C, 84 }; 85 86 #define SRCR(i) srcr[i] 87 88 89 /* Realtime Module Stop Control Register offsets */ 90 #define RMSTPCR(i) (smstpcr[i] - 0x20) 91 92 /* Modem Module Stop Control Register offsets (r8a73a4) */ 93 #define MMSTPCR(i) (smstpcr[i] + 0x20) 94 95 /* Software Reset Clearing Register offsets */ 96 #define SRSTCLR(i) (0x940 + (i) * 4) 97 98 99 /** 100 * Clock Pulse Generator / Module Standby and Software Reset Private Data 101 * 102 * @rcdev: Optional reset controller entity 103 * @dev: CPG/MSSR device 104 * @base: CPG/MSSR register block base address 105 * @rmw_lock: protects RMW register accesses 106 * @clks: Array containing all Core and Module Clocks 107 * @num_core_clks: Number of Core Clocks in clks[] 108 * @num_mod_clks: Number of Module Clocks in clks[] 109 * @last_dt_core_clk: ID of the last Core Clock exported to DT 110 * @notifiers: Notifier chain to save/restore clock state for system resume 111 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control 112 * @smstpcr_saved[].val: Saved values of SMSTPCR[] 113 */ 114 struct cpg_mssr_priv { 115 #ifdef CONFIG_RESET_CONTROLLER 116 struct reset_controller_dev rcdev; 117 #endif 118 struct device *dev; 119 void __iomem *base; 120 spinlock_t rmw_lock; 121 122 struct clk **clks; 123 unsigned int num_core_clks; 124 unsigned int num_mod_clks; 125 unsigned int last_dt_core_clk; 126 127 struct raw_notifier_head notifiers; 128 struct { 129 u32 mask; 130 u32 val; 131 } smstpcr_saved[ARRAY_SIZE(smstpcr)]; 132 }; 133 134 135 /** 136 * struct mstp_clock - MSTP gating clock 137 * @hw: handle between common and hardware-specific interfaces 138 * @index: MSTP clock number 139 * @priv: CPG/MSSR private data 140 */ 141 struct mstp_clock { 142 struct clk_hw hw; 143 u32 index; 144 struct cpg_mssr_priv *priv; 145 }; 146 147 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) 148 149 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 150 { 151 struct mstp_clock *clock = to_mstp_clock(hw); 152 struct cpg_mssr_priv *priv = clock->priv; 153 unsigned int reg = clock->index / 32; 154 unsigned int bit = clock->index % 32; 155 struct device *dev = priv->dev; 156 u32 bitmask = BIT(bit); 157 unsigned long flags; 158 unsigned int i; 159 u32 value; 160 161 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 162 enable ? "ON" : "OFF"); 163 spin_lock_irqsave(&priv->rmw_lock, flags); 164 165 value = readl(priv->base + SMSTPCR(reg)); 166 if (enable) 167 value &= ~bitmask; 168 else 169 value |= bitmask; 170 writel(value, priv->base + SMSTPCR(reg)); 171 172 spin_unlock_irqrestore(&priv->rmw_lock, flags); 173 174 if (!enable) 175 return 0; 176 177 for (i = 1000; i > 0; --i) { 178 if (!(readl(priv->base + MSTPSR(reg)) & bitmask)) 179 break; 180 cpu_relax(); 181 } 182 183 if (!i) { 184 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 185 priv->base + SMSTPCR(reg), bit); 186 return -ETIMEDOUT; 187 } 188 189 return 0; 190 } 191 192 static int cpg_mstp_clock_enable(struct clk_hw *hw) 193 { 194 return cpg_mstp_clock_endisable(hw, true); 195 } 196 197 static void cpg_mstp_clock_disable(struct clk_hw *hw) 198 { 199 cpg_mstp_clock_endisable(hw, false); 200 } 201 202 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 203 { 204 struct mstp_clock *clock = to_mstp_clock(hw); 205 struct cpg_mssr_priv *priv = clock->priv; 206 u32 value; 207 208 value = readl(priv->base + MSTPSR(clock->index / 32)); 209 210 return !(value & BIT(clock->index % 32)); 211 } 212 213 static const struct clk_ops cpg_mstp_clock_ops = { 214 .enable = cpg_mstp_clock_enable, 215 .disable = cpg_mstp_clock_disable, 216 .is_enabled = cpg_mstp_clock_is_enabled, 217 }; 218 219 static 220 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 221 void *data) 222 { 223 unsigned int clkidx = clkspec->args[1]; 224 struct cpg_mssr_priv *priv = data; 225 struct device *dev = priv->dev; 226 unsigned int idx; 227 const char *type; 228 struct clk *clk; 229 230 switch (clkspec->args[0]) { 231 case CPG_CORE: 232 type = "core"; 233 if (clkidx > priv->last_dt_core_clk) { 234 dev_err(dev, "Invalid %s clock index %u\n", type, 235 clkidx); 236 return ERR_PTR(-EINVAL); 237 } 238 clk = priv->clks[clkidx]; 239 break; 240 241 case CPG_MOD: 242 type = "module"; 243 idx = MOD_CLK_PACK(clkidx); 244 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) { 245 dev_err(dev, "Invalid %s clock index %u\n", type, 246 clkidx); 247 return ERR_PTR(-EINVAL); 248 } 249 clk = priv->clks[priv->num_core_clks + idx]; 250 break; 251 252 default: 253 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); 254 return ERR_PTR(-EINVAL); 255 } 256 257 if (IS_ERR(clk)) 258 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, 259 PTR_ERR(clk)); 260 else 261 dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n", 262 clkspec->args[0], clkspec->args[1], clk, clk); 263 return clk; 264 } 265 266 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 267 const struct cpg_mssr_info *info, 268 struct cpg_mssr_priv *priv) 269 { 270 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; 271 struct device *dev = priv->dev; 272 unsigned int id = core->id, div = core->div; 273 const char *parent_name; 274 275 WARN_DEBUG(id >= priv->num_core_clks); 276 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 277 278 if (!core->name) { 279 /* Skip NULLified clock */ 280 return; 281 } 282 283 switch (core->type) { 284 case CLK_TYPE_IN: 285 clk = of_clk_get_by_name(priv->dev->of_node, core->name); 286 break; 287 288 case CLK_TYPE_FF: 289 case CLK_TYPE_DIV6P1: 290 case CLK_TYPE_DIV6_RO: 291 WARN_DEBUG(core->parent >= priv->num_core_clks); 292 parent = priv->clks[core->parent]; 293 if (IS_ERR(parent)) { 294 clk = parent; 295 goto fail; 296 } 297 298 parent_name = __clk_get_name(parent); 299 300 if (core->type == CLK_TYPE_DIV6_RO) 301 /* Multiply with the DIV6 register value */ 302 div *= (readl(priv->base + core->offset) & 0x3f) + 1; 303 304 if (core->type == CLK_TYPE_DIV6P1) { 305 clk = cpg_div6_register(core->name, 1, &parent_name, 306 priv->base + core->offset, 307 &priv->notifiers); 308 } else { 309 clk = clk_register_fixed_factor(NULL, core->name, 310 parent_name, 0, 311 core->mult, div); 312 } 313 break; 314 315 default: 316 if (info->cpg_clk_register) 317 clk = info->cpg_clk_register(dev, core, info, 318 priv->clks, priv->base, 319 &priv->notifiers); 320 else 321 dev_err(dev, "%s has unsupported core clock type %u\n", 322 core->name, core->type); 323 break; 324 } 325 326 if (IS_ERR_OR_NULL(clk)) 327 goto fail; 328 329 dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk); 330 priv->clks[id] = clk; 331 return; 332 333 fail: 334 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", 335 core->name, PTR_ERR(clk)); 336 } 337 338 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 339 const struct cpg_mssr_info *info, 340 struct cpg_mssr_priv *priv) 341 { 342 struct mstp_clock *clock = NULL; 343 struct device *dev = priv->dev; 344 unsigned int id = mod->id; 345 struct clk_init_data init; 346 struct clk *parent, *clk; 347 const char *parent_name; 348 unsigned int i; 349 350 WARN_DEBUG(id < priv->num_core_clks); 351 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 352 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 353 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 354 355 if (!mod->name) { 356 /* Skip NULLified clock */ 357 return; 358 } 359 360 parent = priv->clks[mod->parent]; 361 if (IS_ERR(parent)) { 362 clk = parent; 363 goto fail; 364 } 365 366 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 367 if (!clock) { 368 clk = ERR_PTR(-ENOMEM); 369 goto fail; 370 } 371 372 init.name = mod->name; 373 init.ops = &cpg_mstp_clock_ops; 374 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; 375 for (i = 0; i < info->num_crit_mod_clks; i++) 376 if (id == info->crit_mod_clks[i]) { 377 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", 378 mod->name); 379 init.flags |= CLK_IS_CRITICAL; 380 break; 381 } 382 383 parent_name = __clk_get_name(parent); 384 init.parent_names = &parent_name; 385 init.num_parents = 1; 386 387 clock->index = id - priv->num_core_clks; 388 clock->priv = priv; 389 clock->hw.init = &init; 390 391 clk = clk_register(NULL, &clock->hw); 392 if (IS_ERR(clk)) 393 goto fail; 394 395 dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk); 396 priv->clks[id] = clk; 397 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); 398 return; 399 400 fail: 401 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", 402 mod->name, PTR_ERR(clk)); 403 kfree(clock); 404 } 405 406 struct cpg_mssr_clk_domain { 407 struct generic_pm_domain genpd; 408 struct device_node *np; 409 unsigned int num_core_pm_clks; 410 unsigned int core_pm_clks[0]; 411 }; 412 413 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; 414 415 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, 416 struct cpg_mssr_clk_domain *pd) 417 { 418 unsigned int i; 419 420 if (clkspec->np != pd->np || clkspec->args_count != 2) 421 return false; 422 423 switch (clkspec->args[0]) { 424 case CPG_CORE: 425 for (i = 0; i < pd->num_core_pm_clks; i++) 426 if (clkspec->args[1] == pd->core_pm_clks[i]) 427 return true; 428 return false; 429 430 case CPG_MOD: 431 return true; 432 433 default: 434 return false; 435 } 436 } 437 438 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) 439 { 440 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; 441 struct device_node *np = dev->of_node; 442 struct of_phandle_args clkspec; 443 struct clk *clk; 444 int i = 0; 445 int error; 446 447 if (!pd) { 448 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); 449 return -EPROBE_DEFER; 450 } 451 452 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 453 &clkspec)) { 454 if (cpg_mssr_is_pm_clk(&clkspec, pd)) 455 goto found; 456 457 of_node_put(clkspec.np); 458 i++; 459 } 460 461 return 0; 462 463 found: 464 clk = of_clk_get_from_provider(&clkspec); 465 of_node_put(clkspec.np); 466 467 if (IS_ERR(clk)) 468 return PTR_ERR(clk); 469 470 error = pm_clk_create(dev); 471 if (error) { 472 dev_err(dev, "pm_clk_create failed %d\n", error); 473 goto fail_put; 474 } 475 476 error = pm_clk_add_clk(dev, clk); 477 if (error) { 478 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error); 479 goto fail_destroy; 480 } 481 482 return 0; 483 484 fail_destroy: 485 pm_clk_destroy(dev); 486 fail_put: 487 clk_put(clk); 488 return error; 489 } 490 491 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) 492 { 493 if (!pm_clk_no_clocks(dev)) 494 pm_clk_destroy(dev); 495 } 496 497 static int __init cpg_mssr_add_clk_domain(struct device *dev, 498 const unsigned int *core_pm_clks, 499 unsigned int num_core_pm_clks) 500 { 501 struct device_node *np = dev->of_node; 502 struct generic_pm_domain *genpd; 503 struct cpg_mssr_clk_domain *pd; 504 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); 505 506 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); 507 if (!pd) 508 return -ENOMEM; 509 510 pd->np = np; 511 pd->num_core_pm_clks = num_core_pm_clks; 512 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); 513 514 genpd = &pd->genpd; 515 genpd->name = np->name; 516 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; 517 genpd->attach_dev = cpg_mssr_attach_dev; 518 genpd->detach_dev = cpg_mssr_detach_dev; 519 pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 520 cpg_mssr_clk_domain = pd; 521 522 of_genpd_add_provider_simple(np, genpd); 523 return 0; 524 } 525 526 #ifdef CONFIG_RESET_CONTROLLER 527 528 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) 529 530 static int cpg_mssr_reset(struct reset_controller_dev *rcdev, 531 unsigned long id) 532 { 533 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 534 unsigned int reg = id / 32; 535 unsigned int bit = id % 32; 536 u32 bitmask = BIT(bit); 537 unsigned long flags; 538 u32 value; 539 540 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 541 542 /* Reset module */ 543 spin_lock_irqsave(&priv->rmw_lock, flags); 544 value = readl(priv->base + SRCR(reg)); 545 value |= bitmask; 546 writel(value, priv->base + SRCR(reg)); 547 spin_unlock_irqrestore(&priv->rmw_lock, flags); 548 549 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 550 udelay(35); 551 552 /* Release module from reset state */ 553 writel(bitmask, priv->base + SRSTCLR(reg)); 554 555 return 0; 556 } 557 558 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) 559 { 560 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 561 unsigned int reg = id / 32; 562 unsigned int bit = id % 32; 563 u32 bitmask = BIT(bit); 564 unsigned long flags; 565 u32 value; 566 567 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 568 569 spin_lock_irqsave(&priv->rmw_lock, flags); 570 value = readl(priv->base + SRCR(reg)); 571 value |= bitmask; 572 writel(value, priv->base + SRCR(reg)); 573 spin_unlock_irqrestore(&priv->rmw_lock, flags); 574 return 0; 575 } 576 577 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, 578 unsigned long id) 579 { 580 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 581 unsigned int reg = id / 32; 582 unsigned int bit = id % 32; 583 u32 bitmask = BIT(bit); 584 585 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 586 587 writel(bitmask, priv->base + SRSTCLR(reg)); 588 return 0; 589 } 590 591 static int cpg_mssr_status(struct reset_controller_dev *rcdev, 592 unsigned long id) 593 { 594 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 595 unsigned int reg = id / 32; 596 unsigned int bit = id % 32; 597 u32 bitmask = BIT(bit); 598 599 return !!(readl(priv->base + SRCR(reg)) & bitmask); 600 } 601 602 static const struct reset_control_ops cpg_mssr_reset_ops = { 603 .reset = cpg_mssr_reset, 604 .assert = cpg_mssr_assert, 605 .deassert = cpg_mssr_deassert, 606 .status = cpg_mssr_status, 607 }; 608 609 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, 610 const struct of_phandle_args *reset_spec) 611 { 612 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 613 unsigned int unpacked = reset_spec->args[0]; 614 unsigned int idx = MOD_CLK_PACK(unpacked); 615 616 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { 617 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); 618 return -EINVAL; 619 } 620 621 return idx; 622 } 623 624 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 625 { 626 priv->rcdev.ops = &cpg_mssr_reset_ops; 627 priv->rcdev.of_node = priv->dev->of_node; 628 priv->rcdev.of_reset_n_cells = 1; 629 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; 630 priv->rcdev.nr_resets = priv->num_mod_clks; 631 return devm_reset_controller_register(priv->dev, &priv->rcdev); 632 } 633 634 #else /* !CONFIG_RESET_CONTROLLER */ 635 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 636 { 637 return 0; 638 } 639 #endif /* !CONFIG_RESET_CONTROLLER */ 640 641 642 static const struct of_device_id cpg_mssr_match[] = { 643 #ifdef CONFIG_CLK_R8A7743 644 { 645 .compatible = "renesas,r8a7743-cpg-mssr", 646 .data = &r8a7743_cpg_mssr_info, 647 }, 648 #endif 649 #ifdef CONFIG_CLK_R8A7745 650 { 651 .compatible = "renesas,r8a7745-cpg-mssr", 652 .data = &r8a7745_cpg_mssr_info, 653 }, 654 #endif 655 #ifdef CONFIG_CLK_R8A7790 656 { 657 .compatible = "renesas,r8a7790-cpg-mssr", 658 .data = &r8a7790_cpg_mssr_info, 659 }, 660 #endif 661 #ifdef CONFIG_CLK_R8A7791 662 { 663 .compatible = "renesas,r8a7791-cpg-mssr", 664 .data = &r8a7791_cpg_mssr_info, 665 }, 666 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ 667 { 668 .compatible = "renesas,r8a7793-cpg-mssr", 669 .data = &r8a7791_cpg_mssr_info, 670 }, 671 #endif 672 #ifdef CONFIG_CLK_R8A7792 673 { 674 .compatible = "renesas,r8a7792-cpg-mssr", 675 .data = &r8a7792_cpg_mssr_info, 676 }, 677 #endif 678 #ifdef CONFIG_CLK_R8A7794 679 { 680 .compatible = "renesas,r8a7794-cpg-mssr", 681 .data = &r8a7794_cpg_mssr_info, 682 }, 683 #endif 684 #ifdef CONFIG_CLK_R8A7795 685 { 686 .compatible = "renesas,r8a7795-cpg-mssr", 687 .data = &r8a7795_cpg_mssr_info, 688 }, 689 #endif 690 #ifdef CONFIG_CLK_R8A7796 691 { 692 .compatible = "renesas,r8a7796-cpg-mssr", 693 .data = &r8a7796_cpg_mssr_info, 694 }, 695 #endif 696 #ifdef CONFIG_CLK_R8A77970 697 { 698 .compatible = "renesas,r8a77970-cpg-mssr", 699 .data = &r8a77970_cpg_mssr_info, 700 }, 701 #endif 702 #ifdef CONFIG_CLK_R8A77995 703 { 704 .compatible = "renesas,r8a77995-cpg-mssr", 705 .data = &r8a77995_cpg_mssr_info, 706 }, 707 #endif 708 { /* sentinel */ } 709 }; 710 711 static void cpg_mssr_del_clk_provider(void *data) 712 { 713 of_clk_del_provider(data); 714 } 715 716 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 717 static int cpg_mssr_suspend_noirq(struct device *dev) 718 { 719 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 720 unsigned int reg; 721 722 /* This is the best we can do to check for the presence of PSCI */ 723 if (!psci_ops.cpu_suspend) 724 return 0; 725 726 /* Save module registers with bits under our control */ 727 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 728 if (priv->smstpcr_saved[reg].mask) 729 priv->smstpcr_saved[reg].val = 730 readl(priv->base + SMSTPCR(reg)); 731 } 732 733 /* Save core clocks */ 734 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); 735 736 return 0; 737 } 738 739 static int cpg_mssr_resume_noirq(struct device *dev) 740 { 741 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 742 unsigned int reg, i; 743 u32 mask, oldval, newval; 744 745 /* This is the best we can do to check for the presence of PSCI */ 746 if (!psci_ops.cpu_suspend) 747 return 0; 748 749 /* Restore core clocks */ 750 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); 751 752 /* Restore module clocks */ 753 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 754 mask = priv->smstpcr_saved[reg].mask; 755 if (!mask) 756 continue; 757 758 oldval = readl(priv->base + SMSTPCR(reg)); 759 newval = oldval & ~mask; 760 newval |= priv->smstpcr_saved[reg].val & mask; 761 if (newval == oldval) 762 continue; 763 764 writel(newval, priv->base + SMSTPCR(reg)); 765 766 /* Wait until enabled clocks are really enabled */ 767 mask &= ~priv->smstpcr_saved[reg].val; 768 if (!mask) 769 continue; 770 771 for (i = 1000; i > 0; --i) { 772 oldval = readl(priv->base + MSTPSR(reg)); 773 if (!(oldval & mask)) 774 break; 775 cpu_relax(); 776 } 777 778 if (!i) 779 dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n", 780 priv->base + SMSTPCR(reg), oldval & mask); 781 } 782 783 return 0; 784 } 785 786 static const struct dev_pm_ops cpg_mssr_pm = { 787 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq, 788 cpg_mssr_resume_noirq) 789 }; 790 #define DEV_PM_OPS &cpg_mssr_pm 791 #else 792 #define DEV_PM_OPS NULL 793 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 794 795 static int __init cpg_mssr_probe(struct platform_device *pdev) 796 { 797 struct device *dev = &pdev->dev; 798 struct device_node *np = dev->of_node; 799 const struct cpg_mssr_info *info; 800 struct cpg_mssr_priv *priv; 801 unsigned int nclks, i; 802 struct resource *res; 803 struct clk **clks; 804 int error; 805 806 info = of_device_get_match_data(dev); 807 if (info->init) { 808 error = info->init(dev); 809 if (error) 810 return error; 811 } 812 813 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 814 if (!priv) 815 return -ENOMEM; 816 817 priv->dev = dev; 818 spin_lock_init(&priv->rmw_lock); 819 820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 821 priv->base = devm_ioremap_resource(dev, res); 822 if (IS_ERR(priv->base)) 823 return PTR_ERR(priv->base); 824 825 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 826 clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL); 827 if (!clks) 828 return -ENOMEM; 829 830 dev_set_drvdata(dev, priv); 831 priv->clks = clks; 832 priv->num_core_clks = info->num_total_core_clks; 833 priv->num_mod_clks = info->num_hw_mod_clks; 834 priv->last_dt_core_clk = info->last_dt_core_clk; 835 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 836 837 for (i = 0; i < nclks; i++) 838 clks[i] = ERR_PTR(-ENOENT); 839 840 for (i = 0; i < info->num_core_clks; i++) 841 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 842 843 for (i = 0; i < info->num_mod_clks; i++) 844 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 845 846 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); 847 if (error) 848 return error; 849 850 error = devm_add_action_or_reset(dev, 851 cpg_mssr_del_clk_provider, 852 np); 853 if (error) 854 return error; 855 856 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, 857 info->num_core_pm_clks); 858 if (error) 859 return error; 860 861 error = cpg_mssr_reset_controller_register(priv); 862 if (error) 863 return error; 864 865 return 0; 866 } 867 868 static struct platform_driver cpg_mssr_driver = { 869 .driver = { 870 .name = "renesas-cpg-mssr", 871 .of_match_table = cpg_mssr_match, 872 .pm = DEV_PM_OPS, 873 }, 874 }; 875 876 static int __init cpg_mssr_init(void) 877 { 878 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); 879 } 880 881 subsys_initcall(cpg_mssr_init); 882 883 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks, 884 unsigned int num_core_clks, 885 unsigned int first_clk, 886 unsigned int last_clk) 887 { 888 unsigned int i; 889 890 for (i = 0; i < num_core_clks; i++) 891 if (core_clks[i].id >= first_clk && 892 core_clks[i].id <= last_clk) 893 core_clks[i].name = NULL; 894 } 895 896 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 897 unsigned int num_mod_clks, 898 const unsigned int *clks, unsigned int n) 899 { 900 unsigned int i, j; 901 902 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 903 if (mod_clks[i].id == clks[j]) { 904 mod_clks[i].name = NULL; 905 j++; 906 } 907 } 908 909 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks, 910 unsigned int num_mod_clks, 911 const struct mssr_mod_reparent *clks, 912 unsigned int n) 913 { 914 unsigned int i, j; 915 916 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 917 if (mod_clks[i].id == clks[j].clk) { 918 mod_clks[i].parent = clks[j].parent; 919 j++; 920 } 921 } 922 923 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 924 MODULE_LICENSE("GPL v2"); 925