1 /* 2 * Renesas Clock Pulse Generator / Module Standby and Software Reset 3 * 4 * Copyright (C) 2015 Glider bvba 5 * 6 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 7 * 8 * Copyright (C) 2013 Ideas On Board SPRL 9 * Copyright (C) 2015 Renesas Electronics Corp. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; version 2 of the License. 14 */ 15 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/clk/renesas.h> 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/init.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/module.h> 24 #include <linux/of_address.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_clock.h> 28 #include <linux/pm_domain.h> 29 #include <linux/reset-controller.h> 30 #include <linux/slab.h> 31 32 #include <dt-bindings/clock/renesas-cpg-mssr.h> 33 34 #include "renesas-cpg-mssr.h" 35 #include "clk-div6.h" 36 37 #ifdef DEBUG 38 #define WARN_DEBUG(x) WARN_ON(x) 39 #else 40 #define WARN_DEBUG(x) do { } while (0) 41 #endif 42 43 44 /* 45 * Module Standby and Software Reset register offets. 46 * 47 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 48 * R-Car Gen2, R-Car Gen3, and RZ/G1. 49 * These are NOT valid for R-Car Gen1 and RZ/A1! 50 */ 51 52 /* 53 * Module Stop Status Register offsets 54 */ 55 56 static const u16 mstpsr[] = { 57 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 58 0x9A0, 0x9A4, 0x9A8, 0x9AC, 59 }; 60 61 #define MSTPSR(i) mstpsr[i] 62 63 64 /* 65 * System Module Stop Control Register offsets 66 */ 67 68 static const u16 smstpcr[] = { 69 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 70 0x990, 0x994, 0x998, 0x99C, 71 }; 72 73 #define SMSTPCR(i) smstpcr[i] 74 75 76 /* 77 * Software Reset Register offsets 78 */ 79 80 static const u16 srcr[] = { 81 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 82 0x920, 0x924, 0x928, 0x92C, 83 }; 84 85 #define SRCR(i) srcr[i] 86 87 88 /* Realtime Module Stop Control Register offsets */ 89 #define RMSTPCR(i) (smstpcr[i] - 0x20) 90 91 /* Modem Module Stop Control Register offsets (r8a73a4) */ 92 #define MMSTPCR(i) (smstpcr[i] + 0x20) 93 94 /* Software Reset Clearing Register offsets */ 95 #define SRSTCLR(i) (0x940 + (i) * 4) 96 97 98 /** 99 * Clock Pulse Generator / Module Standby and Software Reset Private Data 100 * 101 * @rcdev: Optional reset controller entity 102 * @dev: CPG/MSSR device 103 * @base: CPG/MSSR register block base address 104 * @rmw_lock: protects RMW register accesses 105 * @clks: Array containing all Core and Module Clocks 106 * @num_core_clks: Number of Core Clocks in clks[] 107 * @num_mod_clks: Number of Module Clocks in clks[] 108 * @last_dt_core_clk: ID of the last Core Clock exported to DT 109 */ 110 struct cpg_mssr_priv { 111 #ifdef CONFIG_RESET_CONTROLLER 112 struct reset_controller_dev rcdev; 113 #endif 114 struct device *dev; 115 void __iomem *base; 116 spinlock_t rmw_lock; 117 118 struct clk **clks; 119 unsigned int num_core_clks; 120 unsigned int num_mod_clks; 121 unsigned int last_dt_core_clk; 122 }; 123 124 125 /** 126 * struct mstp_clock - MSTP gating clock 127 * @hw: handle between common and hardware-specific interfaces 128 * @index: MSTP clock number 129 * @priv: CPG/MSSR private data 130 */ 131 struct mstp_clock { 132 struct clk_hw hw; 133 u32 index; 134 struct cpg_mssr_priv *priv; 135 }; 136 137 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) 138 139 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 140 { 141 struct mstp_clock *clock = to_mstp_clock(hw); 142 struct cpg_mssr_priv *priv = clock->priv; 143 unsigned int reg = clock->index / 32; 144 unsigned int bit = clock->index % 32; 145 struct device *dev = priv->dev; 146 u32 bitmask = BIT(bit); 147 unsigned long flags; 148 unsigned int i; 149 u32 value; 150 151 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 152 enable ? "ON" : "OFF"); 153 spin_lock_irqsave(&priv->rmw_lock, flags); 154 155 value = readl(priv->base + SMSTPCR(reg)); 156 if (enable) 157 value &= ~bitmask; 158 else 159 value |= bitmask; 160 writel(value, priv->base + SMSTPCR(reg)); 161 162 spin_unlock_irqrestore(&priv->rmw_lock, flags); 163 164 if (!enable) 165 return 0; 166 167 for (i = 1000; i > 0; --i) { 168 if (!(readl(priv->base + MSTPSR(reg)) & bitmask)) 169 break; 170 cpu_relax(); 171 } 172 173 if (!i) { 174 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 175 priv->base + SMSTPCR(reg), bit); 176 return -ETIMEDOUT; 177 } 178 179 return 0; 180 } 181 182 static int cpg_mstp_clock_enable(struct clk_hw *hw) 183 { 184 return cpg_mstp_clock_endisable(hw, true); 185 } 186 187 static void cpg_mstp_clock_disable(struct clk_hw *hw) 188 { 189 cpg_mstp_clock_endisable(hw, false); 190 } 191 192 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 193 { 194 struct mstp_clock *clock = to_mstp_clock(hw); 195 struct cpg_mssr_priv *priv = clock->priv; 196 u32 value; 197 198 value = readl(priv->base + MSTPSR(clock->index / 32)); 199 200 return !(value & BIT(clock->index % 32)); 201 } 202 203 static const struct clk_ops cpg_mstp_clock_ops = { 204 .enable = cpg_mstp_clock_enable, 205 .disable = cpg_mstp_clock_disable, 206 .is_enabled = cpg_mstp_clock_is_enabled, 207 }; 208 209 static 210 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 211 void *data) 212 { 213 unsigned int clkidx = clkspec->args[1]; 214 struct cpg_mssr_priv *priv = data; 215 struct device *dev = priv->dev; 216 unsigned int idx; 217 const char *type; 218 struct clk *clk; 219 220 switch (clkspec->args[0]) { 221 case CPG_CORE: 222 type = "core"; 223 if (clkidx > priv->last_dt_core_clk) { 224 dev_err(dev, "Invalid %s clock index %u\n", type, 225 clkidx); 226 return ERR_PTR(-EINVAL); 227 } 228 clk = priv->clks[clkidx]; 229 break; 230 231 case CPG_MOD: 232 type = "module"; 233 idx = MOD_CLK_PACK(clkidx); 234 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) { 235 dev_err(dev, "Invalid %s clock index %u\n", type, 236 clkidx); 237 return ERR_PTR(-EINVAL); 238 } 239 clk = priv->clks[priv->num_core_clks + idx]; 240 break; 241 242 default: 243 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); 244 return ERR_PTR(-EINVAL); 245 } 246 247 if (IS_ERR(clk)) 248 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, 249 PTR_ERR(clk)); 250 else 251 dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n", 252 clkspec->args[0], clkspec->args[1], clk, clk); 253 return clk; 254 } 255 256 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 257 const struct cpg_mssr_info *info, 258 struct cpg_mssr_priv *priv) 259 { 260 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; 261 struct device *dev = priv->dev; 262 unsigned int id = core->id, div = core->div; 263 const char *parent_name; 264 265 WARN_DEBUG(id >= priv->num_core_clks); 266 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 267 268 if (!core->name) { 269 /* Skip NULLified clock */ 270 return; 271 } 272 273 switch (core->type) { 274 case CLK_TYPE_IN: 275 clk = of_clk_get_by_name(priv->dev->of_node, core->name); 276 break; 277 278 case CLK_TYPE_FF: 279 case CLK_TYPE_DIV6P1: 280 case CLK_TYPE_DIV6_RO: 281 WARN_DEBUG(core->parent >= priv->num_core_clks); 282 parent = priv->clks[core->parent]; 283 if (IS_ERR(parent)) { 284 clk = parent; 285 goto fail; 286 } 287 288 parent_name = __clk_get_name(parent); 289 290 if (core->type == CLK_TYPE_DIV6_RO) 291 /* Multiply with the DIV6 register value */ 292 div *= (readl(priv->base + core->offset) & 0x3f) + 1; 293 294 if (core->type == CLK_TYPE_DIV6P1) { 295 clk = cpg_div6_register(core->name, 1, &parent_name, 296 priv->base + core->offset); 297 } else { 298 clk = clk_register_fixed_factor(NULL, core->name, 299 parent_name, 0, 300 core->mult, div); 301 } 302 break; 303 304 default: 305 if (info->cpg_clk_register) 306 clk = info->cpg_clk_register(dev, core, info, 307 priv->clks, priv->base); 308 else 309 dev_err(dev, "%s has unsupported core clock type %u\n", 310 core->name, core->type); 311 break; 312 } 313 314 if (IS_ERR_OR_NULL(clk)) 315 goto fail; 316 317 dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk); 318 priv->clks[id] = clk; 319 return; 320 321 fail: 322 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", 323 core->name, PTR_ERR(clk)); 324 } 325 326 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 327 const struct cpg_mssr_info *info, 328 struct cpg_mssr_priv *priv) 329 { 330 struct mstp_clock *clock = NULL; 331 struct device *dev = priv->dev; 332 unsigned int id = mod->id; 333 struct clk_init_data init; 334 struct clk *parent, *clk; 335 const char *parent_name; 336 unsigned int i; 337 338 WARN_DEBUG(id < priv->num_core_clks); 339 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 340 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 341 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 342 343 if (!mod->name) { 344 /* Skip NULLified clock */ 345 return; 346 } 347 348 parent = priv->clks[mod->parent]; 349 if (IS_ERR(parent)) { 350 clk = parent; 351 goto fail; 352 } 353 354 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 355 if (!clock) { 356 clk = ERR_PTR(-ENOMEM); 357 goto fail; 358 } 359 360 init.name = mod->name; 361 init.ops = &cpg_mstp_clock_ops; 362 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; 363 for (i = 0; i < info->num_crit_mod_clks; i++) 364 if (id == info->crit_mod_clks[i]) { 365 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", 366 mod->name); 367 init.flags |= CLK_IS_CRITICAL; 368 break; 369 } 370 371 parent_name = __clk_get_name(parent); 372 init.parent_names = &parent_name; 373 init.num_parents = 1; 374 375 clock->index = id - priv->num_core_clks; 376 clock->priv = priv; 377 clock->hw.init = &init; 378 379 clk = clk_register(NULL, &clock->hw); 380 if (IS_ERR(clk)) 381 goto fail; 382 383 dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk); 384 priv->clks[id] = clk; 385 return; 386 387 fail: 388 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", 389 mod->name, PTR_ERR(clk)); 390 kfree(clock); 391 } 392 393 struct cpg_mssr_clk_domain { 394 struct generic_pm_domain genpd; 395 struct device_node *np; 396 unsigned int num_core_pm_clks; 397 unsigned int core_pm_clks[0]; 398 }; 399 400 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; 401 402 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, 403 struct cpg_mssr_clk_domain *pd) 404 { 405 unsigned int i; 406 407 if (clkspec->np != pd->np || clkspec->args_count != 2) 408 return false; 409 410 switch (clkspec->args[0]) { 411 case CPG_CORE: 412 for (i = 0; i < pd->num_core_pm_clks; i++) 413 if (clkspec->args[1] == pd->core_pm_clks[i]) 414 return true; 415 return false; 416 417 case CPG_MOD: 418 return true; 419 420 default: 421 return false; 422 } 423 } 424 425 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) 426 { 427 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; 428 struct device_node *np = dev->of_node; 429 struct of_phandle_args clkspec; 430 struct clk *clk; 431 int i = 0; 432 int error; 433 434 if (!pd) { 435 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); 436 return -EPROBE_DEFER; 437 } 438 439 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 440 &clkspec)) { 441 if (cpg_mssr_is_pm_clk(&clkspec, pd)) 442 goto found; 443 444 of_node_put(clkspec.np); 445 i++; 446 } 447 448 return 0; 449 450 found: 451 clk = of_clk_get_from_provider(&clkspec); 452 of_node_put(clkspec.np); 453 454 if (IS_ERR(clk)) 455 return PTR_ERR(clk); 456 457 error = pm_clk_create(dev); 458 if (error) { 459 dev_err(dev, "pm_clk_create failed %d\n", error); 460 goto fail_put; 461 } 462 463 error = pm_clk_add_clk(dev, clk); 464 if (error) { 465 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error); 466 goto fail_destroy; 467 } 468 469 return 0; 470 471 fail_destroy: 472 pm_clk_destroy(dev); 473 fail_put: 474 clk_put(clk); 475 return error; 476 } 477 478 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) 479 { 480 if (!pm_clk_no_clocks(dev)) 481 pm_clk_destroy(dev); 482 } 483 484 static int __init cpg_mssr_add_clk_domain(struct device *dev, 485 const unsigned int *core_pm_clks, 486 unsigned int num_core_pm_clks) 487 { 488 struct device_node *np = dev->of_node; 489 struct generic_pm_domain *genpd; 490 struct cpg_mssr_clk_domain *pd; 491 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); 492 493 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); 494 if (!pd) 495 return -ENOMEM; 496 497 pd->np = np; 498 pd->num_core_pm_clks = num_core_pm_clks; 499 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); 500 501 genpd = &pd->genpd; 502 genpd->name = np->name; 503 genpd->flags = GENPD_FLAG_PM_CLK; 504 genpd->attach_dev = cpg_mssr_attach_dev; 505 genpd->detach_dev = cpg_mssr_detach_dev; 506 pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 507 cpg_mssr_clk_domain = pd; 508 509 of_genpd_add_provider_simple(np, genpd); 510 return 0; 511 } 512 513 #ifdef CONFIG_RESET_CONTROLLER 514 515 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) 516 517 static int cpg_mssr_reset(struct reset_controller_dev *rcdev, 518 unsigned long id) 519 { 520 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 521 unsigned int reg = id / 32; 522 unsigned int bit = id % 32; 523 u32 bitmask = BIT(bit); 524 unsigned long flags; 525 u32 value; 526 527 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 528 529 /* Reset module */ 530 spin_lock_irqsave(&priv->rmw_lock, flags); 531 value = readl(priv->base + SRCR(reg)); 532 value |= bitmask; 533 writel(value, priv->base + SRCR(reg)); 534 spin_unlock_irqrestore(&priv->rmw_lock, flags); 535 536 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 537 udelay(35); 538 539 /* Release module from reset state */ 540 writel(bitmask, priv->base + SRSTCLR(reg)); 541 542 return 0; 543 } 544 545 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) 546 { 547 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 548 unsigned int reg = id / 32; 549 unsigned int bit = id % 32; 550 u32 bitmask = BIT(bit); 551 unsigned long flags; 552 u32 value; 553 554 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 555 556 spin_lock_irqsave(&priv->rmw_lock, flags); 557 value = readl(priv->base + SRCR(reg)); 558 value |= bitmask; 559 writel(value, priv->base + SRCR(reg)); 560 spin_unlock_irqrestore(&priv->rmw_lock, flags); 561 return 0; 562 } 563 564 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, 565 unsigned long id) 566 { 567 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 568 unsigned int reg = id / 32; 569 unsigned int bit = id % 32; 570 u32 bitmask = BIT(bit); 571 572 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 573 574 writel(bitmask, priv->base + SRSTCLR(reg)); 575 return 0; 576 } 577 578 static int cpg_mssr_status(struct reset_controller_dev *rcdev, 579 unsigned long id) 580 { 581 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 582 unsigned int reg = id / 32; 583 unsigned int bit = id % 32; 584 u32 bitmask = BIT(bit); 585 586 return !!(readl(priv->base + SRCR(reg)) & bitmask); 587 } 588 589 static const struct reset_control_ops cpg_mssr_reset_ops = { 590 .reset = cpg_mssr_reset, 591 .assert = cpg_mssr_assert, 592 .deassert = cpg_mssr_deassert, 593 .status = cpg_mssr_status, 594 }; 595 596 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, 597 const struct of_phandle_args *reset_spec) 598 { 599 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 600 unsigned int unpacked = reset_spec->args[0]; 601 unsigned int idx = MOD_CLK_PACK(unpacked); 602 603 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { 604 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); 605 return -EINVAL; 606 } 607 608 return idx; 609 } 610 611 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 612 { 613 priv->rcdev.ops = &cpg_mssr_reset_ops; 614 priv->rcdev.of_node = priv->dev->of_node; 615 priv->rcdev.of_reset_n_cells = 1; 616 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; 617 priv->rcdev.nr_resets = priv->num_mod_clks; 618 return devm_reset_controller_register(priv->dev, &priv->rcdev); 619 } 620 621 #else /* !CONFIG_RESET_CONTROLLER */ 622 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 623 { 624 return 0; 625 } 626 #endif /* !CONFIG_RESET_CONTROLLER */ 627 628 629 static const struct of_device_id cpg_mssr_match[] = { 630 #ifdef CONFIG_CLK_R8A7743 631 { 632 .compatible = "renesas,r8a7743-cpg-mssr", 633 .data = &r8a7743_cpg_mssr_info, 634 }, 635 #endif 636 #ifdef CONFIG_CLK_R8A7745 637 { 638 .compatible = "renesas,r8a7745-cpg-mssr", 639 .data = &r8a7745_cpg_mssr_info, 640 }, 641 #endif 642 #ifdef CONFIG_CLK_R8A7790 643 { 644 .compatible = "renesas,r8a7790-cpg-mssr", 645 .data = &r8a7790_cpg_mssr_info, 646 }, 647 #endif 648 #ifdef CONFIG_CLK_R8A7791 649 { 650 .compatible = "renesas,r8a7791-cpg-mssr", 651 .data = &r8a7791_cpg_mssr_info, 652 }, 653 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ 654 { 655 .compatible = "renesas,r8a7793-cpg-mssr", 656 .data = &r8a7791_cpg_mssr_info, 657 }, 658 #endif 659 #ifdef CONFIG_CLK_R8A7792 660 { 661 .compatible = "renesas,r8a7792-cpg-mssr", 662 .data = &r8a7792_cpg_mssr_info, 663 }, 664 #endif 665 #ifdef CONFIG_CLK_R8A7794 666 { 667 .compatible = "renesas,r8a7794-cpg-mssr", 668 .data = &r8a7794_cpg_mssr_info, 669 }, 670 #endif 671 #ifdef CONFIG_CLK_R8A7795 672 { 673 .compatible = "renesas,r8a7795-cpg-mssr", 674 .data = &r8a7795_cpg_mssr_info, 675 }, 676 #endif 677 #ifdef CONFIG_CLK_R8A7796 678 { 679 .compatible = "renesas,r8a7796-cpg-mssr", 680 .data = &r8a7796_cpg_mssr_info, 681 }, 682 #endif 683 #ifdef CONFIG_CLK_R8A77995 684 { 685 .compatible = "renesas,r8a77995-cpg-mssr", 686 .data = &r8a77995_cpg_mssr_info, 687 }, 688 #endif 689 { /* sentinel */ } 690 }; 691 692 static void cpg_mssr_del_clk_provider(void *data) 693 { 694 of_clk_del_provider(data); 695 } 696 697 static int __init cpg_mssr_probe(struct platform_device *pdev) 698 { 699 struct device *dev = &pdev->dev; 700 struct device_node *np = dev->of_node; 701 const struct cpg_mssr_info *info; 702 struct cpg_mssr_priv *priv; 703 unsigned int nclks, i; 704 struct resource *res; 705 struct clk **clks; 706 int error; 707 708 info = of_device_get_match_data(dev); 709 if (info->init) { 710 error = info->init(dev); 711 if (error) 712 return error; 713 } 714 715 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 716 if (!priv) 717 return -ENOMEM; 718 719 priv->dev = dev; 720 spin_lock_init(&priv->rmw_lock); 721 722 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 723 priv->base = devm_ioremap_resource(dev, res); 724 if (IS_ERR(priv->base)) 725 return PTR_ERR(priv->base); 726 727 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 728 clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL); 729 if (!clks) 730 return -ENOMEM; 731 732 priv->clks = clks; 733 priv->num_core_clks = info->num_total_core_clks; 734 priv->num_mod_clks = info->num_hw_mod_clks; 735 priv->last_dt_core_clk = info->last_dt_core_clk; 736 737 for (i = 0; i < nclks; i++) 738 clks[i] = ERR_PTR(-ENOENT); 739 740 for (i = 0; i < info->num_core_clks; i++) 741 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 742 743 for (i = 0; i < info->num_mod_clks; i++) 744 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 745 746 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); 747 if (error) 748 return error; 749 750 error = devm_add_action_or_reset(dev, 751 cpg_mssr_del_clk_provider, 752 np); 753 if (error) 754 return error; 755 756 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, 757 info->num_core_pm_clks); 758 if (error) 759 return error; 760 761 error = cpg_mssr_reset_controller_register(priv); 762 if (error) 763 return error; 764 765 return 0; 766 } 767 768 static struct platform_driver cpg_mssr_driver = { 769 .driver = { 770 .name = "renesas-cpg-mssr", 771 .of_match_table = cpg_mssr_match, 772 }, 773 }; 774 775 static int __init cpg_mssr_init(void) 776 { 777 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); 778 } 779 780 subsys_initcall(cpg_mssr_init); 781 782 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks, 783 unsigned int num_core_clks, 784 unsigned int first_clk, 785 unsigned int last_clk) 786 { 787 unsigned int i; 788 789 for (i = 0; i < num_core_clks; i++) 790 if (core_clks[i].id >= first_clk && 791 core_clks[i].id <= last_clk) 792 core_clks[i].name = NULL; 793 } 794 795 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 796 unsigned int num_mod_clks, 797 const unsigned int *clks, unsigned int n) 798 { 799 unsigned int i, j; 800 801 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 802 if (mod_clks[i].id == clks[j]) { 803 mod_clks[i].name = NULL; 804 j++; 805 } 806 } 807 808 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks, 809 unsigned int num_mod_clks, 810 const struct mssr_mod_reparent *clks, 811 unsigned int n) 812 { 813 unsigned int i, j; 814 815 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 816 if (mod_clks[i].id == clks[j].clk) { 817 mod_clks[i].parent = clks[j].parent; 818 j++; 819 } 820 } 821 822 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 823 MODULE_LICENSE("GPL v2"); 824