1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2015 Glider bvba 6 * 7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 8 * 9 * Copyright (C) 2013 Ideas On Board SPRL 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk/renesas.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_clock.h> 26 #include <linux/pm_domain.h> 27 #include <linux/psci.h> 28 #include <linux/reset-controller.h> 29 #include <linux/slab.h> 30 31 #include <dt-bindings/clock/renesas-cpg-mssr.h> 32 33 #include "renesas-cpg-mssr.h" 34 #include "clk-div6.h" 35 36 #ifdef DEBUG 37 #define WARN_DEBUG(x) WARN_ON(x) 38 #else 39 #define WARN_DEBUG(x) do { } while (0) 40 #endif 41 42 43 /* 44 * Module Standby and Software Reset register offets. 45 * 46 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 47 * R-Car Gen2, R-Car Gen3, and RZ/G1. 48 * These are NOT valid for R-Car Gen1 and RZ/A1! 49 */ 50 51 /* 52 * Module Stop Status Register offsets 53 */ 54 55 static const u16 mstpsr[] = { 56 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 57 0x9A0, 0x9A4, 0x9A8, 0x9AC, 58 }; 59 60 #define MSTPSR(i) mstpsr[i] 61 62 63 /* 64 * System Module Stop Control Register offsets 65 */ 66 67 static const u16 smstpcr[] = { 68 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 69 0x990, 0x994, 0x998, 0x99C, 70 }; 71 72 #define SMSTPCR(i) smstpcr[i] 73 74 /* 75 * Standby Control Register offsets (RZ/A) 76 * Base address is FRQCR register 77 */ 78 79 static const u16 stbcr[] = { 80 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420, 81 0x424, 0x428, 0x42C, 82 }; 83 84 #define STBCR(i) stbcr[i] 85 86 /* 87 * Software Reset Register offsets 88 */ 89 90 static const u16 srcr[] = { 91 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 92 0x920, 0x924, 0x928, 0x92C, 93 }; 94 95 #define SRCR(i) srcr[i] 96 97 98 /* Realtime Module Stop Control Register offsets */ 99 #define RMSTPCR(i) (smstpcr[i] - 0x20) 100 101 /* Modem Module Stop Control Register offsets (r8a73a4) */ 102 #define MMSTPCR(i) (smstpcr[i] + 0x20) 103 104 /* Software Reset Clearing Register offsets */ 105 #define SRSTCLR(i) (0x940 + (i) * 4) 106 107 108 /** 109 * Clock Pulse Generator / Module Standby and Software Reset Private Data 110 * 111 * @rcdev: Optional reset controller entity 112 * @dev: CPG/MSSR device 113 * @base: CPG/MSSR register block base address 114 * @rmw_lock: protects RMW register accesses 115 * @clks: Array containing all Core and Module Clocks 116 * @num_core_clks: Number of Core Clocks in clks[] 117 * @num_mod_clks: Number of Module Clocks in clks[] 118 * @last_dt_core_clk: ID of the last Core Clock exported to DT 119 * @notifiers: Notifier chain to save/restore clock state for system resume 120 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control 121 * @smstpcr_saved[].val: Saved values of SMSTPCR[] 122 * @stbyctrl: This device has Standby Control Registers 123 */ 124 struct cpg_mssr_priv { 125 #ifdef CONFIG_RESET_CONTROLLER 126 struct reset_controller_dev rcdev; 127 #endif 128 struct device *dev; 129 void __iomem *base; 130 spinlock_t rmw_lock; 131 struct device_node *np; 132 133 struct clk **clks; 134 unsigned int num_core_clks; 135 unsigned int num_mod_clks; 136 unsigned int last_dt_core_clk; 137 bool stbyctrl; 138 139 struct raw_notifier_head notifiers; 140 struct { 141 u32 mask; 142 u32 val; 143 } smstpcr_saved[ARRAY_SIZE(smstpcr)]; 144 }; 145 146 static struct cpg_mssr_priv *cpg_mssr_priv; 147 148 /** 149 * struct mstp_clock - MSTP gating clock 150 * @hw: handle between common and hardware-specific interfaces 151 * @index: MSTP clock number 152 * @priv: CPG/MSSR private data 153 */ 154 struct mstp_clock { 155 struct clk_hw hw; 156 u32 index; 157 struct cpg_mssr_priv *priv; 158 }; 159 160 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) 161 162 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 163 { 164 struct mstp_clock *clock = to_mstp_clock(hw); 165 struct cpg_mssr_priv *priv = clock->priv; 166 unsigned int reg = clock->index / 32; 167 unsigned int bit = clock->index % 32; 168 struct device *dev = priv->dev; 169 u32 bitmask = BIT(bit); 170 unsigned long flags; 171 unsigned int i; 172 u32 value; 173 174 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 175 enable ? "ON" : "OFF"); 176 spin_lock_irqsave(&priv->rmw_lock, flags); 177 178 if (priv->stbyctrl) { 179 value = readb(priv->base + STBCR(reg)); 180 if (enable) 181 value &= ~bitmask; 182 else 183 value |= bitmask; 184 writeb(value, priv->base + STBCR(reg)); 185 186 /* dummy read to ensure write has completed */ 187 readb(priv->base + STBCR(reg)); 188 barrier_data(priv->base + STBCR(reg)); 189 } else { 190 value = readl(priv->base + SMSTPCR(reg)); 191 if (enable) 192 value &= ~bitmask; 193 else 194 value |= bitmask; 195 writel(value, priv->base + SMSTPCR(reg)); 196 } 197 198 spin_unlock_irqrestore(&priv->rmw_lock, flags); 199 200 if (!enable || priv->stbyctrl) 201 return 0; 202 203 for (i = 1000; i > 0; --i) { 204 if (!(readl(priv->base + MSTPSR(reg)) & bitmask)) 205 break; 206 cpu_relax(); 207 } 208 209 if (!i) { 210 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 211 priv->base + SMSTPCR(reg), bit); 212 return -ETIMEDOUT; 213 } 214 215 return 0; 216 } 217 218 static int cpg_mstp_clock_enable(struct clk_hw *hw) 219 { 220 return cpg_mstp_clock_endisable(hw, true); 221 } 222 223 static void cpg_mstp_clock_disable(struct clk_hw *hw) 224 { 225 cpg_mstp_clock_endisable(hw, false); 226 } 227 228 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 229 { 230 struct mstp_clock *clock = to_mstp_clock(hw); 231 struct cpg_mssr_priv *priv = clock->priv; 232 u32 value; 233 234 if (priv->stbyctrl) 235 value = readb(priv->base + STBCR(clock->index / 32)); 236 else 237 value = readl(priv->base + MSTPSR(clock->index / 32)); 238 239 return !(value & BIT(clock->index % 32)); 240 } 241 242 static const struct clk_ops cpg_mstp_clock_ops = { 243 .enable = cpg_mstp_clock_enable, 244 .disable = cpg_mstp_clock_disable, 245 .is_enabled = cpg_mstp_clock_is_enabled, 246 }; 247 248 static 249 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 250 void *data) 251 { 252 unsigned int clkidx = clkspec->args[1]; 253 struct cpg_mssr_priv *priv = data; 254 struct device *dev = priv->dev; 255 unsigned int idx; 256 const char *type; 257 struct clk *clk; 258 int range_check; 259 260 switch (clkspec->args[0]) { 261 case CPG_CORE: 262 type = "core"; 263 if (clkidx > priv->last_dt_core_clk) { 264 dev_err(dev, "Invalid %s clock index %u\n", type, 265 clkidx); 266 return ERR_PTR(-EINVAL); 267 } 268 clk = priv->clks[clkidx]; 269 break; 270 271 case CPG_MOD: 272 type = "module"; 273 if (priv->stbyctrl) { 274 idx = MOD_CLK_PACK_10(clkidx); 275 range_check = 7 - (clkidx % 10); 276 } else { 277 idx = MOD_CLK_PACK(clkidx); 278 range_check = 31 - (clkidx % 100); 279 } 280 if (range_check < 0 || idx >= priv->num_mod_clks) { 281 dev_err(dev, "Invalid %s clock index %u\n", type, 282 clkidx); 283 return ERR_PTR(-EINVAL); 284 } 285 clk = priv->clks[priv->num_core_clks + idx]; 286 break; 287 288 default: 289 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); 290 return ERR_PTR(-EINVAL); 291 } 292 293 if (IS_ERR(clk)) 294 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, 295 PTR_ERR(clk)); 296 else 297 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", 298 clkspec->args[0], clkspec->args[1], clk, 299 clk_get_rate(clk)); 300 return clk; 301 } 302 303 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 304 const struct cpg_mssr_info *info, 305 struct cpg_mssr_priv *priv) 306 { 307 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; 308 struct device *dev = priv->dev; 309 unsigned int id = core->id, div = core->div; 310 const char *parent_name; 311 312 WARN_DEBUG(id >= priv->num_core_clks); 313 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 314 315 if (!core->name) { 316 /* Skip NULLified clock */ 317 return; 318 } 319 320 switch (core->type) { 321 case CLK_TYPE_IN: 322 clk = of_clk_get_by_name(priv->np, core->name); 323 break; 324 325 case CLK_TYPE_FF: 326 case CLK_TYPE_DIV6P1: 327 case CLK_TYPE_DIV6_RO: 328 WARN_DEBUG(core->parent >= priv->num_core_clks); 329 parent = priv->clks[core->parent]; 330 if (IS_ERR(parent)) { 331 clk = parent; 332 goto fail; 333 } 334 335 parent_name = __clk_get_name(parent); 336 337 if (core->type == CLK_TYPE_DIV6_RO) 338 /* Multiply with the DIV6 register value */ 339 div *= (readl(priv->base + core->offset) & 0x3f) + 1; 340 341 if (core->type == CLK_TYPE_DIV6P1) { 342 clk = cpg_div6_register(core->name, 1, &parent_name, 343 priv->base + core->offset, 344 &priv->notifiers); 345 } else { 346 clk = clk_register_fixed_factor(NULL, core->name, 347 parent_name, 0, 348 core->mult, div); 349 } 350 break; 351 352 case CLK_TYPE_FR: 353 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, 354 core->mult); 355 break; 356 357 default: 358 if (info->cpg_clk_register) 359 clk = info->cpg_clk_register(dev, core, info, 360 priv->clks, priv->base, 361 &priv->notifiers); 362 else 363 dev_err(dev, "%s has unsupported core clock type %u\n", 364 core->name, core->type); 365 break; 366 } 367 368 if (IS_ERR_OR_NULL(clk)) 369 goto fail; 370 371 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 372 priv->clks[id] = clk; 373 return; 374 375 fail: 376 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", 377 core->name, PTR_ERR(clk)); 378 } 379 380 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 381 const struct cpg_mssr_info *info, 382 struct cpg_mssr_priv *priv) 383 { 384 struct mstp_clock *clock = NULL; 385 struct device *dev = priv->dev; 386 unsigned int id = mod->id; 387 struct clk_init_data init; 388 struct clk *parent, *clk; 389 const char *parent_name; 390 unsigned int i; 391 392 WARN_DEBUG(id < priv->num_core_clks); 393 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 394 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 395 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 396 397 if (!mod->name) { 398 /* Skip NULLified clock */ 399 return; 400 } 401 402 parent = priv->clks[mod->parent]; 403 if (IS_ERR(parent)) { 404 clk = parent; 405 goto fail; 406 } 407 408 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 409 if (!clock) { 410 clk = ERR_PTR(-ENOMEM); 411 goto fail; 412 } 413 414 init.name = mod->name; 415 init.ops = &cpg_mstp_clock_ops; 416 init.flags = CLK_SET_RATE_PARENT; 417 for (i = 0; i < info->num_crit_mod_clks; i++) 418 if (id == info->crit_mod_clks[i]) { 419 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", 420 mod->name); 421 init.flags |= CLK_IS_CRITICAL; 422 break; 423 } 424 425 parent_name = __clk_get_name(parent); 426 init.parent_names = &parent_name; 427 init.num_parents = 1; 428 429 clock->index = id - priv->num_core_clks; 430 clock->priv = priv; 431 clock->hw.init = &init; 432 433 clk = clk_register(NULL, &clock->hw); 434 if (IS_ERR(clk)) 435 goto fail; 436 437 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 438 priv->clks[id] = clk; 439 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); 440 return; 441 442 fail: 443 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", 444 mod->name, PTR_ERR(clk)); 445 kfree(clock); 446 } 447 448 struct cpg_mssr_clk_domain { 449 struct generic_pm_domain genpd; 450 struct device_node *np; 451 unsigned int num_core_pm_clks; 452 unsigned int core_pm_clks[0]; 453 }; 454 455 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; 456 457 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, 458 struct cpg_mssr_clk_domain *pd) 459 { 460 unsigned int i; 461 462 if (clkspec->np != pd->np || clkspec->args_count != 2) 463 return false; 464 465 switch (clkspec->args[0]) { 466 case CPG_CORE: 467 for (i = 0; i < pd->num_core_pm_clks; i++) 468 if (clkspec->args[1] == pd->core_pm_clks[i]) 469 return true; 470 return false; 471 472 case CPG_MOD: 473 return true; 474 475 default: 476 return false; 477 } 478 } 479 480 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) 481 { 482 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; 483 struct device_node *np = dev->of_node; 484 struct of_phandle_args clkspec; 485 struct clk *clk; 486 int i = 0; 487 int error; 488 489 if (!pd) { 490 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); 491 return -EPROBE_DEFER; 492 } 493 494 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 495 &clkspec)) { 496 if (cpg_mssr_is_pm_clk(&clkspec, pd)) 497 goto found; 498 499 of_node_put(clkspec.np); 500 i++; 501 } 502 503 return 0; 504 505 found: 506 clk = of_clk_get_from_provider(&clkspec); 507 of_node_put(clkspec.np); 508 509 if (IS_ERR(clk)) 510 return PTR_ERR(clk); 511 512 error = pm_clk_create(dev); 513 if (error) { 514 dev_err(dev, "pm_clk_create failed %d\n", error); 515 goto fail_put; 516 } 517 518 error = pm_clk_add_clk(dev, clk); 519 if (error) { 520 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error); 521 goto fail_destroy; 522 } 523 524 return 0; 525 526 fail_destroy: 527 pm_clk_destroy(dev); 528 fail_put: 529 clk_put(clk); 530 return error; 531 } 532 533 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) 534 { 535 if (!pm_clk_no_clocks(dev)) 536 pm_clk_destroy(dev); 537 } 538 539 static int __init cpg_mssr_add_clk_domain(struct device *dev, 540 const unsigned int *core_pm_clks, 541 unsigned int num_core_pm_clks) 542 { 543 struct device_node *np = dev->of_node; 544 struct generic_pm_domain *genpd; 545 struct cpg_mssr_clk_domain *pd; 546 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); 547 548 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); 549 if (!pd) 550 return -ENOMEM; 551 552 pd->np = np; 553 pd->num_core_pm_clks = num_core_pm_clks; 554 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); 555 556 genpd = &pd->genpd; 557 genpd->name = np->name; 558 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; 559 genpd->attach_dev = cpg_mssr_attach_dev; 560 genpd->detach_dev = cpg_mssr_detach_dev; 561 pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 562 cpg_mssr_clk_domain = pd; 563 564 of_genpd_add_provider_simple(np, genpd); 565 return 0; 566 } 567 568 #ifdef CONFIG_RESET_CONTROLLER 569 570 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) 571 572 static int cpg_mssr_reset(struct reset_controller_dev *rcdev, 573 unsigned long id) 574 { 575 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 576 unsigned int reg = id / 32; 577 unsigned int bit = id % 32; 578 u32 bitmask = BIT(bit); 579 unsigned long flags; 580 u32 value; 581 582 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 583 584 /* Reset module */ 585 spin_lock_irqsave(&priv->rmw_lock, flags); 586 value = readl(priv->base + SRCR(reg)); 587 value |= bitmask; 588 writel(value, priv->base + SRCR(reg)); 589 spin_unlock_irqrestore(&priv->rmw_lock, flags); 590 591 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 592 udelay(35); 593 594 /* Release module from reset state */ 595 writel(bitmask, priv->base + SRSTCLR(reg)); 596 597 return 0; 598 } 599 600 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) 601 { 602 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 603 unsigned int reg = id / 32; 604 unsigned int bit = id % 32; 605 u32 bitmask = BIT(bit); 606 unsigned long flags; 607 u32 value; 608 609 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 610 611 spin_lock_irqsave(&priv->rmw_lock, flags); 612 value = readl(priv->base + SRCR(reg)); 613 value |= bitmask; 614 writel(value, priv->base + SRCR(reg)); 615 spin_unlock_irqrestore(&priv->rmw_lock, flags); 616 return 0; 617 } 618 619 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, 620 unsigned long id) 621 { 622 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 623 unsigned int reg = id / 32; 624 unsigned int bit = id % 32; 625 u32 bitmask = BIT(bit); 626 627 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 628 629 writel(bitmask, priv->base + SRSTCLR(reg)); 630 return 0; 631 } 632 633 static int cpg_mssr_status(struct reset_controller_dev *rcdev, 634 unsigned long id) 635 { 636 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 637 unsigned int reg = id / 32; 638 unsigned int bit = id % 32; 639 u32 bitmask = BIT(bit); 640 641 return !!(readl(priv->base + SRCR(reg)) & bitmask); 642 } 643 644 static const struct reset_control_ops cpg_mssr_reset_ops = { 645 .reset = cpg_mssr_reset, 646 .assert = cpg_mssr_assert, 647 .deassert = cpg_mssr_deassert, 648 .status = cpg_mssr_status, 649 }; 650 651 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, 652 const struct of_phandle_args *reset_spec) 653 { 654 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 655 unsigned int unpacked = reset_spec->args[0]; 656 unsigned int idx = MOD_CLK_PACK(unpacked); 657 658 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { 659 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); 660 return -EINVAL; 661 } 662 663 return idx; 664 } 665 666 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 667 { 668 priv->rcdev.ops = &cpg_mssr_reset_ops; 669 priv->rcdev.of_node = priv->dev->of_node; 670 priv->rcdev.of_reset_n_cells = 1; 671 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; 672 priv->rcdev.nr_resets = priv->num_mod_clks; 673 return devm_reset_controller_register(priv->dev, &priv->rcdev); 674 } 675 676 #else /* !CONFIG_RESET_CONTROLLER */ 677 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 678 { 679 return 0; 680 } 681 #endif /* !CONFIG_RESET_CONTROLLER */ 682 683 684 static const struct of_device_id cpg_mssr_match[] = { 685 #ifdef CONFIG_CLK_R7S9210 686 { 687 .compatible = "renesas,r7s9210-cpg-mssr", 688 .data = &r7s9210_cpg_mssr_info, 689 }, 690 #endif 691 #ifdef CONFIG_CLK_R8A7743 692 { 693 .compatible = "renesas,r8a7743-cpg-mssr", 694 .data = &r8a7743_cpg_mssr_info, 695 }, 696 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */ 697 { 698 .compatible = "renesas,r8a7744-cpg-mssr", 699 .data = &r8a7743_cpg_mssr_info, 700 }, 701 #endif 702 #ifdef CONFIG_CLK_R8A7745 703 { 704 .compatible = "renesas,r8a7745-cpg-mssr", 705 .data = &r8a7745_cpg_mssr_info, 706 }, 707 #endif 708 #ifdef CONFIG_CLK_R8A77470 709 { 710 .compatible = "renesas,r8a77470-cpg-mssr", 711 .data = &r8a77470_cpg_mssr_info, 712 }, 713 #endif 714 #ifdef CONFIG_CLK_R8A774A1 715 { 716 .compatible = "renesas,r8a774a1-cpg-mssr", 717 .data = &r8a774a1_cpg_mssr_info, 718 }, 719 #endif 720 #ifdef CONFIG_CLK_R8A774C0 721 { 722 .compatible = "renesas,r8a774c0-cpg-mssr", 723 .data = &r8a774c0_cpg_mssr_info, 724 }, 725 #endif 726 #ifdef CONFIG_CLK_R8A7790 727 { 728 .compatible = "renesas,r8a7790-cpg-mssr", 729 .data = &r8a7790_cpg_mssr_info, 730 }, 731 #endif 732 #ifdef CONFIG_CLK_R8A7791 733 { 734 .compatible = "renesas,r8a7791-cpg-mssr", 735 .data = &r8a7791_cpg_mssr_info, 736 }, 737 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ 738 { 739 .compatible = "renesas,r8a7793-cpg-mssr", 740 .data = &r8a7791_cpg_mssr_info, 741 }, 742 #endif 743 #ifdef CONFIG_CLK_R8A7792 744 { 745 .compatible = "renesas,r8a7792-cpg-mssr", 746 .data = &r8a7792_cpg_mssr_info, 747 }, 748 #endif 749 #ifdef CONFIG_CLK_R8A7794 750 { 751 .compatible = "renesas,r8a7794-cpg-mssr", 752 .data = &r8a7794_cpg_mssr_info, 753 }, 754 #endif 755 #ifdef CONFIG_CLK_R8A7795 756 { 757 .compatible = "renesas,r8a7795-cpg-mssr", 758 .data = &r8a7795_cpg_mssr_info, 759 }, 760 #endif 761 #ifdef CONFIG_CLK_R8A7796 762 { 763 .compatible = "renesas,r8a7796-cpg-mssr", 764 .data = &r8a7796_cpg_mssr_info, 765 }, 766 #endif 767 #ifdef CONFIG_CLK_R8A77965 768 { 769 .compatible = "renesas,r8a77965-cpg-mssr", 770 .data = &r8a77965_cpg_mssr_info, 771 }, 772 #endif 773 #ifdef CONFIG_CLK_R8A77970 774 { 775 .compatible = "renesas,r8a77970-cpg-mssr", 776 .data = &r8a77970_cpg_mssr_info, 777 }, 778 #endif 779 #ifdef CONFIG_CLK_R8A77980 780 { 781 .compatible = "renesas,r8a77980-cpg-mssr", 782 .data = &r8a77980_cpg_mssr_info, 783 }, 784 #endif 785 #ifdef CONFIG_CLK_R8A77990 786 { 787 .compatible = "renesas,r8a77990-cpg-mssr", 788 .data = &r8a77990_cpg_mssr_info, 789 }, 790 #endif 791 #ifdef CONFIG_CLK_R8A77995 792 { 793 .compatible = "renesas,r8a77995-cpg-mssr", 794 .data = &r8a77995_cpg_mssr_info, 795 }, 796 #endif 797 { /* sentinel */ } 798 }; 799 800 static void cpg_mssr_del_clk_provider(void *data) 801 { 802 of_clk_del_provider(data); 803 } 804 805 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 806 static int cpg_mssr_suspend_noirq(struct device *dev) 807 { 808 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 809 unsigned int reg; 810 811 /* This is the best we can do to check for the presence of PSCI */ 812 if (!psci_ops.cpu_suspend) 813 return 0; 814 815 /* Save module registers with bits under our control */ 816 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 817 if (priv->smstpcr_saved[reg].mask) 818 priv->smstpcr_saved[reg].val = 819 readl(priv->base + SMSTPCR(reg)); 820 } 821 822 /* Save core clocks */ 823 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); 824 825 return 0; 826 } 827 828 static int cpg_mssr_resume_noirq(struct device *dev) 829 { 830 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 831 unsigned int reg, i; 832 u32 mask, oldval, newval; 833 834 /* This is the best we can do to check for the presence of PSCI */ 835 if (!psci_ops.cpu_suspend) 836 return 0; 837 838 /* Restore core clocks */ 839 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); 840 841 /* Restore module clocks */ 842 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 843 mask = priv->smstpcr_saved[reg].mask; 844 if (!mask) 845 continue; 846 847 if (priv->stbyctrl) 848 oldval = readb(priv->base + STBCR(reg)); 849 else 850 oldval = readl(priv->base + SMSTPCR(reg)); 851 newval = oldval & ~mask; 852 newval |= priv->smstpcr_saved[reg].val & mask; 853 if (newval == oldval) 854 continue; 855 856 if (priv->stbyctrl) { 857 writeb(newval, priv->base + STBCR(reg)); 858 /* dummy read to ensure write has completed */ 859 readb(priv->base + STBCR(reg)); 860 barrier_data(priv->base + STBCR(reg)); 861 continue; 862 } else 863 writel(newval, priv->base + SMSTPCR(reg)); 864 865 /* Wait until enabled clocks are really enabled */ 866 mask &= ~priv->smstpcr_saved[reg].val; 867 if (!mask) 868 continue; 869 870 for (i = 1000; i > 0; --i) { 871 oldval = readl(priv->base + MSTPSR(reg)); 872 if (!(oldval & mask)) 873 break; 874 cpu_relax(); 875 } 876 877 if (!i) 878 dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n", 879 priv->base + SMSTPCR(reg), oldval & mask); 880 } 881 882 return 0; 883 } 884 885 static const struct dev_pm_ops cpg_mssr_pm = { 886 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq, 887 cpg_mssr_resume_noirq) 888 }; 889 #define DEV_PM_OPS &cpg_mssr_pm 890 #else 891 #define DEV_PM_OPS NULL 892 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 893 894 static int __init cpg_mssr_common_init(struct device *dev, 895 struct device_node *np, 896 const struct cpg_mssr_info *info) 897 { 898 struct cpg_mssr_priv *priv; 899 struct clk **clks = NULL; 900 unsigned int nclks, i; 901 int error; 902 903 if (info->init) { 904 error = info->init(dev); 905 if (error) 906 return error; 907 } 908 909 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 910 if (!priv) 911 return -ENOMEM; 912 913 priv->np = np; 914 priv->dev = dev; 915 spin_lock_init(&priv->rmw_lock); 916 917 priv->base = of_iomap(np, 0); 918 if (!priv->base) { 919 error = -ENOMEM; 920 goto out_err; 921 } 922 923 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 924 clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL); 925 if (!clks) { 926 error = -ENOMEM; 927 goto out_err; 928 } 929 930 cpg_mssr_priv = priv; 931 priv->clks = clks; 932 priv->num_core_clks = info->num_total_core_clks; 933 priv->num_mod_clks = info->num_hw_mod_clks; 934 priv->last_dt_core_clk = info->last_dt_core_clk; 935 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 936 priv->stbyctrl = info->stbyctrl; 937 938 for (i = 0; i < nclks; i++) 939 clks[i] = ERR_PTR(-ENOENT); 940 941 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); 942 if (error) 943 goto out_err; 944 945 return 0; 946 947 out_err: 948 kfree(clks); 949 if (priv->base) 950 iounmap(priv->base); 951 kfree(priv); 952 953 return error; 954 } 955 956 void __init cpg_mssr_early_init(struct device_node *np, 957 const struct cpg_mssr_info *info) 958 { 959 int error; 960 int i; 961 962 error = cpg_mssr_common_init(NULL, np, info); 963 if (error) 964 return; 965 966 for (i = 0; i < info->num_early_core_clks; i++) 967 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, 968 cpg_mssr_priv); 969 970 for (i = 0; i < info->num_early_mod_clks; i++) 971 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, 972 cpg_mssr_priv); 973 974 } 975 976 static int __init cpg_mssr_probe(struct platform_device *pdev) 977 { 978 struct device *dev = &pdev->dev; 979 struct device_node *np = dev->of_node; 980 const struct cpg_mssr_info *info; 981 struct cpg_mssr_priv *priv; 982 unsigned int i; 983 int error; 984 985 info = of_device_get_match_data(dev); 986 987 if (!cpg_mssr_priv) { 988 error = cpg_mssr_common_init(dev, dev->of_node, info); 989 if (error) 990 return error; 991 } 992 993 priv = cpg_mssr_priv; 994 priv->dev = dev; 995 dev_set_drvdata(dev, priv); 996 997 for (i = 0; i < info->num_core_clks; i++) 998 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 999 1000 for (i = 0; i < info->num_mod_clks; i++) 1001 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 1002 1003 error = devm_add_action_or_reset(dev, 1004 cpg_mssr_del_clk_provider, 1005 np); 1006 if (error) 1007 return error; 1008 1009 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, 1010 info->num_core_pm_clks); 1011 if (error) 1012 return error; 1013 1014 /* Reset Controller not supported for Standby Control SoCs */ 1015 if (info->stbyctrl) 1016 return 0; 1017 1018 error = cpg_mssr_reset_controller_register(priv); 1019 if (error) 1020 return error; 1021 1022 return 0; 1023 } 1024 1025 static struct platform_driver cpg_mssr_driver = { 1026 .driver = { 1027 .name = "renesas-cpg-mssr", 1028 .of_match_table = cpg_mssr_match, 1029 .pm = DEV_PM_OPS, 1030 }, 1031 }; 1032 1033 static int __init cpg_mssr_init(void) 1034 { 1035 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); 1036 } 1037 1038 subsys_initcall(cpg_mssr_init); 1039 1040 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks, 1041 unsigned int num_core_clks, 1042 unsigned int first_clk, 1043 unsigned int last_clk) 1044 { 1045 unsigned int i; 1046 1047 for (i = 0; i < num_core_clks; i++) 1048 if (core_clks[i].id >= first_clk && 1049 core_clks[i].id <= last_clk) 1050 core_clks[i].name = NULL; 1051 } 1052 1053 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 1054 unsigned int num_mod_clks, 1055 const unsigned int *clks, unsigned int n) 1056 { 1057 unsigned int i, j; 1058 1059 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1060 if (mod_clks[i].id == clks[j]) { 1061 mod_clks[i].name = NULL; 1062 j++; 1063 } 1064 } 1065 1066 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks, 1067 unsigned int num_mod_clks, 1068 const struct mssr_mod_reparent *clks, 1069 unsigned int n) 1070 { 1071 unsigned int i, j; 1072 1073 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1074 if (mod_clks[i].id == clks[j].clk) { 1075 mod_clks[i].parent = clks[j].parent; 1076 j++; 1077 } 1078 } 1079 1080 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 1081 MODULE_LICENSE("GPL v2"); 1082