1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
4  *
5  * Copyright (C) 2015 Glider bvba
6  *
7  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
8  *
9  * Copyright (C) 2013 Ideas On Board SPRL
10  * Copyright (C) 2015 Renesas Electronics Corp.
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_clock.h>
26 #include <linux/pm_domain.h>
27 #include <linux/psci.h>
28 #include <linux/reset-controller.h>
29 #include <linux/slab.h>
30 
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
35 
36 #ifdef DEBUG
37 #define WARN_DEBUG(x)	WARN_ON(x)
38 #else
39 #define WARN_DEBUG(x)	do { } while (0)
40 #endif
41 
42 
43 /*
44  * Module Standby and Software Reset register offets.
45  *
46  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47  * R-Car Gen2, R-Car Gen3, and RZ/G1.
48  * These are NOT valid for R-Car Gen1 and RZ/A1!
49  */
50 
51 /*
52  * Module Stop Status Register offsets
53  */
54 
55 static const u16 mstpsr[] = {
56 	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
57 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
58 };
59 
60 static const u16 mstpsr_for_v3u[] = {
61 	0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62 	0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
63 };
64 
65 /*
66  * System Module Stop Control Register offsets
67  */
68 
69 static const u16 smstpcr[] = {
70 	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
71 	0x990, 0x994, 0x998, 0x99C,
72 };
73 
74 static const u16 mstpcr_for_v3u[] = {
75 	0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
76 	0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
77 };
78 
79 /*
80  * Standby Control Register offsets (RZ/A)
81  * Base address is FRQCR register
82  */
83 
84 static const u16 stbcr[] = {
85 	0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
86 	0x424, 0x428, 0x42C,
87 };
88 
89 /*
90  * Software Reset Register offsets
91  */
92 
93 static const u16 srcr[] = {
94 	0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
95 	0x920, 0x924, 0x928, 0x92C,
96 };
97 
98 static const u16 srcr_for_v3u[] = {
99 	0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
100 	0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
101 };
102 
103 /* Realtime Module Stop Control Register offsets */
104 #define RMSTPCR(i)	(smstpcr[i] - 0x20)
105 
106 /* Modem Module Stop Control Register offsets (r8a73a4) */
107 #define MMSTPCR(i)	(smstpcr[i] + 0x20)
108 
109 /* Software Reset Clearing Register offsets */
110 
111 static const u16 srstclr[] = {
112 	0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
113 	0x960, 0x964, 0x968, 0x96C,
114 };
115 
116 static const u16 srstclr_for_v3u[] = {
117 	0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
118 	0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
119 };
120 
121 /**
122  * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
123  *                        and Software Reset Private Data
124  *
125  * @rcdev: Optional reset controller entity
126  * @dev: CPG/MSSR device
127  * @base: CPG/MSSR register block base address
128  * @reg_layout: CPG/MSSR register layout
129  * @rmw_lock: protects RMW register accesses
130  * @np: Device node in DT for this CPG/MSSR module
131  * @num_core_clks: Number of Core Clocks in clks[]
132  * @num_mod_clks: Number of Module Clocks in clks[]
133  * @last_dt_core_clk: ID of the last Core Clock exported to DT
134  * @notifiers: Notifier chain to save/restore clock state for system resume
135  * @status_regs: Pointer to status registers array
136  * @control_regs: Pointer to control registers array
137  * @reset_regs: Pointer to reset registers array
138  * @reset_clear_regs:  Pointer to reset clearing registers array
139  * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
140  * @smstpcr_saved[].val: Saved values of SMSTPCR[]
141  * @clks: Array containing all Core and Module Clocks
142  */
143 struct cpg_mssr_priv {
144 #ifdef CONFIG_RESET_CONTROLLER
145 	struct reset_controller_dev rcdev;
146 #endif
147 	struct device *dev;
148 	void __iomem *base;
149 	enum clk_reg_layout reg_layout;
150 	spinlock_t rmw_lock;
151 	struct device_node *np;
152 
153 	unsigned int num_core_clks;
154 	unsigned int num_mod_clks;
155 	unsigned int last_dt_core_clk;
156 
157 	struct raw_notifier_head notifiers;
158 	const u16 *status_regs;
159 	const u16 *control_regs;
160 	const u16 *reset_regs;
161 	const u16 *reset_clear_regs;
162 	struct {
163 		u32 mask;
164 		u32 val;
165 	} smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
166 
167 	struct clk *clks[];
168 };
169 
170 static struct cpg_mssr_priv *cpg_mssr_priv;
171 
172 /**
173  * struct mstp_clock - MSTP gating clock
174  * @hw: handle between common and hardware-specific interfaces
175  * @index: MSTP clock number
176  * @priv: CPG/MSSR private data
177  */
178 struct mstp_clock {
179 	struct clk_hw hw;
180 	u32 index;
181 	struct cpg_mssr_priv *priv;
182 };
183 
184 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
185 
186 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
187 {
188 	struct mstp_clock *clock = to_mstp_clock(hw);
189 	struct cpg_mssr_priv *priv = clock->priv;
190 	unsigned int reg = clock->index / 32;
191 	unsigned int bit = clock->index % 32;
192 	struct device *dev = priv->dev;
193 	u32 bitmask = BIT(bit);
194 	unsigned long flags;
195 	unsigned int i;
196 	u32 value;
197 
198 	dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
199 		enable ? "ON" : "OFF");
200 	spin_lock_irqsave(&priv->rmw_lock, flags);
201 
202 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
203 		value = readb(priv->base + priv->control_regs[reg]);
204 		if (enable)
205 			value &= ~bitmask;
206 		else
207 			value |= bitmask;
208 		writeb(value, priv->base + priv->control_regs[reg]);
209 
210 		/* dummy read to ensure write has completed */
211 		readb(priv->base + priv->control_regs[reg]);
212 		barrier_data(priv->base + priv->control_regs[reg]);
213 	} else {
214 		value = readl(priv->base + priv->control_regs[reg]);
215 		if (enable)
216 			value &= ~bitmask;
217 		else
218 			value |= bitmask;
219 		writel(value, priv->base + priv->control_regs[reg]);
220 	}
221 
222 	spin_unlock_irqrestore(&priv->rmw_lock, flags);
223 
224 	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
225 		return 0;
226 
227 	for (i = 1000; i > 0; --i) {
228 		if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
229 			break;
230 		cpu_relax();
231 	}
232 
233 	if (!i) {
234 		dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
235 			priv->base + priv->control_regs[reg], bit);
236 		return -ETIMEDOUT;
237 	}
238 
239 	return 0;
240 }
241 
242 static int cpg_mstp_clock_enable(struct clk_hw *hw)
243 {
244 	return cpg_mstp_clock_endisable(hw, true);
245 }
246 
247 static void cpg_mstp_clock_disable(struct clk_hw *hw)
248 {
249 	cpg_mstp_clock_endisable(hw, false);
250 }
251 
252 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
253 {
254 	struct mstp_clock *clock = to_mstp_clock(hw);
255 	struct cpg_mssr_priv *priv = clock->priv;
256 	u32 value;
257 
258 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
259 		value = readb(priv->base + priv->control_regs[clock->index / 32]);
260 	else
261 		value = readl(priv->base + priv->status_regs[clock->index / 32]);
262 
263 	return !(value & BIT(clock->index % 32));
264 }
265 
266 static const struct clk_ops cpg_mstp_clock_ops = {
267 	.enable = cpg_mstp_clock_enable,
268 	.disable = cpg_mstp_clock_disable,
269 	.is_enabled = cpg_mstp_clock_is_enabled,
270 };
271 
272 static
273 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
274 					 void *data)
275 {
276 	unsigned int clkidx = clkspec->args[1];
277 	struct cpg_mssr_priv *priv = data;
278 	struct device *dev = priv->dev;
279 	unsigned int idx;
280 	const char *type;
281 	struct clk *clk;
282 	int range_check;
283 
284 	switch (clkspec->args[0]) {
285 	case CPG_CORE:
286 		type = "core";
287 		if (clkidx > priv->last_dt_core_clk) {
288 			dev_err(dev, "Invalid %s clock index %u\n", type,
289 			       clkidx);
290 			return ERR_PTR(-EINVAL);
291 		}
292 		clk = priv->clks[clkidx];
293 		break;
294 
295 	case CPG_MOD:
296 		type = "module";
297 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
298 			idx = MOD_CLK_PACK_10(clkidx);
299 			range_check = 7 - (clkidx % 10);
300 		} else {
301 			idx = MOD_CLK_PACK(clkidx);
302 			range_check = 31 - (clkidx % 100);
303 		}
304 		if (range_check < 0 || idx >= priv->num_mod_clks) {
305 			dev_err(dev, "Invalid %s clock index %u\n", type,
306 				clkidx);
307 			return ERR_PTR(-EINVAL);
308 		}
309 		clk = priv->clks[priv->num_core_clks + idx];
310 		break;
311 
312 	default:
313 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
314 		return ERR_PTR(-EINVAL);
315 	}
316 
317 	if (IS_ERR(clk))
318 		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
319 		       PTR_ERR(clk));
320 	else
321 		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
322 			clkspec->args[0], clkspec->args[1], clk,
323 			clk_get_rate(clk));
324 	return clk;
325 }
326 
327 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
328 					      const struct cpg_mssr_info *info,
329 					      struct cpg_mssr_priv *priv)
330 {
331 	struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
332 	struct device *dev = priv->dev;
333 	unsigned int id = core->id, div = core->div;
334 	const char *parent_name;
335 
336 	WARN_DEBUG(id >= priv->num_core_clks);
337 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
338 
339 	if (!core->name) {
340 		/* Skip NULLified clock */
341 		return;
342 	}
343 
344 	switch (core->type) {
345 	case CLK_TYPE_IN:
346 		clk = of_clk_get_by_name(priv->np, core->name);
347 		break;
348 
349 	case CLK_TYPE_FF:
350 	case CLK_TYPE_DIV6P1:
351 	case CLK_TYPE_DIV6_RO:
352 		WARN_DEBUG(core->parent >= priv->num_core_clks);
353 		parent = priv->clks[core->parent];
354 		if (IS_ERR(parent)) {
355 			clk = parent;
356 			goto fail;
357 		}
358 
359 		parent_name = __clk_get_name(parent);
360 
361 		if (core->type == CLK_TYPE_DIV6_RO)
362 			/* Multiply with the DIV6 register value */
363 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;
364 
365 		if (core->type == CLK_TYPE_DIV6P1) {
366 			clk = cpg_div6_register(core->name, 1, &parent_name,
367 						priv->base + core->offset,
368 						&priv->notifiers);
369 		} else {
370 			clk = clk_register_fixed_factor(NULL, core->name,
371 							parent_name, 0,
372 							core->mult, div);
373 		}
374 		break;
375 
376 	case CLK_TYPE_FR:
377 		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
378 					      core->mult);
379 		break;
380 
381 	default:
382 		if (info->cpg_clk_register)
383 			clk = info->cpg_clk_register(dev, core, info,
384 						     priv->clks, priv->base,
385 						     &priv->notifiers);
386 		else
387 			dev_err(dev, "%s has unsupported core clock type %u\n",
388 				core->name, core->type);
389 		break;
390 	}
391 
392 	if (IS_ERR_OR_NULL(clk))
393 		goto fail;
394 
395 	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
396 	priv->clks[id] = clk;
397 	return;
398 
399 fail:
400 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
401 		core->name, PTR_ERR(clk));
402 }
403 
404 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
405 					     const struct cpg_mssr_info *info,
406 					     struct cpg_mssr_priv *priv)
407 {
408 	struct mstp_clock *clock = NULL;
409 	struct device *dev = priv->dev;
410 	unsigned int id = mod->id;
411 	struct clk_init_data init;
412 	struct clk *parent, *clk;
413 	const char *parent_name;
414 	unsigned int i;
415 
416 	WARN_DEBUG(id < priv->num_core_clks);
417 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
418 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
419 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
420 
421 	if (!mod->name) {
422 		/* Skip NULLified clock */
423 		return;
424 	}
425 
426 	parent = priv->clks[mod->parent];
427 	if (IS_ERR(parent)) {
428 		clk = parent;
429 		goto fail;
430 	}
431 
432 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
433 	if (!clock) {
434 		clk = ERR_PTR(-ENOMEM);
435 		goto fail;
436 	}
437 
438 	init.name = mod->name;
439 	init.ops = &cpg_mstp_clock_ops;
440 	init.flags = CLK_SET_RATE_PARENT;
441 	parent_name = __clk_get_name(parent);
442 	init.parent_names = &parent_name;
443 	init.num_parents = 1;
444 
445 	clock->index = id - priv->num_core_clks;
446 	clock->priv = priv;
447 	clock->hw.init = &init;
448 
449 	for (i = 0; i < info->num_crit_mod_clks; i++)
450 		if (id == info->crit_mod_clks[i] &&
451 		    cpg_mstp_clock_is_enabled(&clock->hw)) {
452 			dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
453 				mod->name);
454 			init.flags |= CLK_IS_CRITICAL;
455 			break;
456 		}
457 
458 	clk = clk_register(NULL, &clock->hw);
459 	if (IS_ERR(clk))
460 		goto fail;
461 
462 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
463 	priv->clks[id] = clk;
464 	priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
465 	return;
466 
467 fail:
468 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
469 		mod->name, PTR_ERR(clk));
470 	kfree(clock);
471 }
472 
473 struct cpg_mssr_clk_domain {
474 	struct generic_pm_domain genpd;
475 	unsigned int num_core_pm_clks;
476 	unsigned int core_pm_clks[];
477 };
478 
479 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
480 
481 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
482 			       struct cpg_mssr_clk_domain *pd)
483 {
484 	unsigned int i;
485 
486 	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
487 		return false;
488 
489 	switch (clkspec->args[0]) {
490 	case CPG_CORE:
491 		for (i = 0; i < pd->num_core_pm_clks; i++)
492 			if (clkspec->args[1] == pd->core_pm_clks[i])
493 				return true;
494 		return false;
495 
496 	case CPG_MOD:
497 		return true;
498 
499 	default:
500 		return false;
501 	}
502 }
503 
504 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
505 {
506 	struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
507 	struct device_node *np = dev->of_node;
508 	struct of_phandle_args clkspec;
509 	struct clk *clk;
510 	int i = 0;
511 	int error;
512 
513 	if (!pd) {
514 		dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
515 		return -EPROBE_DEFER;
516 	}
517 
518 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
519 					   &clkspec)) {
520 		if (cpg_mssr_is_pm_clk(&clkspec, pd))
521 			goto found;
522 
523 		of_node_put(clkspec.np);
524 		i++;
525 	}
526 
527 	return 0;
528 
529 found:
530 	clk = of_clk_get_from_provider(&clkspec);
531 	of_node_put(clkspec.np);
532 
533 	if (IS_ERR(clk))
534 		return PTR_ERR(clk);
535 
536 	error = pm_clk_create(dev);
537 	if (error)
538 		goto fail_put;
539 
540 	error = pm_clk_add_clk(dev, clk);
541 	if (error)
542 		goto fail_destroy;
543 
544 	return 0;
545 
546 fail_destroy:
547 	pm_clk_destroy(dev);
548 fail_put:
549 	clk_put(clk);
550 	return error;
551 }
552 
553 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
554 {
555 	if (!pm_clk_no_clocks(dev))
556 		pm_clk_destroy(dev);
557 }
558 
559 static int __init cpg_mssr_add_clk_domain(struct device *dev,
560 					  const unsigned int *core_pm_clks,
561 					  unsigned int num_core_pm_clks)
562 {
563 	struct device_node *np = dev->of_node;
564 	struct generic_pm_domain *genpd;
565 	struct cpg_mssr_clk_domain *pd;
566 	size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
567 
568 	pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
569 	if (!pd)
570 		return -ENOMEM;
571 
572 	pd->num_core_pm_clks = num_core_pm_clks;
573 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
574 
575 	genpd = &pd->genpd;
576 	genpd->name = np->name;
577 	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
578 		       GENPD_FLAG_ACTIVE_WAKEUP;
579 	genpd->attach_dev = cpg_mssr_attach_dev;
580 	genpd->detach_dev = cpg_mssr_detach_dev;
581 	pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
582 	cpg_mssr_clk_domain = pd;
583 
584 	of_genpd_add_provider_simple(np, genpd);
585 	return 0;
586 }
587 
588 #ifdef CONFIG_RESET_CONTROLLER
589 
590 #define rcdev_to_priv(x)	container_of(x, struct cpg_mssr_priv, rcdev)
591 
592 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
593 			  unsigned long id)
594 {
595 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
596 	unsigned int reg = id / 32;
597 	unsigned int bit = id % 32;
598 	u32 bitmask = BIT(bit);
599 
600 	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
601 
602 	/* Reset module */
603 	writel(bitmask, priv->base + priv->reset_regs[reg]);
604 
605 	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
606 	udelay(35);
607 
608 	/* Release module from reset state */
609 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
610 
611 	return 0;
612 }
613 
614 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
615 {
616 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
617 	unsigned int reg = id / 32;
618 	unsigned int bit = id % 32;
619 	u32 bitmask = BIT(bit);
620 
621 	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
622 
623 	writel(bitmask, priv->base + priv->reset_regs[reg]);
624 	return 0;
625 }
626 
627 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
628 			     unsigned long id)
629 {
630 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
631 	unsigned int reg = id / 32;
632 	unsigned int bit = id % 32;
633 	u32 bitmask = BIT(bit);
634 
635 	dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
636 
637 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
638 	return 0;
639 }
640 
641 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
642 			   unsigned long id)
643 {
644 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
645 	unsigned int reg = id / 32;
646 	unsigned int bit = id % 32;
647 	u32 bitmask = BIT(bit);
648 
649 	return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
650 }
651 
652 static const struct reset_control_ops cpg_mssr_reset_ops = {
653 	.reset = cpg_mssr_reset,
654 	.assert = cpg_mssr_assert,
655 	.deassert = cpg_mssr_deassert,
656 	.status = cpg_mssr_status,
657 };
658 
659 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
660 				const struct of_phandle_args *reset_spec)
661 {
662 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
663 	unsigned int unpacked = reset_spec->args[0];
664 	unsigned int idx = MOD_CLK_PACK(unpacked);
665 
666 	if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
667 		dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
668 		return -EINVAL;
669 	}
670 
671 	return idx;
672 }
673 
674 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
675 {
676 	priv->rcdev.ops = &cpg_mssr_reset_ops;
677 	priv->rcdev.of_node = priv->dev->of_node;
678 	priv->rcdev.of_reset_n_cells = 1;
679 	priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
680 	priv->rcdev.nr_resets = priv->num_mod_clks;
681 	return devm_reset_controller_register(priv->dev, &priv->rcdev);
682 }
683 
684 #else /* !CONFIG_RESET_CONTROLLER */
685 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
686 {
687 	return 0;
688 }
689 #endif /* !CONFIG_RESET_CONTROLLER */
690 
691 
692 static const struct of_device_id cpg_mssr_match[] = {
693 #ifdef CONFIG_CLK_R7S9210
694 	{
695 		.compatible = "renesas,r7s9210-cpg-mssr",
696 		.data = &r7s9210_cpg_mssr_info,
697 	},
698 #endif
699 #ifdef CONFIG_CLK_R8A7742
700 	{
701 		.compatible = "renesas,r8a7742-cpg-mssr",
702 		.data = &r8a7742_cpg_mssr_info,
703 	},
704 #endif
705 #ifdef CONFIG_CLK_R8A7743
706 	{
707 		.compatible = "renesas,r8a7743-cpg-mssr",
708 		.data = &r8a7743_cpg_mssr_info,
709 	},
710 	/* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
711 	{
712 		.compatible = "renesas,r8a7744-cpg-mssr",
713 		.data = &r8a7743_cpg_mssr_info,
714 	},
715 #endif
716 #ifdef CONFIG_CLK_R8A7745
717 	{
718 		.compatible = "renesas,r8a7745-cpg-mssr",
719 		.data = &r8a7745_cpg_mssr_info,
720 	},
721 #endif
722 #ifdef CONFIG_CLK_R8A77470
723 	{
724 		.compatible = "renesas,r8a77470-cpg-mssr",
725 		.data = &r8a77470_cpg_mssr_info,
726 	},
727 #endif
728 #ifdef CONFIG_CLK_R8A774A1
729 	{
730 		.compatible = "renesas,r8a774a1-cpg-mssr",
731 		.data = &r8a774a1_cpg_mssr_info,
732 	},
733 #endif
734 #ifdef CONFIG_CLK_R8A774B1
735 	{
736 		.compatible = "renesas,r8a774b1-cpg-mssr",
737 		.data = &r8a774b1_cpg_mssr_info,
738 	},
739 #endif
740 #ifdef CONFIG_CLK_R8A774C0
741 	{
742 		.compatible = "renesas,r8a774c0-cpg-mssr",
743 		.data = &r8a774c0_cpg_mssr_info,
744 	},
745 #endif
746 #ifdef CONFIG_CLK_R8A774E1
747 	{
748 		.compatible = "renesas,r8a774e1-cpg-mssr",
749 		.data = &r8a774e1_cpg_mssr_info,
750 	},
751 #endif
752 #ifdef CONFIG_CLK_R8A7790
753 	{
754 		.compatible = "renesas,r8a7790-cpg-mssr",
755 		.data = &r8a7790_cpg_mssr_info,
756 	},
757 #endif
758 #ifdef CONFIG_CLK_R8A7791
759 	{
760 		.compatible = "renesas,r8a7791-cpg-mssr",
761 		.data = &r8a7791_cpg_mssr_info,
762 	},
763 	/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
764 	{
765 		.compatible = "renesas,r8a7793-cpg-mssr",
766 		.data = &r8a7791_cpg_mssr_info,
767 	},
768 #endif
769 #ifdef CONFIG_CLK_R8A7792
770 	{
771 		.compatible = "renesas,r8a7792-cpg-mssr",
772 		.data = &r8a7792_cpg_mssr_info,
773 	},
774 #endif
775 #ifdef CONFIG_CLK_R8A7794
776 	{
777 		.compatible = "renesas,r8a7794-cpg-mssr",
778 		.data = &r8a7794_cpg_mssr_info,
779 	},
780 #endif
781 #ifdef CONFIG_CLK_R8A7795
782 	{
783 		.compatible = "renesas,r8a7795-cpg-mssr",
784 		.data = &r8a7795_cpg_mssr_info,
785 	},
786 #endif
787 #ifdef CONFIG_CLK_R8A77960
788 	{
789 		.compatible = "renesas,r8a7796-cpg-mssr",
790 		.data = &r8a7796_cpg_mssr_info,
791 	},
792 #endif
793 #ifdef CONFIG_CLK_R8A77961
794 	{
795 		.compatible = "renesas,r8a77961-cpg-mssr",
796 		.data = &r8a7796_cpg_mssr_info,
797 	},
798 #endif
799 #ifdef CONFIG_CLK_R8A77965
800 	{
801 		.compatible = "renesas,r8a77965-cpg-mssr",
802 		.data = &r8a77965_cpg_mssr_info,
803 	},
804 #endif
805 #ifdef CONFIG_CLK_R8A77970
806 	{
807 		.compatible = "renesas,r8a77970-cpg-mssr",
808 		.data = &r8a77970_cpg_mssr_info,
809 	},
810 #endif
811 #ifdef CONFIG_CLK_R8A77980
812 	{
813 		.compatible = "renesas,r8a77980-cpg-mssr",
814 		.data = &r8a77980_cpg_mssr_info,
815 	},
816 #endif
817 #ifdef CONFIG_CLK_R8A77990
818 	{
819 		.compatible = "renesas,r8a77990-cpg-mssr",
820 		.data = &r8a77990_cpg_mssr_info,
821 	},
822 #endif
823 #ifdef CONFIG_CLK_R8A77995
824 	{
825 		.compatible = "renesas,r8a77995-cpg-mssr",
826 		.data = &r8a77995_cpg_mssr_info,
827 	},
828 #endif
829 #ifdef CONFIG_CLK_R8A779A0
830 	{
831 		.compatible = "renesas,r8a779a0-cpg-mssr",
832 		.data = &r8a779a0_cpg_mssr_info,
833 	},
834 #endif
835 	{ /* sentinel */ }
836 };
837 
838 static void cpg_mssr_del_clk_provider(void *data)
839 {
840 	of_clk_del_provider(data);
841 }
842 
843 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
844 static int cpg_mssr_suspend_noirq(struct device *dev)
845 {
846 	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
847 	unsigned int reg;
848 
849 	/* This is the best we can do to check for the presence of PSCI */
850 	if (!psci_ops.cpu_suspend)
851 		return 0;
852 
853 	/* Save module registers with bits under our control */
854 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
855 		if (priv->smstpcr_saved[reg].mask)
856 			priv->smstpcr_saved[reg].val =
857 				priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
858 				readb(priv->base + priv->control_regs[reg]) :
859 				readl(priv->base + priv->control_regs[reg]);
860 	}
861 
862 	/* Save core clocks */
863 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
864 
865 	return 0;
866 }
867 
868 static int cpg_mssr_resume_noirq(struct device *dev)
869 {
870 	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
871 	unsigned int reg, i;
872 	u32 mask, oldval, newval;
873 
874 	/* This is the best we can do to check for the presence of PSCI */
875 	if (!psci_ops.cpu_suspend)
876 		return 0;
877 
878 	/* Restore core clocks */
879 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
880 
881 	/* Restore module clocks */
882 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
883 		mask = priv->smstpcr_saved[reg].mask;
884 		if (!mask)
885 			continue;
886 
887 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
888 			oldval = readb(priv->base + priv->control_regs[reg]);
889 		else
890 			oldval = readl(priv->base + priv->control_regs[reg]);
891 		newval = oldval & ~mask;
892 		newval |= priv->smstpcr_saved[reg].val & mask;
893 		if (newval == oldval)
894 			continue;
895 
896 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
897 			writeb(newval, priv->base + priv->control_regs[reg]);
898 			/* dummy read to ensure write has completed */
899 			readb(priv->base + priv->control_regs[reg]);
900 			barrier_data(priv->base + priv->control_regs[reg]);
901 			continue;
902 		} else
903 			writel(newval, priv->base + priv->control_regs[reg]);
904 
905 		/* Wait until enabled clocks are really enabled */
906 		mask &= ~priv->smstpcr_saved[reg].val;
907 		if (!mask)
908 			continue;
909 
910 		for (i = 1000; i > 0; --i) {
911 			oldval = readl(priv->base + priv->status_regs[reg]);
912 			if (!(oldval & mask))
913 				break;
914 			cpu_relax();
915 		}
916 
917 		if (!i)
918 			dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
919 				 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
920 				 "STB" : "SMSTP", reg, oldval & mask);
921 	}
922 
923 	return 0;
924 }
925 
926 static const struct dev_pm_ops cpg_mssr_pm = {
927 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
928 				      cpg_mssr_resume_noirq)
929 };
930 #define DEV_PM_OPS	&cpg_mssr_pm
931 #else
932 #define DEV_PM_OPS	NULL
933 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
934 
935 static int __init cpg_mssr_common_init(struct device *dev,
936 				       struct device_node *np,
937 				       const struct cpg_mssr_info *info)
938 {
939 	struct cpg_mssr_priv *priv;
940 	unsigned int nclks, i;
941 	int error;
942 
943 	if (info->init) {
944 		error = info->init(dev);
945 		if (error)
946 			return error;
947 	}
948 
949 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;
950 	priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
951 	if (!priv)
952 		return -ENOMEM;
953 
954 	priv->np = np;
955 	priv->dev = dev;
956 	spin_lock_init(&priv->rmw_lock);
957 
958 	priv->base = of_iomap(np, 0);
959 	if (!priv->base) {
960 		error = -ENOMEM;
961 		goto out_err;
962 	}
963 
964 	cpg_mssr_priv = priv;
965 	priv->num_core_clks = info->num_total_core_clks;
966 	priv->num_mod_clks = info->num_hw_mod_clks;
967 	priv->last_dt_core_clk = info->last_dt_core_clk;
968 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
969 	priv->reg_layout = info->reg_layout;
970 	if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
971 		priv->status_regs = mstpsr;
972 		priv->control_regs = smstpcr;
973 		priv->reset_regs = srcr;
974 		priv->reset_clear_regs = srstclr;
975 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
976 		priv->control_regs = stbcr;
977 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
978 		priv->status_regs = mstpsr_for_v3u;
979 		priv->control_regs = mstpcr_for_v3u;
980 		priv->reset_regs = srcr_for_v3u;
981 		priv->reset_clear_regs = srstclr_for_v3u;
982 	} else {
983 		error = -EINVAL;
984 		goto out_err;
985 	}
986 
987 	for (i = 0; i < nclks; i++)
988 		priv->clks[i] = ERR_PTR(-ENOENT);
989 
990 	error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
991 	if (error)
992 		goto out_err;
993 
994 	return 0;
995 
996 out_err:
997 	if (priv->base)
998 		iounmap(priv->base);
999 	kfree(priv);
1000 
1001 	return error;
1002 }
1003 
1004 void __init cpg_mssr_early_init(struct device_node *np,
1005 				const struct cpg_mssr_info *info)
1006 {
1007 	int error;
1008 	int i;
1009 
1010 	error = cpg_mssr_common_init(NULL, np, info);
1011 	if (error)
1012 		return;
1013 
1014 	for (i = 0; i < info->num_early_core_clks; i++)
1015 		cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
1016 					   cpg_mssr_priv);
1017 
1018 	for (i = 0; i < info->num_early_mod_clks; i++)
1019 		cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
1020 					  cpg_mssr_priv);
1021 
1022 }
1023 
1024 static int __init cpg_mssr_probe(struct platform_device *pdev)
1025 {
1026 	struct device *dev = &pdev->dev;
1027 	struct device_node *np = dev->of_node;
1028 	const struct cpg_mssr_info *info;
1029 	struct cpg_mssr_priv *priv;
1030 	unsigned int i;
1031 	int error;
1032 
1033 	info = of_device_get_match_data(dev);
1034 
1035 	if (!cpg_mssr_priv) {
1036 		error = cpg_mssr_common_init(dev, dev->of_node, info);
1037 		if (error)
1038 			return error;
1039 	}
1040 
1041 	priv = cpg_mssr_priv;
1042 	priv->dev = dev;
1043 	dev_set_drvdata(dev, priv);
1044 
1045 	for (i = 0; i < info->num_core_clks; i++)
1046 		cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
1047 
1048 	for (i = 0; i < info->num_mod_clks; i++)
1049 		cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
1050 
1051 	error = devm_add_action_or_reset(dev,
1052 					 cpg_mssr_del_clk_provider,
1053 					 np);
1054 	if (error)
1055 		return error;
1056 
1057 	error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
1058 					info->num_core_pm_clks);
1059 	if (error)
1060 		return error;
1061 
1062 	/* Reset Controller not supported for Standby Control SoCs */
1063 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1064 		return 0;
1065 
1066 	error = cpg_mssr_reset_controller_register(priv);
1067 	if (error)
1068 		return error;
1069 
1070 	return 0;
1071 }
1072 
1073 static struct platform_driver cpg_mssr_driver = {
1074 	.driver		= {
1075 		.name	= "renesas-cpg-mssr",
1076 		.of_match_table = cpg_mssr_match,
1077 		.pm = DEV_PM_OPS,
1078 	},
1079 };
1080 
1081 static int __init cpg_mssr_init(void)
1082 {
1083 	return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
1084 }
1085 
1086 subsys_initcall(cpg_mssr_init);
1087 
1088 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
1089 				   unsigned int num_core_clks,
1090 				   unsigned int first_clk,
1091 				   unsigned int last_clk)
1092 {
1093 	unsigned int i;
1094 
1095 	for (i = 0; i < num_core_clks; i++)
1096 		if (core_clks[i].id >= first_clk &&
1097 		    core_clks[i].id <= last_clk)
1098 			core_clks[i].name = NULL;
1099 }
1100 
1101 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
1102 			     unsigned int num_mod_clks,
1103 			     const unsigned int *clks, unsigned int n)
1104 {
1105 	unsigned int i, j;
1106 
1107 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1108 		if (mod_clks[i].id == clks[j]) {
1109 			mod_clks[i].name = NULL;
1110 			j++;
1111 		}
1112 }
1113 
1114 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
1115 			      unsigned int num_mod_clks,
1116 			      const struct mssr_mod_reparent *clks,
1117 			      unsigned int n)
1118 {
1119 	unsigned int i, j;
1120 
1121 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1122 		if (mod_clks[i].id == clks[j].clk) {
1123 			mod_clks[i].parent = clks[j].parent;
1124 			j++;
1125 		}
1126 }
1127 
1128 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
1129 MODULE_LICENSE("GPL v2");
1130