1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
4  *
5  * Copyright (C) 2015 Glider bvba
6  *
7  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
8  *
9  * Copyright (C) 2013 Ideas On Board SPRL
10  * Copyright (C) 2015 Renesas Electronics Corp.
11  */
12 
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_clock.h>
26 #include <linux/pm_domain.h>
27 #include <linux/psci.h>
28 #include <linux/reset-controller.h>
29 #include <linux/slab.h>
30 
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
35 
36 #ifdef DEBUG
37 #define WARN_DEBUG(x)	WARN_ON(x)
38 #else
39 #define WARN_DEBUG(x)	do { } while (0)
40 #endif
41 
42 
43 /*
44  * Module Standby and Software Reset register offets.
45  *
46  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47  * R-Car Gen2, R-Car Gen3, and RZ/G1.
48  * These are NOT valid for R-Car Gen1 and RZ/A1!
49  */
50 
51 /*
52  * Module Stop Status Register offsets
53  */
54 
55 static const u16 mstpsr[] = {
56 	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
57 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
58 };
59 
60 static const u16 mstpsr_for_gen4[] = {
61 	0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62 	0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
63 	0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
64 	0x2E60, 0x2E64, 0x2E68, 0x2E6C,
65 };
66 
67 /*
68  * System Module Stop Control Register offsets
69  */
70 
71 static const u16 smstpcr[] = {
72 	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
73 	0x990, 0x994, 0x998, 0x99C,
74 };
75 
76 static const u16 mstpcr_for_gen4[] = {
77 	0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
78 	0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
79 	0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
80 	0x2D60, 0x2D64, 0x2D68, 0x2D6C,
81 };
82 
83 /*
84  * Standby Control Register offsets (RZ/A)
85  * Base address is FRQCR register
86  */
87 
88 static const u16 stbcr[] = {
89 	0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
90 	0x424, 0x428, 0x42C,
91 };
92 
93 /*
94  * Software Reset Register offsets
95  */
96 
97 static const u16 srcr[] = {
98 	0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
99 	0x920, 0x924, 0x928, 0x92C,
100 };
101 
102 static const u16 srcr_for_gen4[] = {
103 	0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
104 	0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
105 	0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
106 	0x2C60, 0x2C64, 0x2C68, 0x2C6C,
107 };
108 
109 /*
110  * Software Reset Clearing Register offsets
111  */
112 
113 static const u16 srstclr[] = {
114 	0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
115 	0x960, 0x964, 0x968, 0x96C,
116 };
117 
118 static const u16 srstclr_for_gen4[] = {
119 	0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
120 	0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
121 	0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
122 	0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC,
123 };
124 
125 /**
126  * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
127  *                        and Software Reset Private Data
128  *
129  * @rcdev: Optional reset controller entity
130  * @dev: CPG/MSSR device
131  * @base: CPG/MSSR register block base address
132  * @reg_layout: CPG/MSSR register layout
133  * @rmw_lock: protects RMW register accesses
134  * @np: Device node in DT for this CPG/MSSR module
135  * @num_core_clks: Number of Core Clocks in clks[]
136  * @num_mod_clks: Number of Module Clocks in clks[]
137  * @last_dt_core_clk: ID of the last Core Clock exported to DT
138  * @notifiers: Notifier chain to save/restore clock state for system resume
139  * @status_regs: Pointer to status registers array
140  * @control_regs: Pointer to control registers array
141  * @reset_regs: Pointer to reset registers array
142  * @reset_clear_regs:  Pointer to reset clearing registers array
143  * @smstpcr_saved: [].mask: Mask of SMSTPCR[] bits under our control
144  *                 [].val: Saved values of SMSTPCR[]
145  * @clks: Array containing all Core and Module Clocks
146  */
147 struct cpg_mssr_priv {
148 #ifdef CONFIG_RESET_CONTROLLER
149 	struct reset_controller_dev rcdev;
150 #endif
151 	struct device *dev;
152 	void __iomem *base;
153 	enum clk_reg_layout reg_layout;
154 	spinlock_t rmw_lock;
155 	struct device_node *np;
156 
157 	unsigned int num_core_clks;
158 	unsigned int num_mod_clks;
159 	unsigned int last_dt_core_clk;
160 
161 	struct raw_notifier_head notifiers;
162 	const u16 *status_regs;
163 	const u16 *control_regs;
164 	const u16 *reset_regs;
165 	const u16 *reset_clear_regs;
166 	struct {
167 		u32 mask;
168 		u32 val;
169 	} smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)];
170 
171 	struct clk *clks[];
172 };
173 
174 static struct cpg_mssr_priv *cpg_mssr_priv;
175 
176 /**
177  * struct mstp_clock - MSTP gating clock
178  * @hw: handle between common and hardware-specific interfaces
179  * @index: MSTP clock number
180  * @priv: CPG/MSSR private data
181  */
182 struct mstp_clock {
183 	struct clk_hw hw;
184 	u32 index;
185 	struct cpg_mssr_priv *priv;
186 };
187 
188 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
189 
190 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
191 {
192 	struct mstp_clock *clock = to_mstp_clock(hw);
193 	struct cpg_mssr_priv *priv = clock->priv;
194 	unsigned int reg = clock->index / 32;
195 	unsigned int bit = clock->index % 32;
196 	struct device *dev = priv->dev;
197 	u32 bitmask = BIT(bit);
198 	unsigned long flags;
199 	unsigned int i;
200 	u32 value;
201 
202 	dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
203 		enable ? "ON" : "OFF");
204 	spin_lock_irqsave(&priv->rmw_lock, flags);
205 
206 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
207 		value = readb(priv->base + priv->control_regs[reg]);
208 		if (enable)
209 			value &= ~bitmask;
210 		else
211 			value |= bitmask;
212 		writeb(value, priv->base + priv->control_regs[reg]);
213 
214 		/* dummy read to ensure write has completed */
215 		readb(priv->base + priv->control_regs[reg]);
216 		barrier_data(priv->base + priv->control_regs[reg]);
217 	} else {
218 		value = readl(priv->base + priv->control_regs[reg]);
219 		if (enable)
220 			value &= ~bitmask;
221 		else
222 			value |= bitmask;
223 		writel(value, priv->base + priv->control_regs[reg]);
224 	}
225 
226 	spin_unlock_irqrestore(&priv->rmw_lock, flags);
227 
228 	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
229 		return 0;
230 
231 	for (i = 1000; i > 0; --i) {
232 		if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
233 			break;
234 		cpu_relax();
235 	}
236 
237 	if (!i) {
238 		dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
239 			priv->base + priv->control_regs[reg], bit);
240 		return -ETIMEDOUT;
241 	}
242 
243 	return 0;
244 }
245 
246 static int cpg_mstp_clock_enable(struct clk_hw *hw)
247 {
248 	return cpg_mstp_clock_endisable(hw, true);
249 }
250 
251 static void cpg_mstp_clock_disable(struct clk_hw *hw)
252 {
253 	cpg_mstp_clock_endisable(hw, false);
254 }
255 
256 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
257 {
258 	struct mstp_clock *clock = to_mstp_clock(hw);
259 	struct cpg_mssr_priv *priv = clock->priv;
260 	u32 value;
261 
262 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
263 		value = readb(priv->base + priv->control_regs[clock->index / 32]);
264 	else
265 		value = readl(priv->base + priv->status_regs[clock->index / 32]);
266 
267 	return !(value & BIT(clock->index % 32));
268 }
269 
270 static const struct clk_ops cpg_mstp_clock_ops = {
271 	.enable = cpg_mstp_clock_enable,
272 	.disable = cpg_mstp_clock_disable,
273 	.is_enabled = cpg_mstp_clock_is_enabled,
274 };
275 
276 static
277 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
278 					 void *data)
279 {
280 	unsigned int clkidx = clkspec->args[1];
281 	struct cpg_mssr_priv *priv = data;
282 	struct device *dev = priv->dev;
283 	unsigned int idx;
284 	const char *type;
285 	struct clk *clk;
286 	int range_check;
287 
288 	switch (clkspec->args[0]) {
289 	case CPG_CORE:
290 		type = "core";
291 		if (clkidx > priv->last_dt_core_clk) {
292 			dev_err(dev, "Invalid %s clock index %u\n", type,
293 			       clkidx);
294 			return ERR_PTR(-EINVAL);
295 		}
296 		clk = priv->clks[clkidx];
297 		break;
298 
299 	case CPG_MOD:
300 		type = "module";
301 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
302 			idx = MOD_CLK_PACK_10(clkidx);
303 			range_check = 7 - (clkidx % 10);
304 		} else {
305 			idx = MOD_CLK_PACK(clkidx);
306 			range_check = 31 - (clkidx % 100);
307 		}
308 		if (range_check < 0 || idx >= priv->num_mod_clks) {
309 			dev_err(dev, "Invalid %s clock index %u\n", type,
310 				clkidx);
311 			return ERR_PTR(-EINVAL);
312 		}
313 		clk = priv->clks[priv->num_core_clks + idx];
314 		break;
315 
316 	default:
317 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
318 		return ERR_PTR(-EINVAL);
319 	}
320 
321 	if (IS_ERR(clk))
322 		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
323 		       PTR_ERR(clk));
324 	else
325 		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
326 			clkspec->args[0], clkspec->args[1], clk,
327 			clk_get_rate(clk));
328 	return clk;
329 }
330 
331 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
332 					      const struct cpg_mssr_info *info,
333 					      struct cpg_mssr_priv *priv)
334 {
335 	struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
336 	struct device *dev = priv->dev;
337 	unsigned int id = core->id, div = core->div;
338 	const char *parent_name;
339 
340 	WARN_DEBUG(id >= priv->num_core_clks);
341 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
342 
343 	if (!core->name) {
344 		/* Skip NULLified clock */
345 		return;
346 	}
347 
348 	switch (core->type) {
349 	case CLK_TYPE_IN:
350 		clk = of_clk_get_by_name(priv->np, core->name);
351 		break;
352 
353 	case CLK_TYPE_FF:
354 	case CLK_TYPE_DIV6P1:
355 	case CLK_TYPE_DIV6_RO:
356 		WARN_DEBUG(core->parent >= priv->num_core_clks);
357 		parent = priv->clks[core->parent];
358 		if (IS_ERR(parent)) {
359 			clk = parent;
360 			goto fail;
361 		}
362 
363 		parent_name = __clk_get_name(parent);
364 
365 		if (core->type == CLK_TYPE_DIV6_RO)
366 			/* Multiply with the DIV6 register value */
367 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;
368 
369 		if (core->type == CLK_TYPE_DIV6P1) {
370 			clk = cpg_div6_register(core->name, 1, &parent_name,
371 						priv->base + core->offset,
372 						&priv->notifiers);
373 		} else {
374 			clk = clk_register_fixed_factor(NULL, core->name,
375 							parent_name, 0,
376 							core->mult, div);
377 		}
378 		break;
379 
380 	case CLK_TYPE_FR:
381 		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
382 					      core->mult);
383 		break;
384 
385 	default:
386 		if (info->cpg_clk_register)
387 			clk = info->cpg_clk_register(dev, core, info,
388 						     priv->clks, priv->base,
389 						     &priv->notifiers);
390 		else
391 			dev_err(dev, "%s has unsupported core clock type %u\n",
392 				core->name, core->type);
393 		break;
394 	}
395 
396 	if (IS_ERR_OR_NULL(clk))
397 		goto fail;
398 
399 	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
400 	priv->clks[id] = clk;
401 	return;
402 
403 fail:
404 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
405 		core->name, PTR_ERR(clk));
406 }
407 
408 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
409 					     const struct cpg_mssr_info *info,
410 					     struct cpg_mssr_priv *priv)
411 {
412 	struct mstp_clock *clock = NULL;
413 	struct device *dev = priv->dev;
414 	unsigned int id = mod->id;
415 	struct clk_init_data init = {};
416 	struct clk *parent, *clk;
417 	const char *parent_name;
418 	unsigned int i;
419 
420 	WARN_DEBUG(id < priv->num_core_clks);
421 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
422 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
423 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
424 
425 	if (!mod->name) {
426 		/* Skip NULLified clock */
427 		return;
428 	}
429 
430 	parent = priv->clks[mod->parent];
431 	if (IS_ERR(parent)) {
432 		clk = parent;
433 		goto fail;
434 	}
435 
436 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
437 	if (!clock) {
438 		clk = ERR_PTR(-ENOMEM);
439 		goto fail;
440 	}
441 
442 	init.name = mod->name;
443 	init.ops = &cpg_mstp_clock_ops;
444 	init.flags = CLK_SET_RATE_PARENT;
445 	parent_name = __clk_get_name(parent);
446 	init.parent_names = &parent_name;
447 	init.num_parents = 1;
448 
449 	clock->index = id - priv->num_core_clks;
450 	clock->priv = priv;
451 	clock->hw.init = &init;
452 
453 	for (i = 0; i < info->num_crit_mod_clks; i++)
454 		if (id == info->crit_mod_clks[i] &&
455 		    cpg_mstp_clock_is_enabled(&clock->hw)) {
456 			dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
457 				mod->name);
458 			init.flags |= CLK_IS_CRITICAL;
459 			break;
460 		}
461 
462 	clk = clk_register(NULL, &clock->hw);
463 	if (IS_ERR(clk))
464 		goto fail;
465 
466 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
467 	priv->clks[id] = clk;
468 	priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
469 	return;
470 
471 fail:
472 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
473 		mod->name, PTR_ERR(clk));
474 	kfree(clock);
475 }
476 
477 struct cpg_mssr_clk_domain {
478 	struct generic_pm_domain genpd;
479 	unsigned int num_core_pm_clks;
480 	unsigned int core_pm_clks[];
481 };
482 
483 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
484 
485 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
486 			       struct cpg_mssr_clk_domain *pd)
487 {
488 	unsigned int i;
489 
490 	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
491 		return false;
492 
493 	switch (clkspec->args[0]) {
494 	case CPG_CORE:
495 		for (i = 0; i < pd->num_core_pm_clks; i++)
496 			if (clkspec->args[1] == pd->core_pm_clks[i])
497 				return true;
498 		return false;
499 
500 	case CPG_MOD:
501 		return true;
502 
503 	default:
504 		return false;
505 	}
506 }
507 
508 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
509 {
510 	struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
511 	struct device_node *np = dev->of_node;
512 	struct of_phandle_args clkspec;
513 	struct clk *clk;
514 	int i = 0;
515 	int error;
516 
517 	if (!pd) {
518 		dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
519 		return -EPROBE_DEFER;
520 	}
521 
522 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
523 					   &clkspec)) {
524 		if (cpg_mssr_is_pm_clk(&clkspec, pd))
525 			goto found;
526 
527 		of_node_put(clkspec.np);
528 		i++;
529 	}
530 
531 	return 0;
532 
533 found:
534 	clk = of_clk_get_from_provider(&clkspec);
535 	of_node_put(clkspec.np);
536 
537 	if (IS_ERR(clk))
538 		return PTR_ERR(clk);
539 
540 	error = pm_clk_create(dev);
541 	if (error)
542 		goto fail_put;
543 
544 	error = pm_clk_add_clk(dev, clk);
545 	if (error)
546 		goto fail_destroy;
547 
548 	return 0;
549 
550 fail_destroy:
551 	pm_clk_destroy(dev);
552 fail_put:
553 	clk_put(clk);
554 	return error;
555 }
556 
557 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
558 {
559 	if (!pm_clk_no_clocks(dev))
560 		pm_clk_destroy(dev);
561 }
562 
563 static void cpg_mssr_genpd_remove(void *data)
564 {
565 	pm_genpd_remove(data);
566 }
567 
568 static int __init cpg_mssr_add_clk_domain(struct device *dev,
569 					  const unsigned int *core_pm_clks,
570 					  unsigned int num_core_pm_clks)
571 {
572 	struct device_node *np = dev->of_node;
573 	struct generic_pm_domain *genpd;
574 	struct cpg_mssr_clk_domain *pd;
575 	size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
576 	int ret;
577 
578 	pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
579 	if (!pd)
580 		return -ENOMEM;
581 
582 	pd->num_core_pm_clks = num_core_pm_clks;
583 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
584 
585 	genpd = &pd->genpd;
586 	genpd->name = np->name;
587 	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
588 		       GENPD_FLAG_ACTIVE_WAKEUP;
589 	genpd->attach_dev = cpg_mssr_attach_dev;
590 	genpd->detach_dev = cpg_mssr_detach_dev;
591 	ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
592 	if (ret)
593 		return ret;
594 
595 	ret = devm_add_action_or_reset(dev, cpg_mssr_genpd_remove, genpd);
596 	if (ret)
597 		return ret;
598 
599 	cpg_mssr_clk_domain = pd;
600 
601 	return of_genpd_add_provider_simple(np, genpd);
602 }
603 
604 #ifdef CONFIG_RESET_CONTROLLER
605 
606 #define rcdev_to_priv(x)	container_of(x, struct cpg_mssr_priv, rcdev)
607 
608 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
609 			  unsigned long id)
610 {
611 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
612 	unsigned int reg = id / 32;
613 	unsigned int bit = id % 32;
614 	u32 bitmask = BIT(bit);
615 
616 	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
617 
618 	/* Reset module */
619 	writel(bitmask, priv->base + priv->reset_regs[reg]);
620 
621 	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
622 	udelay(35);
623 
624 	/* Release module from reset state */
625 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
626 
627 	return 0;
628 }
629 
630 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
631 {
632 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
633 	unsigned int reg = id / 32;
634 	unsigned int bit = id % 32;
635 	u32 bitmask = BIT(bit);
636 
637 	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
638 
639 	writel(bitmask, priv->base + priv->reset_regs[reg]);
640 	return 0;
641 }
642 
643 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
644 			     unsigned long id)
645 {
646 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
647 	unsigned int reg = id / 32;
648 	unsigned int bit = id % 32;
649 	u32 bitmask = BIT(bit);
650 
651 	dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
652 
653 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
654 	return 0;
655 }
656 
657 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
658 			   unsigned long id)
659 {
660 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
661 	unsigned int reg = id / 32;
662 	unsigned int bit = id % 32;
663 	u32 bitmask = BIT(bit);
664 
665 	return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
666 }
667 
668 static const struct reset_control_ops cpg_mssr_reset_ops = {
669 	.reset = cpg_mssr_reset,
670 	.assert = cpg_mssr_assert,
671 	.deassert = cpg_mssr_deassert,
672 	.status = cpg_mssr_status,
673 };
674 
675 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
676 				const struct of_phandle_args *reset_spec)
677 {
678 	struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
679 	unsigned int unpacked = reset_spec->args[0];
680 	unsigned int idx = MOD_CLK_PACK(unpacked);
681 
682 	if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
683 		dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
684 		return -EINVAL;
685 	}
686 
687 	return idx;
688 }
689 
690 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
691 {
692 	priv->rcdev.ops = &cpg_mssr_reset_ops;
693 	priv->rcdev.of_node = priv->dev->of_node;
694 	priv->rcdev.of_reset_n_cells = 1;
695 	priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
696 	priv->rcdev.nr_resets = priv->num_mod_clks;
697 	return devm_reset_controller_register(priv->dev, &priv->rcdev);
698 }
699 
700 #else /* !CONFIG_RESET_CONTROLLER */
701 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
702 {
703 	return 0;
704 }
705 #endif /* !CONFIG_RESET_CONTROLLER */
706 
707 
708 static const struct of_device_id cpg_mssr_match[] = {
709 #ifdef CONFIG_CLK_R7S9210
710 	{
711 		.compatible = "renesas,r7s9210-cpg-mssr",
712 		.data = &r7s9210_cpg_mssr_info,
713 	},
714 #endif
715 #ifdef CONFIG_CLK_R8A7742
716 	{
717 		.compatible = "renesas,r8a7742-cpg-mssr",
718 		.data = &r8a7742_cpg_mssr_info,
719 	},
720 #endif
721 #ifdef CONFIG_CLK_R8A7743
722 	{
723 		.compatible = "renesas,r8a7743-cpg-mssr",
724 		.data = &r8a7743_cpg_mssr_info,
725 	},
726 	/* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
727 	{
728 		.compatible = "renesas,r8a7744-cpg-mssr",
729 		.data = &r8a7743_cpg_mssr_info,
730 	},
731 #endif
732 #ifdef CONFIG_CLK_R8A7745
733 	{
734 		.compatible = "renesas,r8a7745-cpg-mssr",
735 		.data = &r8a7745_cpg_mssr_info,
736 	},
737 #endif
738 #ifdef CONFIG_CLK_R8A77470
739 	{
740 		.compatible = "renesas,r8a77470-cpg-mssr",
741 		.data = &r8a77470_cpg_mssr_info,
742 	},
743 #endif
744 #ifdef CONFIG_CLK_R8A774A1
745 	{
746 		.compatible = "renesas,r8a774a1-cpg-mssr",
747 		.data = &r8a774a1_cpg_mssr_info,
748 	},
749 #endif
750 #ifdef CONFIG_CLK_R8A774B1
751 	{
752 		.compatible = "renesas,r8a774b1-cpg-mssr",
753 		.data = &r8a774b1_cpg_mssr_info,
754 	},
755 #endif
756 #ifdef CONFIG_CLK_R8A774C0
757 	{
758 		.compatible = "renesas,r8a774c0-cpg-mssr",
759 		.data = &r8a774c0_cpg_mssr_info,
760 	},
761 #endif
762 #ifdef CONFIG_CLK_R8A774E1
763 	{
764 		.compatible = "renesas,r8a774e1-cpg-mssr",
765 		.data = &r8a774e1_cpg_mssr_info,
766 	},
767 #endif
768 #ifdef CONFIG_CLK_R8A7790
769 	{
770 		.compatible = "renesas,r8a7790-cpg-mssr",
771 		.data = &r8a7790_cpg_mssr_info,
772 	},
773 #endif
774 #ifdef CONFIG_CLK_R8A7791
775 	{
776 		.compatible = "renesas,r8a7791-cpg-mssr",
777 		.data = &r8a7791_cpg_mssr_info,
778 	},
779 	/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
780 	{
781 		.compatible = "renesas,r8a7793-cpg-mssr",
782 		.data = &r8a7791_cpg_mssr_info,
783 	},
784 #endif
785 #ifdef CONFIG_CLK_R8A7792
786 	{
787 		.compatible = "renesas,r8a7792-cpg-mssr",
788 		.data = &r8a7792_cpg_mssr_info,
789 	},
790 #endif
791 #ifdef CONFIG_CLK_R8A7794
792 	{
793 		.compatible = "renesas,r8a7794-cpg-mssr",
794 		.data = &r8a7794_cpg_mssr_info,
795 	},
796 #endif
797 #ifdef CONFIG_CLK_R8A7795
798 	{
799 		.compatible = "renesas,r8a7795-cpg-mssr",
800 		.data = &r8a7795_cpg_mssr_info,
801 	},
802 #endif
803 #ifdef CONFIG_CLK_R8A77960
804 	{
805 		.compatible = "renesas,r8a7796-cpg-mssr",
806 		.data = &r8a7796_cpg_mssr_info,
807 	},
808 #endif
809 #ifdef CONFIG_CLK_R8A77961
810 	{
811 		.compatible = "renesas,r8a77961-cpg-mssr",
812 		.data = &r8a7796_cpg_mssr_info,
813 	},
814 #endif
815 #ifdef CONFIG_CLK_R8A77965
816 	{
817 		.compatible = "renesas,r8a77965-cpg-mssr",
818 		.data = &r8a77965_cpg_mssr_info,
819 	},
820 #endif
821 #ifdef CONFIG_CLK_R8A77970
822 	{
823 		.compatible = "renesas,r8a77970-cpg-mssr",
824 		.data = &r8a77970_cpg_mssr_info,
825 	},
826 #endif
827 #ifdef CONFIG_CLK_R8A77980
828 	{
829 		.compatible = "renesas,r8a77980-cpg-mssr",
830 		.data = &r8a77980_cpg_mssr_info,
831 	},
832 #endif
833 #ifdef CONFIG_CLK_R8A77990
834 	{
835 		.compatible = "renesas,r8a77990-cpg-mssr",
836 		.data = &r8a77990_cpg_mssr_info,
837 	},
838 #endif
839 #ifdef CONFIG_CLK_R8A77995
840 	{
841 		.compatible = "renesas,r8a77995-cpg-mssr",
842 		.data = &r8a77995_cpg_mssr_info,
843 	},
844 #endif
845 #ifdef CONFIG_CLK_R8A779A0
846 	{
847 		.compatible = "renesas,r8a779a0-cpg-mssr",
848 		.data = &r8a779a0_cpg_mssr_info,
849 	},
850 #endif
851 #ifdef CONFIG_CLK_R8A779F0
852 	{
853 		.compatible = "renesas,r8a779f0-cpg-mssr",
854 		.data = &r8a779f0_cpg_mssr_info,
855 	},
856 #endif
857 #ifdef CONFIG_CLK_R8A779G0
858 	{
859 		.compatible = "renesas,r8a779g0-cpg-mssr",
860 		.data = &r8a779g0_cpg_mssr_info,
861 	},
862 #endif
863 	{ /* sentinel */ }
864 };
865 
866 static void cpg_mssr_del_clk_provider(void *data)
867 {
868 	of_clk_del_provider(data);
869 }
870 
871 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
872 static int cpg_mssr_suspend_noirq(struct device *dev)
873 {
874 	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
875 	unsigned int reg;
876 
877 	/* This is the best we can do to check for the presence of PSCI */
878 	if (!psci_ops.cpu_suspend)
879 		return 0;
880 
881 	/* Save module registers with bits under our control */
882 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
883 		if (priv->smstpcr_saved[reg].mask)
884 			priv->smstpcr_saved[reg].val =
885 				priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
886 				readb(priv->base + priv->control_regs[reg]) :
887 				readl(priv->base + priv->control_regs[reg]);
888 	}
889 
890 	/* Save core clocks */
891 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
892 
893 	return 0;
894 }
895 
896 static int cpg_mssr_resume_noirq(struct device *dev)
897 {
898 	struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
899 	unsigned int reg, i;
900 	u32 mask, oldval, newval;
901 
902 	/* This is the best we can do to check for the presence of PSCI */
903 	if (!psci_ops.cpu_suspend)
904 		return 0;
905 
906 	/* Restore core clocks */
907 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
908 
909 	/* Restore module clocks */
910 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
911 		mask = priv->smstpcr_saved[reg].mask;
912 		if (!mask)
913 			continue;
914 
915 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
916 			oldval = readb(priv->base + priv->control_regs[reg]);
917 		else
918 			oldval = readl(priv->base + priv->control_regs[reg]);
919 		newval = oldval & ~mask;
920 		newval |= priv->smstpcr_saved[reg].val & mask;
921 		if (newval == oldval)
922 			continue;
923 
924 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
925 			writeb(newval, priv->base + priv->control_regs[reg]);
926 			/* dummy read to ensure write has completed */
927 			readb(priv->base + priv->control_regs[reg]);
928 			barrier_data(priv->base + priv->control_regs[reg]);
929 			continue;
930 		} else
931 			writel(newval, priv->base + priv->control_regs[reg]);
932 
933 		/* Wait until enabled clocks are really enabled */
934 		mask &= ~priv->smstpcr_saved[reg].val;
935 		if (!mask)
936 			continue;
937 
938 		for (i = 1000; i > 0; --i) {
939 			oldval = readl(priv->base + priv->status_regs[reg]);
940 			if (!(oldval & mask))
941 				break;
942 			cpu_relax();
943 		}
944 
945 		if (!i)
946 			dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg,
947 				 oldval & mask);
948 	}
949 
950 	return 0;
951 }
952 
953 static const struct dev_pm_ops cpg_mssr_pm = {
954 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
955 				      cpg_mssr_resume_noirq)
956 };
957 #define DEV_PM_OPS	&cpg_mssr_pm
958 #else
959 #define DEV_PM_OPS	NULL
960 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
961 
962 static int __init cpg_mssr_common_init(struct device *dev,
963 				       struct device_node *np,
964 				       const struct cpg_mssr_info *info)
965 {
966 	struct cpg_mssr_priv *priv;
967 	unsigned int nclks, i;
968 	int error;
969 
970 	if (info->init) {
971 		error = info->init(dev);
972 		if (error)
973 			return error;
974 	}
975 
976 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;
977 	priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
978 	if (!priv)
979 		return -ENOMEM;
980 
981 	priv->np = np;
982 	priv->dev = dev;
983 	spin_lock_init(&priv->rmw_lock);
984 
985 	priv->base = of_iomap(np, 0);
986 	if (!priv->base) {
987 		error = -ENOMEM;
988 		goto out_err;
989 	}
990 
991 	priv->num_core_clks = info->num_total_core_clks;
992 	priv->num_mod_clks = info->num_hw_mod_clks;
993 	priv->last_dt_core_clk = info->last_dt_core_clk;
994 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
995 	priv->reg_layout = info->reg_layout;
996 	if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
997 		priv->status_regs = mstpsr;
998 		priv->control_regs = smstpcr;
999 		priv->reset_regs = srcr;
1000 		priv->reset_clear_regs = srstclr;
1001 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
1002 		priv->control_regs = stbcr;
1003 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
1004 		priv->status_regs = mstpsr_for_gen4;
1005 		priv->control_regs = mstpcr_for_gen4;
1006 		priv->reset_regs = srcr_for_gen4;
1007 		priv->reset_clear_regs = srstclr_for_gen4;
1008 	} else {
1009 		error = -EINVAL;
1010 		goto out_err;
1011 	}
1012 
1013 	for (i = 0; i < nclks; i++)
1014 		priv->clks[i] = ERR_PTR(-ENOENT);
1015 
1016 	error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
1017 	if (error)
1018 		goto out_err;
1019 
1020 	cpg_mssr_priv = priv;
1021 
1022 	return 0;
1023 
1024 out_err:
1025 	if (priv->base)
1026 		iounmap(priv->base);
1027 	kfree(priv);
1028 
1029 	return error;
1030 }
1031 
1032 void __init cpg_mssr_early_init(struct device_node *np,
1033 				const struct cpg_mssr_info *info)
1034 {
1035 	int error;
1036 	int i;
1037 
1038 	error = cpg_mssr_common_init(NULL, np, info);
1039 	if (error)
1040 		return;
1041 
1042 	for (i = 0; i < info->num_early_core_clks; i++)
1043 		cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
1044 					   cpg_mssr_priv);
1045 
1046 	for (i = 0; i < info->num_early_mod_clks; i++)
1047 		cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
1048 					  cpg_mssr_priv);
1049 
1050 }
1051 
1052 static int __init cpg_mssr_probe(struct platform_device *pdev)
1053 {
1054 	struct device *dev = &pdev->dev;
1055 	struct device_node *np = dev->of_node;
1056 	const struct cpg_mssr_info *info;
1057 	struct cpg_mssr_priv *priv;
1058 	unsigned int i;
1059 	int error;
1060 
1061 	info = of_device_get_match_data(dev);
1062 
1063 	if (!cpg_mssr_priv) {
1064 		error = cpg_mssr_common_init(dev, dev->of_node, info);
1065 		if (error)
1066 			return error;
1067 	}
1068 
1069 	priv = cpg_mssr_priv;
1070 	priv->dev = dev;
1071 	dev_set_drvdata(dev, priv);
1072 
1073 	for (i = 0; i < info->num_core_clks; i++)
1074 		cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
1075 
1076 	for (i = 0; i < info->num_mod_clks; i++)
1077 		cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
1078 
1079 	error = devm_add_action_or_reset(dev,
1080 					 cpg_mssr_del_clk_provider,
1081 					 np);
1082 	if (error)
1083 		return error;
1084 
1085 	error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
1086 					info->num_core_pm_clks);
1087 	if (error)
1088 		return error;
1089 
1090 	/* Reset Controller not supported for Standby Control SoCs */
1091 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1092 		return 0;
1093 
1094 	error = cpg_mssr_reset_controller_register(priv);
1095 	if (error)
1096 		return error;
1097 
1098 	return 0;
1099 }
1100 
1101 static struct platform_driver cpg_mssr_driver = {
1102 	.driver		= {
1103 		.name	= "renesas-cpg-mssr",
1104 		.of_match_table = cpg_mssr_match,
1105 		.pm = DEV_PM_OPS,
1106 	},
1107 };
1108 
1109 static int __init cpg_mssr_init(void)
1110 {
1111 	return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
1112 }
1113 
1114 subsys_initcall(cpg_mssr_init);
1115 
1116 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
1117 			     unsigned int num_mod_clks,
1118 			     const unsigned int *clks, unsigned int n)
1119 {
1120 	unsigned int i, j;
1121 
1122 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1123 		if (mod_clks[i].id == clks[j]) {
1124 			mod_clks[i].name = NULL;
1125 			j++;
1126 		}
1127 }
1128 
1129 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
1130 MODULE_LICENSE("GPL v2");
1131