1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2015 Glider bvba 6 * 7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 8 * 9 * Copyright (C) 2013 Ideas On Board SPRL 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk/renesas.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/module.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_clock.h> 27 #include <linux/pm_domain.h> 28 #include <linux/psci.h> 29 #include <linux/reset-controller.h> 30 #include <linux/slab.h> 31 32 #include <dt-bindings/clock/renesas-cpg-mssr.h> 33 34 #include "renesas-cpg-mssr.h" 35 #include "clk-div6.h" 36 37 #ifdef DEBUG 38 #define WARN_DEBUG(x) WARN_ON(x) 39 #else 40 #define WARN_DEBUG(x) do { } while (0) 41 #endif 42 43 44 /* 45 * Module Standby and Software Reset register offets. 46 * 47 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 48 * R-Car Gen2, R-Car Gen3, and RZ/G1. 49 * These are NOT valid for R-Car Gen1 and RZ/A1! 50 */ 51 52 /* 53 * Module Stop Status Register offsets 54 */ 55 56 static const u16 mstpsr[] = { 57 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 58 0x9A0, 0x9A4, 0x9A8, 0x9AC, 59 }; 60 61 static const u16 mstpsr_for_gen4[] = { 62 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, 63 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C, 64 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C, 65 0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74, 66 }; 67 68 /* 69 * System Module Stop Control Register offsets 70 */ 71 72 static const u16 smstpcr[] = { 73 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 74 0x990, 0x994, 0x998, 0x99C, 75 }; 76 77 static const u16 mstpcr_for_gen4[] = { 78 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, 79 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C, 80 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C, 81 0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74, 82 }; 83 84 /* 85 * Standby Control Register offsets (RZ/A) 86 * Base address is FRQCR register 87 */ 88 89 static const u16 stbcr[] = { 90 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420, 91 0x424, 0x428, 0x42C, 92 }; 93 94 /* 95 * Software Reset Register offsets 96 */ 97 98 static const u16 srcr[] = { 99 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 100 0x920, 0x924, 0x928, 0x92C, 101 }; 102 103 static const u16 srcr_for_gen4[] = { 104 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, 105 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C, 106 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C, 107 0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74, 108 }; 109 110 /* 111 * Software Reset Clearing Register offsets 112 */ 113 114 static const u16 srstclr[] = { 115 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C, 116 0x960, 0x964, 0x968, 0x96C, 117 }; 118 119 static const u16 srstclr_for_gen4[] = { 120 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, 121 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC, 122 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC, 123 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4, 124 }; 125 126 /** 127 * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby 128 * and Software Reset Private Data 129 * 130 * @rcdev: Optional reset controller entity 131 * @dev: CPG/MSSR device 132 * @base: CPG/MSSR register block base address 133 * @reg_layout: CPG/MSSR register layout 134 * @rmw_lock: protects RMW register accesses 135 * @np: Device node in DT for this CPG/MSSR module 136 * @num_core_clks: Number of Core Clocks in clks[] 137 * @num_mod_clks: Number of Module Clocks in clks[] 138 * @last_dt_core_clk: ID of the last Core Clock exported to DT 139 * @notifiers: Notifier chain to save/restore clock state for system resume 140 * @status_regs: Pointer to status registers array 141 * @control_regs: Pointer to control registers array 142 * @reset_regs: Pointer to reset registers array 143 * @reset_clear_regs: Pointer to reset clearing registers array 144 * @smstpcr_saved: [].mask: Mask of SMSTPCR[] bits under our control 145 * [].val: Saved values of SMSTPCR[] 146 * @clks: Array containing all Core and Module Clocks 147 */ 148 struct cpg_mssr_priv { 149 #ifdef CONFIG_RESET_CONTROLLER 150 struct reset_controller_dev rcdev; 151 #endif 152 struct device *dev; 153 void __iomem *base; 154 enum clk_reg_layout reg_layout; 155 spinlock_t rmw_lock; 156 struct device_node *np; 157 158 unsigned int num_core_clks; 159 unsigned int num_mod_clks; 160 unsigned int last_dt_core_clk; 161 162 struct raw_notifier_head notifiers; 163 const u16 *status_regs; 164 const u16 *control_regs; 165 const u16 *reset_regs; 166 const u16 *reset_clear_regs; 167 struct { 168 u32 mask; 169 u32 val; 170 } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)]; 171 172 struct clk *clks[]; 173 }; 174 175 static struct cpg_mssr_priv *cpg_mssr_priv; 176 177 /** 178 * struct mstp_clock - MSTP gating clock 179 * @hw: handle between common and hardware-specific interfaces 180 * @index: MSTP clock number 181 * @priv: CPG/MSSR private data 182 */ 183 struct mstp_clock { 184 struct clk_hw hw; 185 u32 index; 186 struct cpg_mssr_priv *priv; 187 }; 188 189 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) 190 191 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 192 { 193 struct mstp_clock *clock = to_mstp_clock(hw); 194 struct cpg_mssr_priv *priv = clock->priv; 195 unsigned int reg = clock->index / 32; 196 unsigned int bit = clock->index % 32; 197 struct device *dev = priv->dev; 198 u32 bitmask = BIT(bit); 199 unsigned long flags; 200 u32 value; 201 int error; 202 203 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 204 enable ? "ON" : "OFF"); 205 spin_lock_irqsave(&priv->rmw_lock, flags); 206 207 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 208 value = readb(priv->base + priv->control_regs[reg]); 209 if (enable) 210 value &= ~bitmask; 211 else 212 value |= bitmask; 213 writeb(value, priv->base + priv->control_regs[reg]); 214 215 /* dummy read to ensure write has completed */ 216 readb(priv->base + priv->control_regs[reg]); 217 barrier_data(priv->base + priv->control_regs[reg]); 218 } else { 219 value = readl(priv->base + priv->control_regs[reg]); 220 if (enable) 221 value &= ~bitmask; 222 else 223 value |= bitmask; 224 writel(value, priv->base + priv->control_regs[reg]); 225 } 226 227 spin_unlock_irqrestore(&priv->rmw_lock, flags); 228 229 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 230 return 0; 231 232 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], 233 value, !(value & bitmask), 0, 10); 234 if (error) 235 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 236 priv->base + priv->control_regs[reg], bit); 237 238 return error; 239 } 240 241 static int cpg_mstp_clock_enable(struct clk_hw *hw) 242 { 243 return cpg_mstp_clock_endisable(hw, true); 244 } 245 246 static void cpg_mstp_clock_disable(struct clk_hw *hw) 247 { 248 cpg_mstp_clock_endisable(hw, false); 249 } 250 251 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 252 { 253 struct mstp_clock *clock = to_mstp_clock(hw); 254 struct cpg_mssr_priv *priv = clock->priv; 255 u32 value; 256 257 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 258 value = readb(priv->base + priv->control_regs[clock->index / 32]); 259 else 260 value = readl(priv->base + priv->status_regs[clock->index / 32]); 261 262 return !(value & BIT(clock->index % 32)); 263 } 264 265 static const struct clk_ops cpg_mstp_clock_ops = { 266 .enable = cpg_mstp_clock_enable, 267 .disable = cpg_mstp_clock_disable, 268 .is_enabled = cpg_mstp_clock_is_enabled, 269 }; 270 271 static 272 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 273 void *data) 274 { 275 unsigned int clkidx = clkspec->args[1]; 276 struct cpg_mssr_priv *priv = data; 277 struct device *dev = priv->dev; 278 unsigned int idx; 279 const char *type; 280 struct clk *clk; 281 int range_check; 282 283 switch (clkspec->args[0]) { 284 case CPG_CORE: 285 type = "core"; 286 if (clkidx > priv->last_dt_core_clk) { 287 dev_err(dev, "Invalid %s clock index %u\n", type, 288 clkidx); 289 return ERR_PTR(-EINVAL); 290 } 291 clk = priv->clks[clkidx]; 292 break; 293 294 case CPG_MOD: 295 type = "module"; 296 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 297 idx = MOD_CLK_PACK_10(clkidx); 298 range_check = 7 - (clkidx % 10); 299 } else { 300 idx = MOD_CLK_PACK(clkidx); 301 range_check = 31 - (clkidx % 100); 302 } 303 if (range_check < 0 || idx >= priv->num_mod_clks) { 304 dev_err(dev, "Invalid %s clock index %u\n", type, 305 clkidx); 306 return ERR_PTR(-EINVAL); 307 } 308 clk = priv->clks[priv->num_core_clks + idx]; 309 break; 310 311 default: 312 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); 313 return ERR_PTR(-EINVAL); 314 } 315 316 if (IS_ERR(clk)) 317 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, 318 PTR_ERR(clk)); 319 else 320 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", 321 clkspec->args[0], clkspec->args[1], clk, 322 clk_get_rate(clk)); 323 return clk; 324 } 325 326 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 327 const struct cpg_mssr_info *info, 328 struct cpg_mssr_priv *priv) 329 { 330 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; 331 struct device *dev = priv->dev; 332 unsigned int id = core->id, div = core->div; 333 const char *parent_name; 334 335 WARN_DEBUG(id >= priv->num_core_clks); 336 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 337 338 if (!core->name) { 339 /* Skip NULLified clock */ 340 return; 341 } 342 343 switch (core->type) { 344 case CLK_TYPE_IN: 345 clk = of_clk_get_by_name(priv->np, core->name); 346 break; 347 348 case CLK_TYPE_FF: 349 case CLK_TYPE_DIV6P1: 350 case CLK_TYPE_DIV6_RO: 351 WARN_DEBUG(core->parent >= priv->num_core_clks); 352 parent = priv->clks[core->parent]; 353 if (IS_ERR(parent)) { 354 clk = parent; 355 goto fail; 356 } 357 358 parent_name = __clk_get_name(parent); 359 360 if (core->type == CLK_TYPE_DIV6_RO) 361 /* Multiply with the DIV6 register value */ 362 div *= (readl(priv->base + core->offset) & 0x3f) + 1; 363 364 if (core->type == CLK_TYPE_DIV6P1) { 365 clk = cpg_div6_register(core->name, 1, &parent_name, 366 priv->base + core->offset, 367 &priv->notifiers); 368 } else { 369 clk = clk_register_fixed_factor(NULL, core->name, 370 parent_name, 0, 371 core->mult, div); 372 } 373 break; 374 375 case CLK_TYPE_FR: 376 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, 377 core->mult); 378 break; 379 380 default: 381 if (info->cpg_clk_register) 382 clk = info->cpg_clk_register(dev, core, info, 383 priv->clks, priv->base, 384 &priv->notifiers); 385 else 386 dev_err(dev, "%s has unsupported core clock type %u\n", 387 core->name, core->type); 388 break; 389 } 390 391 if (IS_ERR_OR_NULL(clk)) 392 goto fail; 393 394 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 395 priv->clks[id] = clk; 396 return; 397 398 fail: 399 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", 400 core->name, PTR_ERR(clk)); 401 } 402 403 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 404 const struct cpg_mssr_info *info, 405 struct cpg_mssr_priv *priv) 406 { 407 struct mstp_clock *clock = NULL; 408 struct device *dev = priv->dev; 409 unsigned int id = mod->id; 410 struct clk_init_data init = {}; 411 struct clk *parent, *clk; 412 const char *parent_name; 413 unsigned int i; 414 415 WARN_DEBUG(id < priv->num_core_clks); 416 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 417 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 418 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 419 420 if (!mod->name) { 421 /* Skip NULLified clock */ 422 return; 423 } 424 425 parent = priv->clks[mod->parent]; 426 if (IS_ERR(parent)) { 427 clk = parent; 428 goto fail; 429 } 430 431 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 432 if (!clock) { 433 clk = ERR_PTR(-ENOMEM); 434 goto fail; 435 } 436 437 init.name = mod->name; 438 init.ops = &cpg_mstp_clock_ops; 439 init.flags = CLK_SET_RATE_PARENT; 440 parent_name = __clk_get_name(parent); 441 init.parent_names = &parent_name; 442 init.num_parents = 1; 443 444 clock->index = id - priv->num_core_clks; 445 clock->priv = priv; 446 clock->hw.init = &init; 447 448 for (i = 0; i < info->num_crit_mod_clks; i++) 449 if (id == info->crit_mod_clks[i] && 450 cpg_mstp_clock_is_enabled(&clock->hw)) { 451 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", 452 mod->name); 453 init.flags |= CLK_IS_CRITICAL; 454 break; 455 } 456 457 clk = clk_register(NULL, &clock->hw); 458 if (IS_ERR(clk)) 459 goto fail; 460 461 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 462 priv->clks[id] = clk; 463 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); 464 return; 465 466 fail: 467 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", 468 mod->name, PTR_ERR(clk)); 469 kfree(clock); 470 } 471 472 struct cpg_mssr_clk_domain { 473 struct generic_pm_domain genpd; 474 unsigned int num_core_pm_clks; 475 unsigned int core_pm_clks[]; 476 }; 477 478 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; 479 480 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, 481 struct cpg_mssr_clk_domain *pd) 482 { 483 unsigned int i; 484 485 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) 486 return false; 487 488 switch (clkspec->args[0]) { 489 case CPG_CORE: 490 for (i = 0; i < pd->num_core_pm_clks; i++) 491 if (clkspec->args[1] == pd->core_pm_clks[i]) 492 return true; 493 return false; 494 495 case CPG_MOD: 496 return true; 497 498 default: 499 return false; 500 } 501 } 502 503 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) 504 { 505 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; 506 struct device_node *np = dev->of_node; 507 struct of_phandle_args clkspec; 508 struct clk *clk; 509 int i = 0; 510 int error; 511 512 if (!pd) { 513 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); 514 return -EPROBE_DEFER; 515 } 516 517 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 518 &clkspec)) { 519 if (cpg_mssr_is_pm_clk(&clkspec, pd)) 520 goto found; 521 522 of_node_put(clkspec.np); 523 i++; 524 } 525 526 return 0; 527 528 found: 529 clk = of_clk_get_from_provider(&clkspec); 530 of_node_put(clkspec.np); 531 532 if (IS_ERR(clk)) 533 return PTR_ERR(clk); 534 535 error = pm_clk_create(dev); 536 if (error) 537 goto fail_put; 538 539 error = pm_clk_add_clk(dev, clk); 540 if (error) 541 goto fail_destroy; 542 543 return 0; 544 545 fail_destroy: 546 pm_clk_destroy(dev); 547 fail_put: 548 clk_put(clk); 549 return error; 550 } 551 552 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) 553 { 554 if (!pm_clk_no_clocks(dev)) 555 pm_clk_destroy(dev); 556 } 557 558 static void cpg_mssr_genpd_remove(void *data) 559 { 560 pm_genpd_remove(data); 561 } 562 563 static int __init cpg_mssr_add_clk_domain(struct device *dev, 564 const unsigned int *core_pm_clks, 565 unsigned int num_core_pm_clks) 566 { 567 struct device_node *np = dev->of_node; 568 struct generic_pm_domain *genpd; 569 struct cpg_mssr_clk_domain *pd; 570 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); 571 int ret; 572 573 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); 574 if (!pd) 575 return -ENOMEM; 576 577 pd->num_core_pm_clks = num_core_pm_clks; 578 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); 579 580 genpd = &pd->genpd; 581 genpd->name = np->name; 582 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON | 583 GENPD_FLAG_ACTIVE_WAKEUP; 584 genpd->attach_dev = cpg_mssr_attach_dev; 585 genpd->detach_dev = cpg_mssr_detach_dev; 586 ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 587 if (ret) 588 return ret; 589 590 ret = devm_add_action_or_reset(dev, cpg_mssr_genpd_remove, genpd); 591 if (ret) 592 return ret; 593 594 cpg_mssr_clk_domain = pd; 595 596 return of_genpd_add_provider_simple(np, genpd); 597 } 598 599 #ifdef CONFIG_RESET_CONTROLLER 600 601 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) 602 603 static int cpg_mssr_reset(struct reset_controller_dev *rcdev, 604 unsigned long id) 605 { 606 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 607 unsigned int reg = id / 32; 608 unsigned int bit = id % 32; 609 u32 bitmask = BIT(bit); 610 611 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 612 613 /* Reset module */ 614 writel(bitmask, priv->base + priv->reset_regs[reg]); 615 616 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 617 udelay(35); 618 619 /* Release module from reset state */ 620 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); 621 622 return 0; 623 } 624 625 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) 626 { 627 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 628 unsigned int reg = id / 32; 629 unsigned int bit = id % 32; 630 u32 bitmask = BIT(bit); 631 632 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 633 634 writel(bitmask, priv->base + priv->reset_regs[reg]); 635 return 0; 636 } 637 638 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, 639 unsigned long id) 640 { 641 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 642 unsigned int reg = id / 32; 643 unsigned int bit = id % 32; 644 u32 bitmask = BIT(bit); 645 646 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 647 648 writel(bitmask, priv->base + priv->reset_clear_regs[reg]); 649 return 0; 650 } 651 652 static int cpg_mssr_status(struct reset_controller_dev *rcdev, 653 unsigned long id) 654 { 655 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 656 unsigned int reg = id / 32; 657 unsigned int bit = id % 32; 658 u32 bitmask = BIT(bit); 659 660 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask); 661 } 662 663 static const struct reset_control_ops cpg_mssr_reset_ops = { 664 .reset = cpg_mssr_reset, 665 .assert = cpg_mssr_assert, 666 .deassert = cpg_mssr_deassert, 667 .status = cpg_mssr_status, 668 }; 669 670 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, 671 const struct of_phandle_args *reset_spec) 672 { 673 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 674 unsigned int unpacked = reset_spec->args[0]; 675 unsigned int idx = MOD_CLK_PACK(unpacked); 676 677 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { 678 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); 679 return -EINVAL; 680 } 681 682 return idx; 683 } 684 685 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 686 { 687 priv->rcdev.ops = &cpg_mssr_reset_ops; 688 priv->rcdev.of_node = priv->dev->of_node; 689 priv->rcdev.of_reset_n_cells = 1; 690 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; 691 priv->rcdev.nr_resets = priv->num_mod_clks; 692 return devm_reset_controller_register(priv->dev, &priv->rcdev); 693 } 694 695 #else /* !CONFIG_RESET_CONTROLLER */ 696 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 697 { 698 return 0; 699 } 700 #endif /* !CONFIG_RESET_CONTROLLER */ 701 702 703 static const struct of_device_id cpg_mssr_match[] = { 704 #ifdef CONFIG_CLK_R7S9210 705 { 706 .compatible = "renesas,r7s9210-cpg-mssr", 707 .data = &r7s9210_cpg_mssr_info, 708 }, 709 #endif 710 #ifdef CONFIG_CLK_R8A7742 711 { 712 .compatible = "renesas,r8a7742-cpg-mssr", 713 .data = &r8a7742_cpg_mssr_info, 714 }, 715 #endif 716 #ifdef CONFIG_CLK_R8A7743 717 { 718 .compatible = "renesas,r8a7743-cpg-mssr", 719 .data = &r8a7743_cpg_mssr_info, 720 }, 721 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */ 722 { 723 .compatible = "renesas,r8a7744-cpg-mssr", 724 .data = &r8a7743_cpg_mssr_info, 725 }, 726 #endif 727 #ifdef CONFIG_CLK_R8A7745 728 { 729 .compatible = "renesas,r8a7745-cpg-mssr", 730 .data = &r8a7745_cpg_mssr_info, 731 }, 732 #endif 733 #ifdef CONFIG_CLK_R8A77470 734 { 735 .compatible = "renesas,r8a77470-cpg-mssr", 736 .data = &r8a77470_cpg_mssr_info, 737 }, 738 #endif 739 #ifdef CONFIG_CLK_R8A774A1 740 { 741 .compatible = "renesas,r8a774a1-cpg-mssr", 742 .data = &r8a774a1_cpg_mssr_info, 743 }, 744 #endif 745 #ifdef CONFIG_CLK_R8A774B1 746 { 747 .compatible = "renesas,r8a774b1-cpg-mssr", 748 .data = &r8a774b1_cpg_mssr_info, 749 }, 750 #endif 751 #ifdef CONFIG_CLK_R8A774C0 752 { 753 .compatible = "renesas,r8a774c0-cpg-mssr", 754 .data = &r8a774c0_cpg_mssr_info, 755 }, 756 #endif 757 #ifdef CONFIG_CLK_R8A774E1 758 { 759 .compatible = "renesas,r8a774e1-cpg-mssr", 760 .data = &r8a774e1_cpg_mssr_info, 761 }, 762 #endif 763 #ifdef CONFIG_CLK_R8A7790 764 { 765 .compatible = "renesas,r8a7790-cpg-mssr", 766 .data = &r8a7790_cpg_mssr_info, 767 }, 768 #endif 769 #ifdef CONFIG_CLK_R8A7791 770 { 771 .compatible = "renesas,r8a7791-cpg-mssr", 772 .data = &r8a7791_cpg_mssr_info, 773 }, 774 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ 775 { 776 .compatible = "renesas,r8a7793-cpg-mssr", 777 .data = &r8a7791_cpg_mssr_info, 778 }, 779 #endif 780 #ifdef CONFIG_CLK_R8A7792 781 { 782 .compatible = "renesas,r8a7792-cpg-mssr", 783 .data = &r8a7792_cpg_mssr_info, 784 }, 785 #endif 786 #ifdef CONFIG_CLK_R8A7794 787 { 788 .compatible = "renesas,r8a7794-cpg-mssr", 789 .data = &r8a7794_cpg_mssr_info, 790 }, 791 #endif 792 #ifdef CONFIG_CLK_R8A7795 793 { 794 .compatible = "renesas,r8a7795-cpg-mssr", 795 .data = &r8a7795_cpg_mssr_info, 796 }, 797 #endif 798 #ifdef CONFIG_CLK_R8A77960 799 { 800 .compatible = "renesas,r8a7796-cpg-mssr", 801 .data = &r8a7796_cpg_mssr_info, 802 }, 803 #endif 804 #ifdef CONFIG_CLK_R8A77961 805 { 806 .compatible = "renesas,r8a77961-cpg-mssr", 807 .data = &r8a7796_cpg_mssr_info, 808 }, 809 #endif 810 #ifdef CONFIG_CLK_R8A77965 811 { 812 .compatible = "renesas,r8a77965-cpg-mssr", 813 .data = &r8a77965_cpg_mssr_info, 814 }, 815 #endif 816 #ifdef CONFIG_CLK_R8A77970 817 { 818 .compatible = "renesas,r8a77970-cpg-mssr", 819 .data = &r8a77970_cpg_mssr_info, 820 }, 821 #endif 822 #ifdef CONFIG_CLK_R8A77980 823 { 824 .compatible = "renesas,r8a77980-cpg-mssr", 825 .data = &r8a77980_cpg_mssr_info, 826 }, 827 #endif 828 #ifdef CONFIG_CLK_R8A77990 829 { 830 .compatible = "renesas,r8a77990-cpg-mssr", 831 .data = &r8a77990_cpg_mssr_info, 832 }, 833 #endif 834 #ifdef CONFIG_CLK_R8A77995 835 { 836 .compatible = "renesas,r8a77995-cpg-mssr", 837 .data = &r8a77995_cpg_mssr_info, 838 }, 839 #endif 840 #ifdef CONFIG_CLK_R8A779A0 841 { 842 .compatible = "renesas,r8a779a0-cpg-mssr", 843 .data = &r8a779a0_cpg_mssr_info, 844 }, 845 #endif 846 #ifdef CONFIG_CLK_R8A779F0 847 { 848 .compatible = "renesas,r8a779f0-cpg-mssr", 849 .data = &r8a779f0_cpg_mssr_info, 850 }, 851 #endif 852 #ifdef CONFIG_CLK_R8A779G0 853 { 854 .compatible = "renesas,r8a779g0-cpg-mssr", 855 .data = &r8a779g0_cpg_mssr_info, 856 }, 857 #endif 858 { /* sentinel */ } 859 }; 860 861 static void cpg_mssr_del_clk_provider(void *data) 862 { 863 of_clk_del_provider(data); 864 } 865 866 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 867 static int cpg_mssr_suspend_noirq(struct device *dev) 868 { 869 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 870 unsigned int reg; 871 872 /* This is the best we can do to check for the presence of PSCI */ 873 if (!psci_ops.cpu_suspend) 874 return 0; 875 876 /* Save module registers with bits under our control */ 877 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 878 if (priv->smstpcr_saved[reg].mask) 879 priv->smstpcr_saved[reg].val = 880 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? 881 readb(priv->base + priv->control_regs[reg]) : 882 readl(priv->base + priv->control_regs[reg]); 883 } 884 885 /* Save core clocks */ 886 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); 887 888 return 0; 889 } 890 891 static int cpg_mssr_resume_noirq(struct device *dev) 892 { 893 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 894 unsigned int reg; 895 u32 mask, oldval, newval; 896 int error; 897 898 /* This is the best we can do to check for the presence of PSCI */ 899 if (!psci_ops.cpu_suspend) 900 return 0; 901 902 /* Restore core clocks */ 903 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); 904 905 /* Restore module clocks */ 906 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 907 mask = priv->smstpcr_saved[reg].mask; 908 if (!mask) 909 continue; 910 911 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 912 oldval = readb(priv->base + priv->control_regs[reg]); 913 else 914 oldval = readl(priv->base + priv->control_regs[reg]); 915 newval = oldval & ~mask; 916 newval |= priv->smstpcr_saved[reg].val & mask; 917 if (newval == oldval) 918 continue; 919 920 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 921 writeb(newval, priv->base + priv->control_regs[reg]); 922 /* dummy read to ensure write has completed */ 923 readb(priv->base + priv->control_regs[reg]); 924 barrier_data(priv->base + priv->control_regs[reg]); 925 continue; 926 } else 927 writel(newval, priv->base + priv->control_regs[reg]); 928 929 /* Wait until enabled clocks are really enabled */ 930 mask &= ~priv->smstpcr_saved[reg].val; 931 if (!mask) 932 continue; 933 934 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg], 935 oldval, !(oldval & mask), 0, 10); 936 if (error) 937 dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg, 938 oldval & mask); 939 } 940 941 return 0; 942 } 943 944 static const struct dev_pm_ops cpg_mssr_pm = { 945 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq, 946 cpg_mssr_resume_noirq) 947 }; 948 #define DEV_PM_OPS &cpg_mssr_pm 949 #else 950 #define DEV_PM_OPS NULL 951 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 952 953 static int __init cpg_mssr_common_init(struct device *dev, 954 struct device_node *np, 955 const struct cpg_mssr_info *info) 956 { 957 struct cpg_mssr_priv *priv; 958 unsigned int nclks, i; 959 int error; 960 961 if (info->init) { 962 error = info->init(dev); 963 if (error) 964 return error; 965 } 966 967 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 968 priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL); 969 if (!priv) 970 return -ENOMEM; 971 972 priv->np = np; 973 priv->dev = dev; 974 spin_lock_init(&priv->rmw_lock); 975 976 priv->base = of_iomap(np, 0); 977 if (!priv->base) { 978 error = -ENOMEM; 979 goto out_err; 980 } 981 982 priv->num_core_clks = info->num_total_core_clks; 983 priv->num_mod_clks = info->num_hw_mod_clks; 984 priv->last_dt_core_clk = info->last_dt_core_clk; 985 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 986 priv->reg_layout = info->reg_layout; 987 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) { 988 priv->status_regs = mstpsr; 989 priv->control_regs = smstpcr; 990 priv->reset_regs = srcr; 991 priv->reset_clear_regs = srstclr; 992 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { 993 priv->control_regs = stbcr; 994 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) { 995 priv->status_regs = mstpsr_for_gen4; 996 priv->control_regs = mstpcr_for_gen4; 997 priv->reset_regs = srcr_for_gen4; 998 priv->reset_clear_regs = srstclr_for_gen4; 999 } else { 1000 error = -EINVAL; 1001 goto out_err; 1002 } 1003 1004 for (i = 0; i < nclks; i++) 1005 priv->clks[i] = ERR_PTR(-ENOENT); 1006 1007 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); 1008 if (error) 1009 goto out_err; 1010 1011 cpg_mssr_priv = priv; 1012 1013 return 0; 1014 1015 out_err: 1016 if (priv->base) 1017 iounmap(priv->base); 1018 kfree(priv); 1019 1020 return error; 1021 } 1022 1023 void __init cpg_mssr_early_init(struct device_node *np, 1024 const struct cpg_mssr_info *info) 1025 { 1026 int error; 1027 int i; 1028 1029 error = cpg_mssr_common_init(NULL, np, info); 1030 if (error) 1031 return; 1032 1033 for (i = 0; i < info->num_early_core_clks; i++) 1034 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, 1035 cpg_mssr_priv); 1036 1037 for (i = 0; i < info->num_early_mod_clks; i++) 1038 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, 1039 cpg_mssr_priv); 1040 1041 } 1042 1043 static int __init cpg_mssr_probe(struct platform_device *pdev) 1044 { 1045 struct device *dev = &pdev->dev; 1046 struct device_node *np = dev->of_node; 1047 const struct cpg_mssr_info *info; 1048 struct cpg_mssr_priv *priv; 1049 unsigned int i; 1050 int error; 1051 1052 info = of_device_get_match_data(dev); 1053 1054 if (!cpg_mssr_priv) { 1055 error = cpg_mssr_common_init(dev, dev->of_node, info); 1056 if (error) 1057 return error; 1058 } 1059 1060 priv = cpg_mssr_priv; 1061 priv->dev = dev; 1062 dev_set_drvdata(dev, priv); 1063 1064 for (i = 0; i < info->num_core_clks; i++) 1065 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 1066 1067 for (i = 0; i < info->num_mod_clks; i++) 1068 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 1069 1070 error = devm_add_action_or_reset(dev, 1071 cpg_mssr_del_clk_provider, 1072 np); 1073 if (error) 1074 return error; 1075 1076 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, 1077 info->num_core_pm_clks); 1078 if (error) 1079 return error; 1080 1081 /* Reset Controller not supported for Standby Control SoCs */ 1082 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) 1083 return 0; 1084 1085 error = cpg_mssr_reset_controller_register(priv); 1086 if (error) 1087 return error; 1088 1089 return 0; 1090 } 1091 1092 static struct platform_driver cpg_mssr_driver = { 1093 .driver = { 1094 .name = "renesas-cpg-mssr", 1095 .of_match_table = cpg_mssr_match, 1096 .pm = DEV_PM_OPS, 1097 }, 1098 }; 1099 1100 static int __init cpg_mssr_init(void) 1101 { 1102 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); 1103 } 1104 1105 subsys_initcall(cpg_mssr_init); 1106 1107 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 1108 unsigned int num_mod_clks, 1109 const unsigned int *clks, unsigned int n) 1110 { 1111 unsigned int i, j; 1112 1113 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1114 if (mod_clks[i].id == clks[j]) { 1115 mod_clks[i].name = NULL; 1116 j++; 1117 } 1118 } 1119 1120 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 1121