1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2015 Glider bvba 6 * 7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c 8 * 9 * Copyright (C) 2013 Ideas On Board SPRL 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/clk/renesas.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/init.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/module.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_clock.h> 25 #include <linux/pm_domain.h> 26 #include <linux/psci.h> 27 #include <linux/reset-controller.h> 28 #include <linux/slab.h> 29 30 #include <dt-bindings/clock/renesas-cpg-mssr.h> 31 32 #include "renesas-cpg-mssr.h" 33 #include "clk-div6.h" 34 35 #ifdef DEBUG 36 #define WARN_DEBUG(x) WARN_ON(x) 37 #else 38 #define WARN_DEBUG(x) do { } while (0) 39 #endif 40 41 42 /* 43 * Module Standby and Software Reset register offets. 44 * 45 * If the registers exist, these are valid for SH-Mobile, R-Mobile, 46 * R-Car Gen2, R-Car Gen3, and RZ/G1. 47 * These are NOT valid for R-Car Gen1 and RZ/A1! 48 */ 49 50 /* 51 * Module Stop Status Register offsets 52 */ 53 54 static const u16 mstpsr[] = { 55 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4, 56 0x9A0, 0x9A4, 0x9A8, 0x9AC, 57 }; 58 59 #define MSTPSR(i) mstpsr[i] 60 61 62 /* 63 * System Module Stop Control Register offsets 64 */ 65 66 static const u16 smstpcr[] = { 67 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C, 68 0x990, 0x994, 0x998, 0x99C, 69 }; 70 71 #define SMSTPCR(i) smstpcr[i] 72 73 /* 74 * Standby Control Register offsets (RZ/A) 75 * Base address is FRQCR register 76 */ 77 78 static const u16 stbcr[] = { 79 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420, 80 0x424, 0x428, 0x42C, 81 }; 82 83 #define STBCR(i) stbcr[i] 84 85 /* 86 * Software Reset Register offsets 87 */ 88 89 static const u16 srcr[] = { 90 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC, 91 0x920, 0x924, 0x928, 0x92C, 92 }; 93 94 #define SRCR(i) srcr[i] 95 96 97 /* Realtime Module Stop Control Register offsets */ 98 #define RMSTPCR(i) (smstpcr[i] - 0x20) 99 100 /* Modem Module Stop Control Register offsets (r8a73a4) */ 101 #define MMSTPCR(i) (smstpcr[i] + 0x20) 102 103 /* Software Reset Clearing Register offsets */ 104 #define SRSTCLR(i) (0x940 + (i) * 4) 105 106 107 /** 108 * Clock Pulse Generator / Module Standby and Software Reset Private Data 109 * 110 * @rcdev: Optional reset controller entity 111 * @dev: CPG/MSSR device 112 * @base: CPG/MSSR register block base address 113 * @rmw_lock: protects RMW register accesses 114 * @clks: Array containing all Core and Module Clocks 115 * @num_core_clks: Number of Core Clocks in clks[] 116 * @num_mod_clks: Number of Module Clocks in clks[] 117 * @last_dt_core_clk: ID of the last Core Clock exported to DT 118 * @notifiers: Notifier chain to save/restore clock state for system resume 119 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control 120 * @smstpcr_saved[].val: Saved values of SMSTPCR[] 121 * @stbyctrl: This device has Standby Control Registers 122 */ 123 struct cpg_mssr_priv { 124 #ifdef CONFIG_RESET_CONTROLLER 125 struct reset_controller_dev rcdev; 126 #endif 127 struct device *dev; 128 void __iomem *base; 129 spinlock_t rmw_lock; 130 struct device_node *np; 131 132 struct clk **clks; 133 unsigned int num_core_clks; 134 unsigned int num_mod_clks; 135 unsigned int last_dt_core_clk; 136 bool stbyctrl; 137 138 struct raw_notifier_head notifiers; 139 struct { 140 u32 mask; 141 u32 val; 142 } smstpcr_saved[ARRAY_SIZE(smstpcr)]; 143 }; 144 145 static struct cpg_mssr_priv *cpg_mssr_priv; 146 147 /** 148 * struct mstp_clock - MSTP gating clock 149 * @hw: handle between common and hardware-specific interfaces 150 * @index: MSTP clock number 151 * @priv: CPG/MSSR private data 152 */ 153 struct mstp_clock { 154 struct clk_hw hw; 155 u32 index; 156 struct cpg_mssr_priv *priv; 157 }; 158 159 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw) 160 161 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 162 { 163 struct mstp_clock *clock = to_mstp_clock(hw); 164 struct cpg_mssr_priv *priv = clock->priv; 165 unsigned int reg = clock->index / 32; 166 unsigned int bit = clock->index % 32; 167 struct device *dev = priv->dev; 168 u32 bitmask = BIT(bit); 169 unsigned long flags; 170 unsigned int i; 171 u32 value; 172 173 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, 174 enable ? "ON" : "OFF"); 175 spin_lock_irqsave(&priv->rmw_lock, flags); 176 177 if (priv->stbyctrl) { 178 value = readb(priv->base + STBCR(reg)); 179 if (enable) 180 value &= ~bitmask; 181 else 182 value |= bitmask; 183 writeb(value, priv->base + STBCR(reg)); 184 185 /* dummy read to ensure write has completed */ 186 readb(priv->base + STBCR(reg)); 187 barrier_data(priv->base + STBCR(reg)); 188 } else { 189 value = readl(priv->base + SMSTPCR(reg)); 190 if (enable) 191 value &= ~bitmask; 192 else 193 value |= bitmask; 194 writel(value, priv->base + SMSTPCR(reg)); 195 } 196 197 spin_unlock_irqrestore(&priv->rmw_lock, flags); 198 199 if (!enable || priv->stbyctrl) 200 return 0; 201 202 for (i = 1000; i > 0; --i) { 203 if (!(readl(priv->base + MSTPSR(reg)) & bitmask)) 204 break; 205 cpu_relax(); 206 } 207 208 if (!i) { 209 dev_err(dev, "Failed to enable SMSTP %p[%d]\n", 210 priv->base + SMSTPCR(reg), bit); 211 return -ETIMEDOUT; 212 } 213 214 return 0; 215 } 216 217 static int cpg_mstp_clock_enable(struct clk_hw *hw) 218 { 219 return cpg_mstp_clock_endisable(hw, true); 220 } 221 222 static void cpg_mstp_clock_disable(struct clk_hw *hw) 223 { 224 cpg_mstp_clock_endisable(hw, false); 225 } 226 227 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 228 { 229 struct mstp_clock *clock = to_mstp_clock(hw); 230 struct cpg_mssr_priv *priv = clock->priv; 231 u32 value; 232 233 if (priv->stbyctrl) 234 value = readb(priv->base + STBCR(clock->index / 32)); 235 else 236 value = readl(priv->base + MSTPSR(clock->index / 32)); 237 238 return !(value & BIT(clock->index % 32)); 239 } 240 241 static const struct clk_ops cpg_mstp_clock_ops = { 242 .enable = cpg_mstp_clock_enable, 243 .disable = cpg_mstp_clock_disable, 244 .is_enabled = cpg_mstp_clock_is_enabled, 245 }; 246 247 static 248 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec, 249 void *data) 250 { 251 unsigned int clkidx = clkspec->args[1]; 252 struct cpg_mssr_priv *priv = data; 253 struct device *dev = priv->dev; 254 unsigned int idx; 255 const char *type; 256 struct clk *clk; 257 int range_check; 258 259 switch (clkspec->args[0]) { 260 case CPG_CORE: 261 type = "core"; 262 if (clkidx > priv->last_dt_core_clk) { 263 dev_err(dev, "Invalid %s clock index %u\n", type, 264 clkidx); 265 return ERR_PTR(-EINVAL); 266 } 267 clk = priv->clks[clkidx]; 268 break; 269 270 case CPG_MOD: 271 type = "module"; 272 if (priv->stbyctrl) { 273 idx = MOD_CLK_PACK_10(clkidx); 274 range_check = 7 - (clkidx % 10); 275 } else { 276 idx = MOD_CLK_PACK(clkidx); 277 range_check = 31 - (clkidx % 100); 278 } 279 if (range_check < 0 || idx >= priv->num_mod_clks) { 280 dev_err(dev, "Invalid %s clock index %u\n", type, 281 clkidx); 282 return ERR_PTR(-EINVAL); 283 } 284 clk = priv->clks[priv->num_core_clks + idx]; 285 break; 286 287 default: 288 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]); 289 return ERR_PTR(-EINVAL); 290 } 291 292 if (IS_ERR(clk)) 293 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx, 294 PTR_ERR(clk)); 295 else 296 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n", 297 clkspec->args[0], clkspec->args[1], clk, 298 clk_get_rate(clk)); 299 return clk; 300 } 301 302 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 303 const struct cpg_mssr_info *info, 304 struct cpg_mssr_priv *priv) 305 { 306 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent; 307 struct device *dev = priv->dev; 308 unsigned int id = core->id, div = core->div; 309 const char *parent_name; 310 311 WARN_DEBUG(id >= priv->num_core_clks); 312 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 313 314 if (!core->name) { 315 /* Skip NULLified clock */ 316 return; 317 } 318 319 switch (core->type) { 320 case CLK_TYPE_IN: 321 clk = of_clk_get_by_name(priv->np, core->name); 322 break; 323 324 case CLK_TYPE_FF: 325 case CLK_TYPE_DIV6P1: 326 case CLK_TYPE_DIV6_RO: 327 WARN_DEBUG(core->parent >= priv->num_core_clks); 328 parent = priv->clks[core->parent]; 329 if (IS_ERR(parent)) { 330 clk = parent; 331 goto fail; 332 } 333 334 parent_name = __clk_get_name(parent); 335 336 if (core->type == CLK_TYPE_DIV6_RO) 337 /* Multiply with the DIV6 register value */ 338 div *= (readl(priv->base + core->offset) & 0x3f) + 1; 339 340 if (core->type == CLK_TYPE_DIV6P1) { 341 clk = cpg_div6_register(core->name, 1, &parent_name, 342 priv->base + core->offset, 343 &priv->notifiers); 344 } else { 345 clk = clk_register_fixed_factor(NULL, core->name, 346 parent_name, 0, 347 core->mult, div); 348 } 349 break; 350 351 case CLK_TYPE_FR: 352 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0, 353 core->mult); 354 break; 355 356 default: 357 if (info->cpg_clk_register) 358 clk = info->cpg_clk_register(dev, core, info, 359 priv->clks, priv->base, 360 &priv->notifiers); 361 else 362 dev_err(dev, "%s has unsupported core clock type %u\n", 363 core->name, core->type); 364 break; 365 } 366 367 if (IS_ERR_OR_NULL(clk)) 368 goto fail; 369 370 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 371 priv->clks[id] = clk; 372 return; 373 374 fail: 375 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core", 376 core->name, PTR_ERR(clk)); 377 } 378 379 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 380 const struct cpg_mssr_info *info, 381 struct cpg_mssr_priv *priv) 382 { 383 struct mstp_clock *clock = NULL; 384 struct device *dev = priv->dev; 385 unsigned int id = mod->id; 386 struct clk_init_data init; 387 struct clk *parent, *clk; 388 const char *parent_name; 389 unsigned int i; 390 391 WARN_DEBUG(id < priv->num_core_clks); 392 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks); 393 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 394 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 395 396 if (!mod->name) { 397 /* Skip NULLified clock */ 398 return; 399 } 400 401 parent = priv->clks[mod->parent]; 402 if (IS_ERR(parent)) { 403 clk = parent; 404 goto fail; 405 } 406 407 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 408 if (!clock) { 409 clk = ERR_PTR(-ENOMEM); 410 goto fail; 411 } 412 413 init.name = mod->name; 414 init.ops = &cpg_mstp_clock_ops; 415 init.flags = CLK_SET_RATE_PARENT; 416 for (i = 0; i < info->num_crit_mod_clks; i++) 417 if (id == info->crit_mod_clks[i]) { 418 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n", 419 mod->name); 420 init.flags |= CLK_IS_CRITICAL; 421 break; 422 } 423 424 parent_name = __clk_get_name(parent); 425 init.parent_names = &parent_name; 426 init.num_parents = 1; 427 428 clock->index = id - priv->num_core_clks; 429 clock->priv = priv; 430 clock->hw.init = &init; 431 432 clk = clk_register(NULL, &clock->hw); 433 if (IS_ERR(clk)) 434 goto fail; 435 436 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 437 priv->clks[id] = clk; 438 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); 439 return; 440 441 fail: 442 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module", 443 mod->name, PTR_ERR(clk)); 444 kfree(clock); 445 } 446 447 struct cpg_mssr_clk_domain { 448 struct generic_pm_domain genpd; 449 struct device_node *np; 450 unsigned int num_core_pm_clks; 451 unsigned int core_pm_clks[0]; 452 }; 453 454 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain; 455 456 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec, 457 struct cpg_mssr_clk_domain *pd) 458 { 459 unsigned int i; 460 461 if (clkspec->np != pd->np || clkspec->args_count != 2) 462 return false; 463 464 switch (clkspec->args[0]) { 465 case CPG_CORE: 466 for (i = 0; i < pd->num_core_pm_clks; i++) 467 if (clkspec->args[1] == pd->core_pm_clks[i]) 468 return true; 469 return false; 470 471 case CPG_MOD: 472 return true; 473 474 default: 475 return false; 476 } 477 } 478 479 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev) 480 { 481 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain; 482 struct device_node *np = dev->of_node; 483 struct of_phandle_args clkspec; 484 struct clk *clk; 485 int i = 0; 486 int error; 487 488 if (!pd) { 489 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n"); 490 return -EPROBE_DEFER; 491 } 492 493 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, 494 &clkspec)) { 495 if (cpg_mssr_is_pm_clk(&clkspec, pd)) 496 goto found; 497 498 of_node_put(clkspec.np); 499 i++; 500 } 501 502 return 0; 503 504 found: 505 clk = of_clk_get_from_provider(&clkspec); 506 of_node_put(clkspec.np); 507 508 if (IS_ERR(clk)) 509 return PTR_ERR(clk); 510 511 error = pm_clk_create(dev); 512 if (error) { 513 dev_err(dev, "pm_clk_create failed %d\n", error); 514 goto fail_put; 515 } 516 517 error = pm_clk_add_clk(dev, clk); 518 if (error) { 519 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error); 520 goto fail_destroy; 521 } 522 523 return 0; 524 525 fail_destroy: 526 pm_clk_destroy(dev); 527 fail_put: 528 clk_put(clk); 529 return error; 530 } 531 532 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev) 533 { 534 if (!pm_clk_no_clocks(dev)) 535 pm_clk_destroy(dev); 536 } 537 538 static int __init cpg_mssr_add_clk_domain(struct device *dev, 539 const unsigned int *core_pm_clks, 540 unsigned int num_core_pm_clks) 541 { 542 struct device_node *np = dev->of_node; 543 struct generic_pm_domain *genpd; 544 struct cpg_mssr_clk_domain *pd; 545 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]); 546 547 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL); 548 if (!pd) 549 return -ENOMEM; 550 551 pd->np = np; 552 pd->num_core_pm_clks = num_core_pm_clks; 553 memcpy(pd->core_pm_clks, core_pm_clks, pm_size); 554 555 genpd = &pd->genpd; 556 genpd->name = np->name; 557 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; 558 genpd->attach_dev = cpg_mssr_attach_dev; 559 genpd->detach_dev = cpg_mssr_detach_dev; 560 pm_genpd_init(genpd, &pm_domain_always_on_gov, false); 561 cpg_mssr_clk_domain = pd; 562 563 of_genpd_add_provider_simple(np, genpd); 564 return 0; 565 } 566 567 #ifdef CONFIG_RESET_CONTROLLER 568 569 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev) 570 571 static int cpg_mssr_reset(struct reset_controller_dev *rcdev, 572 unsigned long id) 573 { 574 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 575 unsigned int reg = id / 32; 576 unsigned int bit = id % 32; 577 u32 bitmask = BIT(bit); 578 unsigned long flags; 579 u32 value; 580 581 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); 582 583 /* Reset module */ 584 spin_lock_irqsave(&priv->rmw_lock, flags); 585 value = readl(priv->base + SRCR(reg)); 586 value |= bitmask; 587 writel(value, priv->base + SRCR(reg)); 588 spin_unlock_irqrestore(&priv->rmw_lock, flags); 589 590 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ 591 udelay(35); 592 593 /* Release module from reset state */ 594 writel(bitmask, priv->base + SRSTCLR(reg)); 595 596 return 0; 597 } 598 599 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) 600 { 601 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 602 unsigned int reg = id / 32; 603 unsigned int bit = id % 32; 604 u32 bitmask = BIT(bit); 605 unsigned long flags; 606 u32 value; 607 608 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); 609 610 spin_lock_irqsave(&priv->rmw_lock, flags); 611 value = readl(priv->base + SRCR(reg)); 612 value |= bitmask; 613 writel(value, priv->base + SRCR(reg)); 614 spin_unlock_irqrestore(&priv->rmw_lock, flags); 615 return 0; 616 } 617 618 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev, 619 unsigned long id) 620 { 621 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 622 unsigned int reg = id / 32; 623 unsigned int bit = id % 32; 624 u32 bitmask = BIT(bit); 625 626 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); 627 628 writel(bitmask, priv->base + SRSTCLR(reg)); 629 return 0; 630 } 631 632 static int cpg_mssr_status(struct reset_controller_dev *rcdev, 633 unsigned long id) 634 { 635 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 636 unsigned int reg = id / 32; 637 unsigned int bit = id % 32; 638 u32 bitmask = BIT(bit); 639 640 return !!(readl(priv->base + SRCR(reg)) & bitmask); 641 } 642 643 static const struct reset_control_ops cpg_mssr_reset_ops = { 644 .reset = cpg_mssr_reset, 645 .assert = cpg_mssr_assert, 646 .deassert = cpg_mssr_deassert, 647 .status = cpg_mssr_status, 648 }; 649 650 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev, 651 const struct of_phandle_args *reset_spec) 652 { 653 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev); 654 unsigned int unpacked = reset_spec->args[0]; 655 unsigned int idx = MOD_CLK_PACK(unpacked); 656 657 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) { 658 dev_err(priv->dev, "Invalid reset index %u\n", unpacked); 659 return -EINVAL; 660 } 661 662 return idx; 663 } 664 665 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 666 { 667 priv->rcdev.ops = &cpg_mssr_reset_ops; 668 priv->rcdev.of_node = priv->dev->of_node; 669 priv->rcdev.of_reset_n_cells = 1; 670 priv->rcdev.of_xlate = cpg_mssr_reset_xlate; 671 priv->rcdev.nr_resets = priv->num_mod_clks; 672 return devm_reset_controller_register(priv->dev, &priv->rcdev); 673 } 674 675 #else /* !CONFIG_RESET_CONTROLLER */ 676 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv) 677 { 678 return 0; 679 } 680 #endif /* !CONFIG_RESET_CONTROLLER */ 681 682 683 static const struct of_device_id cpg_mssr_match[] = { 684 #ifdef CONFIG_CLK_R7S9210 685 { 686 .compatible = "renesas,r7s9210-cpg-mssr", 687 .data = &r7s9210_cpg_mssr_info, 688 }, 689 #endif 690 #ifdef CONFIG_CLK_R8A7743 691 { 692 .compatible = "renesas,r8a7743-cpg-mssr", 693 .data = &r8a7743_cpg_mssr_info, 694 }, 695 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */ 696 { 697 .compatible = "renesas,r8a7744-cpg-mssr", 698 .data = &r8a7743_cpg_mssr_info, 699 }, 700 #endif 701 #ifdef CONFIG_CLK_R8A7745 702 { 703 .compatible = "renesas,r8a7745-cpg-mssr", 704 .data = &r8a7745_cpg_mssr_info, 705 }, 706 #endif 707 #ifdef CONFIG_CLK_R8A77470 708 { 709 .compatible = "renesas,r8a77470-cpg-mssr", 710 .data = &r8a77470_cpg_mssr_info, 711 }, 712 #endif 713 #ifdef CONFIG_CLK_R8A774A1 714 { 715 .compatible = "renesas,r8a774a1-cpg-mssr", 716 .data = &r8a774a1_cpg_mssr_info, 717 }, 718 #endif 719 #ifdef CONFIG_CLK_R8A774C0 720 { 721 .compatible = "renesas,r8a774c0-cpg-mssr", 722 .data = &r8a774c0_cpg_mssr_info, 723 }, 724 #endif 725 #ifdef CONFIG_CLK_R8A7790 726 { 727 .compatible = "renesas,r8a7790-cpg-mssr", 728 .data = &r8a7790_cpg_mssr_info, 729 }, 730 #endif 731 #ifdef CONFIG_CLK_R8A7791 732 { 733 .compatible = "renesas,r8a7791-cpg-mssr", 734 .data = &r8a7791_cpg_mssr_info, 735 }, 736 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */ 737 { 738 .compatible = "renesas,r8a7793-cpg-mssr", 739 .data = &r8a7791_cpg_mssr_info, 740 }, 741 #endif 742 #ifdef CONFIG_CLK_R8A7792 743 { 744 .compatible = "renesas,r8a7792-cpg-mssr", 745 .data = &r8a7792_cpg_mssr_info, 746 }, 747 #endif 748 #ifdef CONFIG_CLK_R8A7794 749 { 750 .compatible = "renesas,r8a7794-cpg-mssr", 751 .data = &r8a7794_cpg_mssr_info, 752 }, 753 #endif 754 #ifdef CONFIG_CLK_R8A7795 755 { 756 .compatible = "renesas,r8a7795-cpg-mssr", 757 .data = &r8a7795_cpg_mssr_info, 758 }, 759 #endif 760 #ifdef CONFIG_CLK_R8A7796 761 { 762 .compatible = "renesas,r8a7796-cpg-mssr", 763 .data = &r8a7796_cpg_mssr_info, 764 }, 765 #endif 766 #ifdef CONFIG_CLK_R8A77965 767 { 768 .compatible = "renesas,r8a77965-cpg-mssr", 769 .data = &r8a77965_cpg_mssr_info, 770 }, 771 #endif 772 #ifdef CONFIG_CLK_R8A77970 773 { 774 .compatible = "renesas,r8a77970-cpg-mssr", 775 .data = &r8a77970_cpg_mssr_info, 776 }, 777 #endif 778 #ifdef CONFIG_CLK_R8A77980 779 { 780 .compatible = "renesas,r8a77980-cpg-mssr", 781 .data = &r8a77980_cpg_mssr_info, 782 }, 783 #endif 784 #ifdef CONFIG_CLK_R8A77990 785 { 786 .compatible = "renesas,r8a77990-cpg-mssr", 787 .data = &r8a77990_cpg_mssr_info, 788 }, 789 #endif 790 #ifdef CONFIG_CLK_R8A77995 791 { 792 .compatible = "renesas,r8a77995-cpg-mssr", 793 .data = &r8a77995_cpg_mssr_info, 794 }, 795 #endif 796 { /* sentinel */ } 797 }; 798 799 static void cpg_mssr_del_clk_provider(void *data) 800 { 801 of_clk_del_provider(data); 802 } 803 804 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) 805 static int cpg_mssr_suspend_noirq(struct device *dev) 806 { 807 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 808 unsigned int reg; 809 810 /* This is the best we can do to check for the presence of PSCI */ 811 if (!psci_ops.cpu_suspend) 812 return 0; 813 814 /* Save module registers with bits under our control */ 815 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 816 if (priv->smstpcr_saved[reg].mask) 817 priv->smstpcr_saved[reg].val = 818 readl(priv->base + SMSTPCR(reg)); 819 } 820 821 /* Save core clocks */ 822 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL); 823 824 return 0; 825 } 826 827 static int cpg_mssr_resume_noirq(struct device *dev) 828 { 829 struct cpg_mssr_priv *priv = dev_get_drvdata(dev); 830 unsigned int reg, i; 831 u32 mask, oldval, newval; 832 833 /* This is the best we can do to check for the presence of PSCI */ 834 if (!psci_ops.cpu_suspend) 835 return 0; 836 837 /* Restore core clocks */ 838 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL); 839 840 /* Restore module clocks */ 841 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { 842 mask = priv->smstpcr_saved[reg].mask; 843 if (!mask) 844 continue; 845 846 if (priv->stbyctrl) 847 oldval = readb(priv->base + STBCR(reg)); 848 else 849 oldval = readl(priv->base + SMSTPCR(reg)); 850 newval = oldval & ~mask; 851 newval |= priv->smstpcr_saved[reg].val & mask; 852 if (newval == oldval) 853 continue; 854 855 if (priv->stbyctrl) { 856 writeb(newval, priv->base + STBCR(reg)); 857 /* dummy read to ensure write has completed */ 858 readb(priv->base + STBCR(reg)); 859 barrier_data(priv->base + STBCR(reg)); 860 continue; 861 } else 862 writel(newval, priv->base + SMSTPCR(reg)); 863 864 /* Wait until enabled clocks are really enabled */ 865 mask &= ~priv->smstpcr_saved[reg].val; 866 if (!mask) 867 continue; 868 869 for (i = 1000; i > 0; --i) { 870 oldval = readl(priv->base + MSTPSR(reg)); 871 if (!(oldval & mask)) 872 break; 873 cpu_relax(); 874 } 875 876 if (!i) 877 dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n", 878 priv->base + SMSTPCR(reg), oldval & mask); 879 } 880 881 return 0; 882 } 883 884 static const struct dev_pm_ops cpg_mssr_pm = { 885 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq, 886 cpg_mssr_resume_noirq) 887 }; 888 #define DEV_PM_OPS &cpg_mssr_pm 889 #else 890 #define DEV_PM_OPS NULL 891 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ 892 893 static int __init cpg_mssr_common_init(struct device *dev, 894 struct device_node *np, 895 const struct cpg_mssr_info *info) 896 { 897 struct cpg_mssr_priv *priv; 898 struct clk **clks = NULL; 899 unsigned int nclks, i; 900 int error; 901 902 if (info->init) { 903 error = info->init(dev); 904 if (error) 905 return error; 906 } 907 908 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 909 if (!priv) 910 return -ENOMEM; 911 912 priv->np = np; 913 priv->dev = dev; 914 spin_lock_init(&priv->rmw_lock); 915 916 priv->base = of_iomap(np, 0); 917 if (!priv->base) { 918 error = -ENOMEM; 919 goto out_err; 920 } 921 922 nclks = info->num_total_core_clks + info->num_hw_mod_clks; 923 clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL); 924 if (!clks) { 925 error = -ENOMEM; 926 goto out_err; 927 } 928 929 cpg_mssr_priv = priv; 930 priv->clks = clks; 931 priv->num_core_clks = info->num_total_core_clks; 932 priv->num_mod_clks = info->num_hw_mod_clks; 933 priv->last_dt_core_clk = info->last_dt_core_clk; 934 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers); 935 priv->stbyctrl = info->stbyctrl; 936 937 for (i = 0; i < nclks; i++) 938 clks[i] = ERR_PTR(-ENOENT); 939 940 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv); 941 if (error) 942 goto out_err; 943 944 return 0; 945 946 out_err: 947 kfree(clks); 948 if (priv->base) 949 iounmap(priv->base); 950 kfree(priv); 951 952 return error; 953 } 954 955 void __init cpg_mssr_early_init(struct device_node *np, 956 const struct cpg_mssr_info *info) 957 { 958 int error; 959 int i; 960 961 error = cpg_mssr_common_init(NULL, np, info); 962 if (error) 963 return; 964 965 for (i = 0; i < info->num_early_core_clks; i++) 966 cpg_mssr_register_core_clk(&info->early_core_clks[i], info, 967 cpg_mssr_priv); 968 969 for (i = 0; i < info->num_early_mod_clks; i++) 970 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info, 971 cpg_mssr_priv); 972 973 } 974 975 static int __init cpg_mssr_probe(struct platform_device *pdev) 976 { 977 struct device *dev = &pdev->dev; 978 struct device_node *np = dev->of_node; 979 const struct cpg_mssr_info *info; 980 struct cpg_mssr_priv *priv; 981 unsigned int i; 982 int error; 983 984 info = of_device_get_match_data(dev); 985 986 if (!cpg_mssr_priv) { 987 error = cpg_mssr_common_init(dev, dev->of_node, info); 988 if (error) 989 return error; 990 } 991 992 priv = cpg_mssr_priv; 993 priv->dev = dev; 994 dev_set_drvdata(dev, priv); 995 996 for (i = 0; i < info->num_core_clks; i++) 997 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv); 998 999 for (i = 0; i < info->num_mod_clks; i++) 1000 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv); 1001 1002 error = devm_add_action_or_reset(dev, 1003 cpg_mssr_del_clk_provider, 1004 np); 1005 if (error) 1006 return error; 1007 1008 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks, 1009 info->num_core_pm_clks); 1010 if (error) 1011 return error; 1012 1013 /* Reset Controller not supported for Standby Control SoCs */ 1014 if (info->stbyctrl) 1015 return 0; 1016 1017 error = cpg_mssr_reset_controller_register(priv); 1018 if (error) 1019 return error; 1020 1021 return 0; 1022 } 1023 1024 static struct platform_driver cpg_mssr_driver = { 1025 .driver = { 1026 .name = "renesas-cpg-mssr", 1027 .of_match_table = cpg_mssr_match, 1028 .pm = DEV_PM_OPS, 1029 }, 1030 }; 1031 1032 static int __init cpg_mssr_init(void) 1033 { 1034 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe); 1035 } 1036 1037 subsys_initcall(cpg_mssr_init); 1038 1039 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks, 1040 unsigned int num_core_clks, 1041 unsigned int first_clk, 1042 unsigned int last_clk) 1043 { 1044 unsigned int i; 1045 1046 for (i = 0; i < num_core_clks; i++) 1047 if (core_clks[i].id >= first_clk && 1048 core_clks[i].id <= last_clk) 1049 core_clks[i].name = NULL; 1050 } 1051 1052 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, 1053 unsigned int num_mod_clks, 1054 const unsigned int *clks, unsigned int n) 1055 { 1056 unsigned int i, j; 1057 1058 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1059 if (mod_clks[i].id == clks[j]) { 1060 mod_clks[i].name = NULL; 1061 j++; 1062 } 1063 } 1064 1065 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks, 1066 unsigned int num_mod_clks, 1067 const struct mssr_mod_reparent *clks, 1068 unsigned int n) 1069 { 1070 unsigned int i, j; 1071 1072 for (i = 0, j = 0; i < num_mod_clks && j < n; i++) 1073 if (mod_clks[i].id == clks[j].clk) { 1074 mod_clks[i].parent = clks[j].parent; 1075 j++; 1076 } 1077 } 1078 1079 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 1080 MODULE_LICENSE("GPL v2"); 1081