1 /* 2 * R-Car Gen3 Clock Pulse Generator 3 * 4 * Copyright (C) 2015-2016 Glider bvba 5 * 6 * Based on clk-rcar-gen3.c 7 * 8 * Copyright (C) 2015 Renesas Electronics Corp. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 */ 14 15 #include <linux/bug.h> 16 #include <linux/bitfield.h> 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/device.h> 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/pm.h> 24 #include <linux/slab.h> 25 #include <linux/sys_soc.h> 26 27 #include "renesas-cpg-mssr.h" 28 #include "rcar-gen3-cpg.h" 29 30 #define CPG_PLL0CR 0x00d8 31 #define CPG_PLL2CR 0x002c 32 #define CPG_PLL4CR 0x01f4 33 34 struct cpg_simple_notifier { 35 struct notifier_block nb; 36 void __iomem *reg; 37 u32 saved; 38 }; 39 40 static int cpg_simple_notifier_call(struct notifier_block *nb, 41 unsigned long action, void *data) 42 { 43 struct cpg_simple_notifier *csn = 44 container_of(nb, struct cpg_simple_notifier, nb); 45 46 switch (action) { 47 case PM_EVENT_SUSPEND: 48 csn->saved = readl(csn->reg); 49 return NOTIFY_OK; 50 51 case PM_EVENT_RESUME: 52 writel(csn->saved, csn->reg); 53 return NOTIFY_OK; 54 } 55 return NOTIFY_DONE; 56 } 57 58 static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, 59 struct cpg_simple_notifier *csn) 60 { 61 csn->nb.notifier_call = cpg_simple_notifier_call; 62 raw_notifier_chain_register(notifiers, &csn->nb); 63 } 64 65 /* 66 * Z Clock & Z2 Clock 67 * 68 * Traits of this clock: 69 * prepare - clk_prepare only ensures that parents are prepared 70 * enable - clk_enable only ensures that parents are enabled 71 * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2 72 * parent - fixed parent. No clk_set_parent support 73 */ 74 #define CPG_FRQCRB 0x00000004 75 #define CPG_FRQCRB_KICK BIT(31) 76 #define CPG_FRQCRC 0x000000e0 77 #define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) 78 #define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) 79 80 struct cpg_z_clk { 81 struct clk_hw hw; 82 void __iomem *reg; 83 void __iomem *kick_reg; 84 unsigned long mask; 85 }; 86 87 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) 88 89 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 90 unsigned long parent_rate) 91 { 92 struct cpg_z_clk *zclk = to_z_clk(hw); 93 unsigned int mult; 94 u32 val; 95 96 val = readl(zclk->reg) & zclk->mask; 97 mult = 32 - (val >> __ffs(zclk->mask)); 98 99 /* Factor of 2 is for fixed divider */ 100 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2); 101 } 102 103 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, 104 unsigned long *parent_rate) 105 { 106 /* Factor of 2 is for fixed divider */ 107 unsigned long prate = *parent_rate / 2; 108 unsigned int mult; 109 110 mult = div_u64(rate * 32ULL, prate); 111 mult = clamp(mult, 1U, 32U); 112 113 return (u64)prate * mult / 32; 114 } 115 116 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 117 unsigned long parent_rate) 118 { 119 struct cpg_z_clk *zclk = to_z_clk(hw); 120 unsigned int mult; 121 unsigned int i; 122 u32 val, kick; 123 124 /* Factor of 2 is for fixed divider */ 125 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); 126 mult = clamp(mult, 1U, 32U); 127 128 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) 129 return -EBUSY; 130 131 val = readl(zclk->reg) & ~zclk->mask; 132 val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask; 133 writel(val, zclk->reg); 134 135 /* 136 * Set KICK bit in FRQCRB to update hardware setting and wait for 137 * clock change completion. 138 */ 139 kick = readl(zclk->kick_reg); 140 kick |= CPG_FRQCRB_KICK; 141 writel(kick, zclk->kick_reg); 142 143 /* 144 * Note: There is no HW information about the worst case latency. 145 * 146 * Using experimental measurements, it seems that no more than 147 * ~10 iterations are needed, independently of the CPU rate. 148 * Since this value might be dependent of external xtal rate, pll1 149 * rate or even the other emulation clocks rate, use 1000 as a 150 * "super" safe value. 151 */ 152 for (i = 1000; i; i--) { 153 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) 154 return 0; 155 156 cpu_relax(); 157 } 158 159 return -ETIMEDOUT; 160 } 161 162 static const struct clk_ops cpg_z_clk_ops = { 163 .recalc_rate = cpg_z_clk_recalc_rate, 164 .round_rate = cpg_z_clk_round_rate, 165 .set_rate = cpg_z_clk_set_rate, 166 }; 167 168 static struct clk * __init cpg_z_clk_register(const char *name, 169 const char *parent_name, 170 void __iomem *reg, 171 unsigned long mask) 172 { 173 struct clk_init_data init; 174 struct cpg_z_clk *zclk; 175 struct clk *clk; 176 177 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); 178 if (!zclk) 179 return ERR_PTR(-ENOMEM); 180 181 init.name = name; 182 init.ops = &cpg_z_clk_ops; 183 init.flags = 0; 184 init.parent_names = &parent_name; 185 init.num_parents = 1; 186 187 zclk->reg = reg + CPG_FRQCRC; 188 zclk->kick_reg = reg + CPG_FRQCRB; 189 zclk->hw.init = &init; 190 zclk->mask = mask; 191 192 clk = clk_register(NULL, &zclk->hw); 193 if (IS_ERR(clk)) 194 kfree(zclk); 195 196 return clk; 197 } 198 199 /* 200 * SDn Clock 201 */ 202 #define CPG_SD_STP_HCK BIT(9) 203 #define CPG_SD_STP_CK BIT(8) 204 205 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) 206 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) 207 208 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ 209 { \ 210 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ 211 ((stp_ck) ? CPG_SD_STP_CK : 0) | \ 212 ((sd_srcfc) << 2) | \ 213 ((sd_fc) << 0), \ 214 .div = (sd_div), \ 215 } 216 217 struct sd_div_table { 218 u32 val; 219 unsigned int div; 220 }; 221 222 struct sd_clock { 223 struct clk_hw hw; 224 const struct sd_div_table *div_table; 225 struct cpg_simple_notifier csn; 226 unsigned int div_num; 227 unsigned int div_min; 228 unsigned int div_max; 229 unsigned int cur_div_idx; 230 }; 231 232 /* SDn divider 233 * sd_srcfc sd_fc div 234 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc 235 *------------------------------------------------------------------- 236 * 0 0 0 (1) 1 (4) 4 237 * 0 0 1 (2) 1 (4) 8 238 * 1 0 2 (4) 1 (4) 16 239 * 1 0 3 (8) 1 (4) 32 240 * 1 0 4 (16) 1 (4) 64 241 * 0 0 0 (1) 0 (2) 2 242 * 0 0 1 (2) 0 (2) 4 243 * 1 0 2 (4) 0 (2) 8 244 * 1 0 3 (8) 0 (2) 16 245 * 1 0 4 (16) 0 (2) 32 246 */ 247 static const struct sd_div_table cpg_sd_div_table[] = { 248 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ 249 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), 250 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), 251 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), 252 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), 253 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), 254 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), 255 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), 256 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), 257 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), 258 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), 259 }; 260 261 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw) 262 263 static int cpg_sd_clock_enable(struct clk_hw *hw) 264 { 265 struct sd_clock *clock = to_sd_clock(hw); 266 u32 val = readl(clock->csn.reg); 267 268 val &= ~(CPG_SD_STP_MASK); 269 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK; 270 271 writel(val, clock->csn.reg); 272 273 return 0; 274 } 275 276 static void cpg_sd_clock_disable(struct clk_hw *hw) 277 { 278 struct sd_clock *clock = to_sd_clock(hw); 279 280 writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg); 281 } 282 283 static int cpg_sd_clock_is_enabled(struct clk_hw *hw) 284 { 285 struct sd_clock *clock = to_sd_clock(hw); 286 287 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK); 288 } 289 290 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, 291 unsigned long parent_rate) 292 { 293 struct sd_clock *clock = to_sd_clock(hw); 294 295 return DIV_ROUND_CLOSEST(parent_rate, 296 clock->div_table[clock->cur_div_idx].div); 297 } 298 299 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, 300 unsigned long rate, 301 unsigned long parent_rate) 302 { 303 unsigned int div; 304 305 if (!rate) 306 rate = 1; 307 308 div = DIV_ROUND_CLOSEST(parent_rate, rate); 309 310 return clamp_t(unsigned int, div, clock->div_min, clock->div_max); 311 } 312 313 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, 314 unsigned long *parent_rate) 315 { 316 struct sd_clock *clock = to_sd_clock(hw); 317 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate); 318 319 return DIV_ROUND_CLOSEST(*parent_rate, div); 320 } 321 322 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, 323 unsigned long parent_rate) 324 { 325 struct sd_clock *clock = to_sd_clock(hw); 326 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); 327 u32 val; 328 unsigned int i; 329 330 for (i = 0; i < clock->div_num; i++) 331 if (div == clock->div_table[i].div) 332 break; 333 334 if (i >= clock->div_num) 335 return -EINVAL; 336 337 clock->cur_div_idx = i; 338 339 val = readl(clock->csn.reg); 340 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK); 341 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK); 342 writel(val, clock->csn.reg); 343 344 return 0; 345 } 346 347 static const struct clk_ops cpg_sd_clock_ops = { 348 .enable = cpg_sd_clock_enable, 349 .disable = cpg_sd_clock_disable, 350 .is_enabled = cpg_sd_clock_is_enabled, 351 .recalc_rate = cpg_sd_clock_recalc_rate, 352 .round_rate = cpg_sd_clock_round_rate, 353 .set_rate = cpg_sd_clock_set_rate, 354 }; 355 356 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, 357 void __iomem *base, const char *parent_name, 358 struct raw_notifier_head *notifiers) 359 { 360 struct clk_init_data init; 361 struct sd_clock *clock; 362 struct clk *clk; 363 unsigned int i; 364 u32 sd_fc; 365 366 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 367 if (!clock) 368 return ERR_PTR(-ENOMEM); 369 370 init.name = core->name; 371 init.ops = &cpg_sd_clock_ops; 372 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; 373 init.parent_names = &parent_name; 374 init.num_parents = 1; 375 376 clock->csn.reg = base + core->offset; 377 clock->hw.init = &init; 378 clock->div_table = cpg_sd_div_table; 379 clock->div_num = ARRAY_SIZE(cpg_sd_div_table); 380 381 sd_fc = readl(clock->csn.reg) & CPG_SD_FC_MASK; 382 for (i = 0; i < clock->div_num; i++) 383 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK)) 384 break; 385 386 if (WARN_ON(i >= clock->div_num)) { 387 kfree(clock); 388 return ERR_PTR(-EINVAL); 389 } 390 391 clock->cur_div_idx = i; 392 393 clock->div_max = clock->div_table[0].div; 394 clock->div_min = clock->div_max; 395 for (i = 1; i < clock->div_num; i++) { 396 clock->div_max = max(clock->div_max, clock->div_table[i].div); 397 clock->div_min = min(clock->div_min, clock->div_table[i].div); 398 } 399 400 clk = clk_register(NULL, &clock->hw); 401 if (IS_ERR(clk)) 402 goto free_clock; 403 404 cpg_simple_notifier_register(notifiers, &clock->csn); 405 return clk; 406 407 free_clock: 408 kfree(clock); 409 return clk; 410 } 411 412 413 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; 414 static unsigned int cpg_clk_extalr __initdata; 415 static u32 cpg_mode __initdata; 416 static u32 cpg_quirks __initdata; 417 418 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ 419 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ 420 421 static const struct soc_device_attribute cpg_quirks_match[] __initconst = { 422 { 423 .soc_id = "r8a7795", .revision = "ES1.0", 424 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL), 425 }, 426 { 427 .soc_id = "r8a7795", .revision = "ES1.*", 428 .data = (void *)RCKCR_CKSEL, 429 }, 430 { 431 .soc_id = "r8a7796", .revision = "ES1.0", 432 .data = (void *)RCKCR_CKSEL, 433 }, 434 { /* sentinel */ } 435 }; 436 437 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 438 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 439 struct clk **clks, void __iomem *base, 440 struct raw_notifier_head *notifiers) 441 { 442 const struct clk *parent; 443 unsigned int mult = 1; 444 unsigned int div = 1; 445 u32 value; 446 447 parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */ 448 if (IS_ERR(parent)) 449 return ERR_CAST(parent); 450 451 switch (core->type) { 452 case CLK_TYPE_GEN3_MAIN: 453 div = cpg_pll_config->extal_div; 454 break; 455 456 case CLK_TYPE_GEN3_PLL0: 457 /* 458 * PLL0 is a configurable multiplier clock. Register it as a 459 * fixed factor clock for now as there's no generic multiplier 460 * clock implementation and we currently have no need to change 461 * the multiplier value. 462 */ 463 value = readl(base + CPG_PLL0CR); 464 mult = (((value >> 24) & 0x7f) + 1) * 2; 465 if (cpg_quirks & PLL_ERRATA) 466 mult *= 2; 467 break; 468 469 case CLK_TYPE_GEN3_PLL1: 470 mult = cpg_pll_config->pll1_mult; 471 div = cpg_pll_config->pll1_div; 472 break; 473 474 case CLK_TYPE_GEN3_PLL2: 475 /* 476 * PLL2 is a configurable multiplier clock. Register it as a 477 * fixed factor clock for now as there's no generic multiplier 478 * clock implementation and we currently have no need to change 479 * the multiplier value. 480 */ 481 value = readl(base + CPG_PLL2CR); 482 mult = (((value >> 24) & 0x7f) + 1) * 2; 483 if (cpg_quirks & PLL_ERRATA) 484 mult *= 2; 485 break; 486 487 case CLK_TYPE_GEN3_PLL3: 488 mult = cpg_pll_config->pll3_mult; 489 div = cpg_pll_config->pll3_div; 490 break; 491 492 case CLK_TYPE_GEN3_PLL4: 493 /* 494 * PLL4 is a configurable multiplier clock. Register it as a 495 * fixed factor clock for now as there's no generic multiplier 496 * clock implementation and we currently have no need to change 497 * the multiplier value. 498 */ 499 value = readl(base + CPG_PLL4CR); 500 mult = (((value >> 24) & 0x7f) + 1) * 2; 501 if (cpg_quirks & PLL_ERRATA) 502 mult *= 2; 503 break; 504 505 case CLK_TYPE_GEN3_SD: 506 return cpg_sd_clk_register(core, base, __clk_get_name(parent), 507 notifiers); 508 509 case CLK_TYPE_GEN3_R: 510 if (cpg_quirks & RCKCR_CKSEL) { 511 struct cpg_simple_notifier *csn; 512 513 csn = kzalloc(sizeof(*csn), GFP_KERNEL); 514 if (!csn) 515 return ERR_PTR(-ENOMEM); 516 517 csn->reg = base + CPG_RCKCR; 518 519 /* 520 * RINT is default. 521 * Only if EXTALR is populated, we switch to it. 522 */ 523 value = readl(csn->reg) & 0x3f; 524 525 if (clk_get_rate(clks[cpg_clk_extalr])) { 526 parent = clks[cpg_clk_extalr]; 527 value |= BIT(15); 528 } 529 530 writel(value, csn->reg); 531 cpg_simple_notifier_register(notifiers, csn); 532 break; 533 } 534 535 /* Select parent clock of RCLK by MD28 */ 536 if (cpg_mode & BIT(28)) 537 parent = clks[cpg_clk_extalr]; 538 break; 539 540 case CLK_TYPE_GEN3_PE: 541 /* 542 * Peripheral clock with a fixed divider, selectable between 543 * clean and spread spectrum parents using MD12 544 */ 545 if (cpg_mode & BIT(12)) { 546 /* Clean */ 547 div = core->div & 0xffff; 548 } else { 549 /* SCCG */ 550 parent = clks[core->parent >> 16]; 551 if (IS_ERR(parent)) 552 return ERR_CAST(parent); 553 div = core->div >> 16; 554 } 555 mult = 1; 556 break; 557 558 case CLK_TYPE_GEN3_Z: 559 return cpg_z_clk_register(core->name, __clk_get_name(parent), 560 base, CPG_FRQCRC_ZFC_MASK); 561 562 case CLK_TYPE_GEN3_Z2: 563 return cpg_z_clk_register(core->name, __clk_get_name(parent), 564 base, CPG_FRQCRC_Z2FC_MASK); 565 566 default: 567 return ERR_PTR(-EINVAL); 568 } 569 570 return clk_register_fixed_factor(NULL, core->name, 571 __clk_get_name(parent), 0, mult, div); 572 } 573 574 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 575 unsigned int clk_extalr, u32 mode) 576 { 577 const struct soc_device_attribute *attr; 578 579 cpg_pll_config = config; 580 cpg_clk_extalr = clk_extalr; 581 cpg_mode = mode; 582 attr = soc_device_match(cpg_quirks_match); 583 if (attr) 584 cpg_quirks = (uintptr_t)attr->data; 585 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); 586 return 0; 587 } 588