1 /*
2  * R-Car Gen3 Clock Pulse Generator
3  *
4  * Copyright (C) 2015-2016 Glider bvba
5  *
6  * Based on clk-rcar-gen3.c
7  *
8  * Copyright (C) 2015 Renesas Electronics Corp.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; version 2 of the License.
13  */
14 
15 #include <linux/bug.h>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/device.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/sys_soc.h>
24 
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
27 
28 #define CPG_PLL0CR		0x00d8
29 #define CPG_PLL2CR		0x002c
30 #define CPG_PLL4CR		0x01f4
31 
32 
33 /*
34  * SDn Clock
35  */
36 #define CPG_SD_STP_HCK		BIT(9)
37 #define CPG_SD_STP_CK		BIT(8)
38 
39 #define CPG_SD_STP_MASK		(CPG_SD_STP_HCK | CPG_SD_STP_CK)
40 #define CPG_SD_FC_MASK		(0x7 << 2 | 0x3 << 0)
41 
42 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
43 { \
44 	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
45 	       ((stp_ck) ? CPG_SD_STP_CK : 0) | \
46 	       ((sd_srcfc) << 2) | \
47 	       ((sd_fc) << 0), \
48 	.div = (sd_div), \
49 }
50 
51 struct sd_div_table {
52 	u32 val;
53 	unsigned int div;
54 };
55 
56 struct sd_clock {
57 	struct clk_hw hw;
58 	void __iomem *reg;
59 	const struct sd_div_table *div_table;
60 	unsigned int div_num;
61 	unsigned int div_min;
62 	unsigned int div_max;
63 };
64 
65 /* SDn divider
66  *                     sd_srcfc   sd_fc   div
67  * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
68  *-------------------------------------------------------------------
69  *  0         0         0 (1)      1 (4)      4
70  *  0         0         1 (2)      1 (4)      8
71  *  1         0         2 (4)      1 (4)     16
72  *  1         0         3 (8)      1 (4)     32
73  *  1         0         4 (16)     1 (4)     64
74  *  0         0         0 (1)      0 (2)      2
75  *  0         0         1 (2)      0 (2)      4
76  *  1         0         2 (4)      0 (2)      8
77  *  1         0         3 (8)      0 (2)     16
78  *  1         0         4 (16)     0 (2)     32
79  */
80 static const struct sd_div_table cpg_sd_div_table[] = {
81 /*	CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
82 	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
83 	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
84 	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
85 	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
86 	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
87 	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
88 	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
89 	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
90 	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
91 	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
92 };
93 
94 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
95 
96 static int cpg_sd_clock_enable(struct clk_hw *hw)
97 {
98 	struct sd_clock *clock = to_sd_clock(hw);
99 	u32 val, sd_fc;
100 	unsigned int i;
101 
102 	val = readl(clock->reg);
103 
104 	sd_fc = val & CPG_SD_FC_MASK;
105 	for (i = 0; i < clock->div_num; i++)
106 		if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
107 			break;
108 
109 	if (i >= clock->div_num)
110 		return -EINVAL;
111 
112 	val &= ~(CPG_SD_STP_MASK);
113 	val |= clock->div_table[i].val & CPG_SD_STP_MASK;
114 
115 	writel(val, clock->reg);
116 
117 	return 0;
118 }
119 
120 static void cpg_sd_clock_disable(struct clk_hw *hw)
121 {
122 	struct sd_clock *clock = to_sd_clock(hw);
123 
124 	writel(readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
125 }
126 
127 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
128 {
129 	struct sd_clock *clock = to_sd_clock(hw);
130 
131 	return !(readl(clock->reg) & CPG_SD_STP_MASK);
132 }
133 
134 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
135 						unsigned long parent_rate)
136 {
137 	struct sd_clock *clock = to_sd_clock(hw);
138 	unsigned long rate = parent_rate;
139 	u32 val, sd_fc;
140 	unsigned int i;
141 
142 	val = readl(clock->reg);
143 
144 	sd_fc = val & CPG_SD_FC_MASK;
145 	for (i = 0; i < clock->div_num; i++)
146 		if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
147 			break;
148 
149 	if (i >= clock->div_num)
150 		return -EINVAL;
151 
152 	return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
153 }
154 
155 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
156 					  unsigned long rate,
157 					  unsigned long parent_rate)
158 {
159 	unsigned int div;
160 
161 	if (!rate)
162 		rate = 1;
163 
164 	div = DIV_ROUND_CLOSEST(parent_rate, rate);
165 
166 	return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
167 }
168 
169 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
170 				      unsigned long *parent_rate)
171 {
172 	struct sd_clock *clock = to_sd_clock(hw);
173 	unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
174 
175 	return DIV_ROUND_CLOSEST(*parent_rate, div);
176 }
177 
178 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
179 				   unsigned long parent_rate)
180 {
181 	struct sd_clock *clock = to_sd_clock(hw);
182 	unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
183 	u32 val;
184 	unsigned int i;
185 
186 	for (i = 0; i < clock->div_num; i++)
187 		if (div == clock->div_table[i].div)
188 			break;
189 
190 	if (i >= clock->div_num)
191 		return -EINVAL;
192 
193 	val = readl(clock->reg);
194 	val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
195 	val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
196 	writel(val, clock->reg);
197 
198 	return 0;
199 }
200 
201 static const struct clk_ops cpg_sd_clock_ops = {
202 	.enable = cpg_sd_clock_enable,
203 	.disable = cpg_sd_clock_disable,
204 	.is_enabled = cpg_sd_clock_is_enabled,
205 	.recalc_rate = cpg_sd_clock_recalc_rate,
206 	.round_rate = cpg_sd_clock_round_rate,
207 	.set_rate = cpg_sd_clock_set_rate,
208 };
209 
210 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
211 					       void __iomem *base,
212 					       const char *parent_name)
213 {
214 	struct clk_init_data init;
215 	struct sd_clock *clock;
216 	struct clk *clk;
217 	unsigned int i;
218 
219 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
220 	if (!clock)
221 		return ERR_PTR(-ENOMEM);
222 
223 	init.name = core->name;
224 	init.ops = &cpg_sd_clock_ops;
225 	init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
226 	init.parent_names = &parent_name;
227 	init.num_parents = 1;
228 
229 	clock->reg = base + core->offset;
230 	clock->hw.init = &init;
231 	clock->div_table = cpg_sd_div_table;
232 	clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
233 
234 	clock->div_max = clock->div_table[0].div;
235 	clock->div_min = clock->div_max;
236 	for (i = 1; i < clock->div_num; i++) {
237 		clock->div_max = max(clock->div_max, clock->div_table[i].div);
238 		clock->div_min = min(clock->div_min, clock->div_table[i].div);
239 	}
240 
241 	clk = clk_register(NULL, &clock->hw);
242 	if (IS_ERR(clk))
243 		kfree(clock);
244 
245 	return clk;
246 }
247 
248 
249 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
250 static unsigned int cpg_clk_extalr __initdata;
251 static u32 cpg_mode __initdata;
252 static u32 cpg_quirks __initdata;
253 
254 #define PLL_ERRATA	BIT(0)		/* Missing PLL0/2/4 post-divider */
255 #define RCKCR_CKSEL	BIT(1)		/* Manual RCLK parent selection */
256 
257 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
258 	{
259 		.soc_id = "r8a7795", .revision = "ES1.0",
260 		.data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
261 	},
262 	{
263 		.soc_id = "r8a7795", .revision = "ES1.*",
264 		.data = (void *)RCKCR_CKSEL,
265 	},
266 	{
267 		.soc_id = "r8a7796", .revision = "ES1.0",
268 		.data = (void *)RCKCR_CKSEL,
269 	},
270 	{ /* sentinel */ }
271 };
272 
273 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
274 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
275 	struct clk **clks, void __iomem *base)
276 {
277 	const struct clk *parent;
278 	unsigned int mult = 1;
279 	unsigned int div = 1;
280 	u32 value;
281 
282 	parent = clks[core->parent];
283 	if (IS_ERR(parent))
284 		return ERR_CAST(parent);
285 
286 	switch (core->type) {
287 	case CLK_TYPE_GEN3_MAIN:
288 		div = cpg_pll_config->extal_div;
289 		break;
290 
291 	case CLK_TYPE_GEN3_PLL0:
292 		/*
293 		 * PLL0 is a configurable multiplier clock. Register it as a
294 		 * fixed factor clock for now as there's no generic multiplier
295 		 * clock implementation and we currently have no need to change
296 		 * the multiplier value.
297 		 */
298 		value = readl(base + CPG_PLL0CR);
299 		mult = (((value >> 24) & 0x7f) + 1) * 2;
300 		if (cpg_quirks & PLL_ERRATA)
301 			mult *= 2;
302 		break;
303 
304 	case CLK_TYPE_GEN3_PLL1:
305 		mult = cpg_pll_config->pll1_mult;
306 		break;
307 
308 	case CLK_TYPE_GEN3_PLL2:
309 		/*
310 		 * PLL2 is a configurable multiplier clock. Register it as a
311 		 * fixed factor clock for now as there's no generic multiplier
312 		 * clock implementation and we currently have no need to change
313 		 * the multiplier value.
314 		 */
315 		value = readl(base + CPG_PLL2CR);
316 		mult = (((value >> 24) & 0x7f) + 1) * 2;
317 		if (cpg_quirks & PLL_ERRATA)
318 			mult *= 2;
319 		break;
320 
321 	case CLK_TYPE_GEN3_PLL3:
322 		mult = cpg_pll_config->pll3_mult;
323 		break;
324 
325 	case CLK_TYPE_GEN3_PLL4:
326 		/*
327 		 * PLL4 is a configurable multiplier clock. Register it as a
328 		 * fixed factor clock for now as there's no generic multiplier
329 		 * clock implementation and we currently have no need to change
330 		 * the multiplier value.
331 		 */
332 		value = readl(base + CPG_PLL4CR);
333 		mult = (((value >> 24) & 0x7f) + 1) * 2;
334 		if (cpg_quirks & PLL_ERRATA)
335 			mult *= 2;
336 		break;
337 
338 	case CLK_TYPE_GEN3_SD:
339 		return cpg_sd_clk_register(core, base, __clk_get_name(parent));
340 
341 	case CLK_TYPE_GEN3_R:
342 		if (cpg_quirks & RCKCR_CKSEL) {
343 			/*
344 			 * RINT is default.
345 			 * Only if EXTALR is populated, we switch to it.
346 			 */
347 			value = readl(base + CPG_RCKCR) & 0x3f;
348 
349 			if (clk_get_rate(clks[cpg_clk_extalr])) {
350 				parent = clks[cpg_clk_extalr];
351 				value |= BIT(15);
352 			}
353 
354 			writel(value, base + CPG_RCKCR);
355 			break;
356 		}
357 
358 		/* Select parent clock of RCLK by MD28 */
359 		if (cpg_mode & BIT(28))
360 			parent = clks[cpg_clk_extalr];
361 		break;
362 
363 	default:
364 		return ERR_PTR(-EINVAL);
365 	}
366 
367 	return clk_register_fixed_factor(NULL, core->name,
368 					 __clk_get_name(parent), 0, mult, div);
369 }
370 
371 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
372 			      unsigned int clk_extalr, u32 mode)
373 {
374 	const struct soc_device_attribute *attr;
375 
376 	cpg_pll_config = config;
377 	cpg_clk_extalr = clk_extalr;
378 	cpg_mode = mode;
379 	attr = soc_device_match(cpg_quirks_match);
380 	if (attr)
381 		cpg_quirks = (uintptr_t)attr->data;
382 	pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
383 	return 0;
384 }
385