1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R-Car Gen3 Clock Pulse Generator 4 * 5 * Copyright (C) 2015-2018 Glider bvba 6 * Copyright (C) 2019 Renesas Electronics Corp. 7 * 8 * Based on clk-rcar-gen3.c 9 * 10 * Copyright (C) 2015 Renesas Electronics Corp. 11 */ 12 13 #include <linux/bug.h> 14 #include <linux/bitfield.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/device.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/pm.h> 22 #include <linux/slab.h> 23 #include <linux/sys_soc.h> 24 25 #include "renesas-cpg-mssr.h" 26 #include "rcar-cpg-lib.h" 27 #include "rcar-gen3-cpg.h" 28 29 #define CPG_PLL0CR 0x00d8 30 #define CPG_PLL2CR 0x002c 31 #define CPG_PLL4CR 0x01f4 32 33 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ 34 35 /* 36 * Z Clock & Z2 Clock 37 * 38 * Traits of this clock: 39 * prepare - clk_prepare only ensures that parents are prepared 40 * enable - clk_enable only ensures that parents are enabled 41 * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2 42 * parent - fixed parent. No clk_set_parent support 43 */ 44 #define CPG_FRQCRB 0x00000004 45 #define CPG_FRQCRB_KICK BIT(31) 46 #define CPG_FRQCRC 0x000000e0 47 48 struct cpg_z_clk { 49 struct clk_hw hw; 50 void __iomem *reg; 51 void __iomem *kick_reg; 52 unsigned long mask; 53 unsigned int fixed_div; 54 }; 55 56 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) 57 58 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 59 unsigned long parent_rate) 60 { 61 struct cpg_z_clk *zclk = to_z_clk(hw); 62 unsigned int mult; 63 u32 val; 64 65 val = readl(zclk->reg) & zclk->mask; 66 mult = 32 - (val >> __ffs(zclk->mask)); 67 68 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 69 32 * zclk->fixed_div); 70 } 71 72 static int cpg_z_clk_determine_rate(struct clk_hw *hw, 73 struct clk_rate_request *req) 74 { 75 struct cpg_z_clk *zclk = to_z_clk(hw); 76 unsigned int min_mult, max_mult, mult; 77 unsigned long prate; 78 79 prate = req->best_parent_rate / zclk->fixed_div; 80 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); 81 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); 82 if (max_mult < min_mult) 83 return -EINVAL; 84 85 mult = div64_ul(req->rate * 32ULL, prate); 86 mult = clamp(mult, min_mult, max_mult); 87 88 req->rate = div_u64((u64)prate * mult, 32); 89 return 0; 90 } 91 92 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 93 unsigned long parent_rate) 94 { 95 struct cpg_z_clk *zclk = to_z_clk(hw); 96 unsigned int mult; 97 unsigned int i; 98 99 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, 100 parent_rate); 101 mult = clamp(mult, 1U, 32U); 102 103 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) 104 return -EBUSY; 105 106 cpg_reg_modify(zclk->reg, zclk->mask, 107 ((32 - mult) << __ffs(zclk->mask)) & zclk->mask); 108 109 /* 110 * Set KICK bit in FRQCRB to update hardware setting and wait for 111 * clock change completion. 112 */ 113 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); 114 115 /* 116 * Note: There is no HW information about the worst case latency. 117 * 118 * Using experimental measurements, it seems that no more than 119 * ~10 iterations are needed, independently of the CPU rate. 120 * Since this value might be dependent of external xtal rate, pll1 121 * rate or even the other emulation clocks rate, use 1000 as a 122 * "super" safe value. 123 */ 124 for (i = 1000; i; i--) { 125 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) 126 return 0; 127 128 cpu_relax(); 129 } 130 131 return -ETIMEDOUT; 132 } 133 134 static const struct clk_ops cpg_z_clk_ops = { 135 .recalc_rate = cpg_z_clk_recalc_rate, 136 .determine_rate = cpg_z_clk_determine_rate, 137 .set_rate = cpg_z_clk_set_rate, 138 }; 139 140 static struct clk * __init cpg_z_clk_register(const char *name, 141 const char *parent_name, 142 void __iomem *reg, 143 unsigned int div, 144 unsigned int offset) 145 { 146 struct clk_init_data init = {}; 147 struct cpg_z_clk *zclk; 148 struct clk *clk; 149 150 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); 151 if (!zclk) 152 return ERR_PTR(-ENOMEM); 153 154 init.name = name; 155 init.ops = &cpg_z_clk_ops; 156 init.flags = 0; 157 init.parent_names = &parent_name; 158 init.num_parents = 1; 159 160 zclk->reg = reg + CPG_FRQCRC; 161 zclk->kick_reg = reg + CPG_FRQCRB; 162 zclk->hw.init = &init; 163 zclk->mask = GENMASK(offset + 4, offset); 164 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ 165 166 clk = clk_register(NULL, &zclk->hw); 167 if (IS_ERR(clk)) 168 kfree(zclk); 169 170 return clk; 171 } 172 173 struct rpc_clock { 174 struct clk_divider div; 175 struct clk_gate gate; 176 /* 177 * One notifier covers both RPC and RPCD2 clocks as they are both 178 * controlled by the same RPCCKCR register... 179 */ 180 struct cpg_simple_notifier csn; 181 }; 182 183 static const struct clk_div_table cpg_rpcsrc_div_table[] = { 184 { 2, 5 }, { 3, 6 }, { 0, 0 }, 185 }; 186 187 static const struct clk_div_table cpg_rpc_div_table[] = { 188 { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 }, 189 }; 190 191 static struct clk * __init cpg_rpc_clk_register(const char *name, 192 void __iomem *base, const char *parent_name, 193 struct raw_notifier_head *notifiers) 194 { 195 struct rpc_clock *rpc; 196 struct clk *clk; 197 198 rpc = kzalloc(sizeof(*rpc), GFP_KERNEL); 199 if (!rpc) 200 return ERR_PTR(-ENOMEM); 201 202 rpc->div.reg = base + CPG_RPCCKCR; 203 rpc->div.width = 3; 204 rpc->div.table = cpg_rpc_div_table; 205 rpc->div.lock = &cpg_lock; 206 207 rpc->gate.reg = base + CPG_RPCCKCR; 208 rpc->gate.bit_idx = 8; 209 rpc->gate.flags = CLK_GATE_SET_TO_DISABLE; 210 rpc->gate.lock = &cpg_lock; 211 212 rpc->csn.reg = base + CPG_RPCCKCR; 213 214 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, 215 &rpc->div.hw, &clk_divider_ops, 216 &rpc->gate.hw, &clk_gate_ops, 217 CLK_SET_RATE_PARENT); 218 if (IS_ERR(clk)) { 219 kfree(rpc); 220 return clk; 221 } 222 223 cpg_simple_notifier_register(notifiers, &rpc->csn); 224 return clk; 225 } 226 227 struct rpcd2_clock { 228 struct clk_fixed_factor fixed; 229 struct clk_gate gate; 230 }; 231 232 static struct clk * __init cpg_rpcd2_clk_register(const char *name, 233 void __iomem *base, 234 const char *parent_name) 235 { 236 struct rpcd2_clock *rpcd2; 237 struct clk *clk; 238 239 rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL); 240 if (!rpcd2) 241 return ERR_PTR(-ENOMEM); 242 243 rpcd2->fixed.mult = 1; 244 rpcd2->fixed.div = 2; 245 246 rpcd2->gate.reg = base + CPG_RPCCKCR; 247 rpcd2->gate.bit_idx = 9; 248 rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE; 249 rpcd2->gate.lock = &cpg_lock; 250 251 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, 252 &rpcd2->fixed.hw, &clk_fixed_factor_ops, 253 &rpcd2->gate.hw, &clk_gate_ops, 254 CLK_SET_RATE_PARENT); 255 if (IS_ERR(clk)) 256 kfree(rpcd2); 257 258 return clk; 259 } 260 261 262 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; 263 static unsigned int cpg_clk_extalr __initdata; 264 static u32 cpg_mode __initdata; 265 static u32 cpg_quirks __initdata; 266 267 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ 268 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ 269 #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ 270 271 272 static const struct soc_device_attribute cpg_quirks_match[] __initconst = { 273 { 274 .soc_id = "r8a7795", .revision = "ES1.0", 275 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST), 276 }, 277 { 278 .soc_id = "r8a7795", .revision = "ES1.*", 279 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), 280 }, 281 { 282 .soc_id = "r8a7795", .revision = "ES2.0", 283 .data = (void *)SD_SKIP_FIRST, 284 }, 285 { 286 .soc_id = "r8a7796", .revision = "ES1.0", 287 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), 288 }, 289 { 290 .soc_id = "r8a7796", .revision = "ES1.1", 291 .data = (void *)SD_SKIP_FIRST, 292 }, 293 { /* sentinel */ } 294 }; 295 296 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 297 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 298 struct clk **clks, void __iomem *base, 299 struct raw_notifier_head *notifiers) 300 { 301 const struct clk *parent; 302 unsigned int mult = 1; 303 unsigned int div = 1; 304 u32 value; 305 306 parent = clks[core->parent & 0xffff]; /* some types use high bits */ 307 if (IS_ERR(parent)) 308 return ERR_CAST(parent); 309 310 switch (core->type) { 311 case CLK_TYPE_GEN3_MAIN: 312 div = cpg_pll_config->extal_div; 313 break; 314 315 case CLK_TYPE_GEN3_PLL0: 316 /* 317 * PLL0 is a configurable multiplier clock. Register it as a 318 * fixed factor clock for now as there's no generic multiplier 319 * clock implementation and we currently have no need to change 320 * the multiplier value. 321 */ 322 value = readl(base + CPG_PLL0CR); 323 mult = (((value >> 24) & 0x7f) + 1) * 2; 324 if (cpg_quirks & PLL_ERRATA) 325 mult *= 2; 326 break; 327 328 case CLK_TYPE_GEN3_PLL1: 329 mult = cpg_pll_config->pll1_mult; 330 div = cpg_pll_config->pll1_div; 331 break; 332 333 case CLK_TYPE_GEN3_PLL2: 334 /* 335 * PLL2 is a configurable multiplier clock. Register it as a 336 * fixed factor clock for now as there's no generic multiplier 337 * clock implementation and we currently have no need to change 338 * the multiplier value. 339 */ 340 value = readl(base + CPG_PLL2CR); 341 mult = (((value >> 24) & 0x7f) + 1) * 2; 342 if (cpg_quirks & PLL_ERRATA) 343 mult *= 2; 344 break; 345 346 case CLK_TYPE_GEN3_PLL3: 347 mult = cpg_pll_config->pll3_mult; 348 div = cpg_pll_config->pll3_div; 349 break; 350 351 case CLK_TYPE_GEN3_PLL4: 352 /* 353 * PLL4 is a configurable multiplier clock. Register it as a 354 * fixed factor clock for now as there's no generic multiplier 355 * clock implementation and we currently have no need to change 356 * the multiplier value. 357 */ 358 value = readl(base + CPG_PLL4CR); 359 mult = (((value >> 24) & 0x7f) + 1) * 2; 360 if (cpg_quirks & PLL_ERRATA) 361 mult *= 2; 362 break; 363 364 case CLK_TYPE_GEN3_SD: 365 return cpg_sd_clk_register(core->name, base, core->offset, 366 __clk_get_name(parent), notifiers, 367 cpg_quirks & SD_SKIP_FIRST); 368 369 case CLK_TYPE_GEN3_R: 370 if (cpg_quirks & RCKCR_CKSEL) { 371 struct cpg_simple_notifier *csn; 372 373 csn = kzalloc(sizeof(*csn), GFP_KERNEL); 374 if (!csn) 375 return ERR_PTR(-ENOMEM); 376 377 csn->reg = base + CPG_RCKCR; 378 379 /* 380 * RINT is default. 381 * Only if EXTALR is populated, we switch to it. 382 */ 383 value = readl(csn->reg) & 0x3f; 384 385 if (clk_get_rate(clks[cpg_clk_extalr])) { 386 parent = clks[cpg_clk_extalr]; 387 value |= CPG_RCKCR_CKSEL; 388 } 389 390 writel(value, csn->reg); 391 cpg_simple_notifier_register(notifiers, csn); 392 break; 393 } 394 395 /* Select parent clock of RCLK by MD28 */ 396 if (cpg_mode & BIT(28)) 397 parent = clks[cpg_clk_extalr]; 398 break; 399 400 case CLK_TYPE_GEN3_MDSEL: 401 /* 402 * Clock selectable between two parents and two fixed dividers 403 * using a mode pin 404 */ 405 if (cpg_mode & BIT(core->offset)) { 406 div = core->div & 0xffff; 407 } else { 408 parent = clks[core->parent >> 16]; 409 if (IS_ERR(parent)) 410 return ERR_CAST(parent); 411 div = core->div >> 16; 412 } 413 mult = 1; 414 break; 415 416 case CLK_TYPE_GEN3_Z: 417 return cpg_z_clk_register(core->name, __clk_get_name(parent), 418 base, core->div, core->offset); 419 420 case CLK_TYPE_GEN3_OSC: 421 /* 422 * Clock combining OSC EXTAL predivider and a fixed divider 423 */ 424 div = cpg_pll_config->osc_prediv * core->div; 425 break; 426 427 case CLK_TYPE_GEN3_RCKSEL: 428 /* 429 * Clock selectable between two parents and two fixed dividers 430 * using RCKCR.CKSEL 431 */ 432 if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) { 433 div = core->div & 0xffff; 434 } else { 435 parent = clks[core->parent >> 16]; 436 if (IS_ERR(parent)) 437 return ERR_CAST(parent); 438 div = core->div >> 16; 439 } 440 break; 441 442 case CLK_TYPE_GEN3_RPCSRC: 443 return clk_register_divider_table(NULL, core->name, 444 __clk_get_name(parent), 0, 445 base + CPG_RPCCKCR, 3, 2, 0, 446 cpg_rpcsrc_div_table, 447 &cpg_lock); 448 449 case CLK_TYPE_GEN3_E3_RPCSRC: 450 /* 451 * Register RPCSRC as fixed factor clock based on the 452 * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for 453 * which has been set prior to booting the kernel. 454 */ 455 value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3; 456 457 switch (value) { 458 case 0: 459 div = 5; 460 break; 461 case 1: 462 div = 3; 463 break; 464 case 2: 465 parent = clks[core->parent >> 16]; 466 if (IS_ERR(parent)) 467 return ERR_CAST(parent); 468 div = core->div; 469 break; 470 case 3: 471 default: 472 div = 2; 473 break; 474 } 475 break; 476 477 case CLK_TYPE_GEN3_RPC: 478 return cpg_rpc_clk_register(core->name, base, 479 __clk_get_name(parent), notifiers); 480 481 case CLK_TYPE_GEN3_RPCD2: 482 return cpg_rpcd2_clk_register(core->name, base, 483 __clk_get_name(parent)); 484 485 default: 486 return ERR_PTR(-EINVAL); 487 } 488 489 return clk_register_fixed_factor(NULL, core->name, 490 __clk_get_name(parent), 0, mult, div); 491 } 492 493 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 494 unsigned int clk_extalr, u32 mode) 495 { 496 const struct soc_device_attribute *attr; 497 498 cpg_pll_config = config; 499 cpg_clk_extalr = clk_extalr; 500 cpg_mode = mode; 501 attr = soc_device_match(cpg_quirks_match); 502 if (attr) 503 cpg_quirks = (uintptr_t)attr->data; 504 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); 505 506 spin_lock_init(&cpg_lock); 507 508 return 0; 509 } 510