1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R-Car Gen3 Clock Pulse Generator 4 * 5 * Copyright (C) 2015-2018 Glider bvba 6 * 7 * Based on clk-rcar-gen3.c 8 * 9 * Copyright (C) 2015 Renesas Electronics Corp. 10 */ 11 12 #include <linux/bug.h> 13 #include <linux/bitfield.h> 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/device.h> 17 #include <linux/err.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/pm.h> 21 #include <linux/slab.h> 22 #include <linux/sys_soc.h> 23 24 #include "renesas-cpg-mssr.h" 25 #include "rcar-gen3-cpg.h" 26 27 #define CPG_PLL0CR 0x00d8 28 #define CPG_PLL2CR 0x002c 29 #define CPG_PLL4CR 0x01f4 30 31 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ 32 33 struct cpg_simple_notifier { 34 struct notifier_block nb; 35 void __iomem *reg; 36 u32 saved; 37 }; 38 39 static int cpg_simple_notifier_call(struct notifier_block *nb, 40 unsigned long action, void *data) 41 { 42 struct cpg_simple_notifier *csn = 43 container_of(nb, struct cpg_simple_notifier, nb); 44 45 switch (action) { 46 case PM_EVENT_SUSPEND: 47 csn->saved = readl(csn->reg); 48 return NOTIFY_OK; 49 50 case PM_EVENT_RESUME: 51 writel(csn->saved, csn->reg); 52 return NOTIFY_OK; 53 } 54 return NOTIFY_DONE; 55 } 56 57 static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, 58 struct cpg_simple_notifier *csn) 59 { 60 csn->nb.notifier_call = cpg_simple_notifier_call; 61 raw_notifier_chain_register(notifiers, &csn->nb); 62 } 63 64 /* 65 * Z Clock & Z2 Clock 66 * 67 * Traits of this clock: 68 * prepare - clk_prepare only ensures that parents are prepared 69 * enable - clk_enable only ensures that parents are enabled 70 * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2 71 * parent - fixed parent. No clk_set_parent support 72 */ 73 #define CPG_FRQCRB 0x00000004 74 #define CPG_FRQCRB_KICK BIT(31) 75 #define CPG_FRQCRC 0x000000e0 76 #define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) 77 #define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) 78 79 struct cpg_z_clk { 80 struct clk_hw hw; 81 void __iomem *reg; 82 void __iomem *kick_reg; 83 unsigned long mask; 84 }; 85 86 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) 87 88 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, 89 unsigned long parent_rate) 90 { 91 struct cpg_z_clk *zclk = to_z_clk(hw); 92 unsigned int mult; 93 u32 val; 94 95 val = readl(zclk->reg) & zclk->mask; 96 mult = 32 - (val >> __ffs(zclk->mask)); 97 98 /* Factor of 2 is for fixed divider */ 99 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2); 100 } 101 102 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, 103 unsigned long *parent_rate) 104 { 105 /* Factor of 2 is for fixed divider */ 106 unsigned long prate = *parent_rate / 2; 107 unsigned int mult; 108 109 mult = div_u64(rate * 32ULL, prate); 110 mult = clamp(mult, 1U, 32U); 111 112 return (u64)prate * mult / 32; 113 } 114 115 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, 116 unsigned long parent_rate) 117 { 118 struct cpg_z_clk *zclk = to_z_clk(hw); 119 unsigned int mult; 120 unsigned int i; 121 u32 val, kick; 122 123 /* Factor of 2 is for fixed divider */ 124 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); 125 mult = clamp(mult, 1U, 32U); 126 127 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) 128 return -EBUSY; 129 130 val = readl(zclk->reg) & ~zclk->mask; 131 val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask; 132 writel(val, zclk->reg); 133 134 /* 135 * Set KICK bit in FRQCRB to update hardware setting and wait for 136 * clock change completion. 137 */ 138 kick = readl(zclk->kick_reg); 139 kick |= CPG_FRQCRB_KICK; 140 writel(kick, zclk->kick_reg); 141 142 /* 143 * Note: There is no HW information about the worst case latency. 144 * 145 * Using experimental measurements, it seems that no more than 146 * ~10 iterations are needed, independently of the CPU rate. 147 * Since this value might be dependent of external xtal rate, pll1 148 * rate or even the other emulation clocks rate, use 1000 as a 149 * "super" safe value. 150 */ 151 for (i = 1000; i; i--) { 152 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) 153 return 0; 154 155 cpu_relax(); 156 } 157 158 return -ETIMEDOUT; 159 } 160 161 static const struct clk_ops cpg_z_clk_ops = { 162 .recalc_rate = cpg_z_clk_recalc_rate, 163 .round_rate = cpg_z_clk_round_rate, 164 .set_rate = cpg_z_clk_set_rate, 165 }; 166 167 static struct clk * __init cpg_z_clk_register(const char *name, 168 const char *parent_name, 169 void __iomem *reg, 170 unsigned long mask) 171 { 172 struct clk_init_data init; 173 struct cpg_z_clk *zclk; 174 struct clk *clk; 175 176 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); 177 if (!zclk) 178 return ERR_PTR(-ENOMEM); 179 180 init.name = name; 181 init.ops = &cpg_z_clk_ops; 182 init.flags = 0; 183 init.parent_names = &parent_name; 184 init.num_parents = 1; 185 186 zclk->reg = reg + CPG_FRQCRC; 187 zclk->kick_reg = reg + CPG_FRQCRB; 188 zclk->hw.init = &init; 189 zclk->mask = mask; 190 191 clk = clk_register(NULL, &zclk->hw); 192 if (IS_ERR(clk)) 193 kfree(zclk); 194 195 return clk; 196 } 197 198 /* 199 * SDn Clock 200 */ 201 #define CPG_SD_STP_HCK BIT(9) 202 #define CPG_SD_STP_CK BIT(8) 203 204 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) 205 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) 206 207 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ 208 { \ 209 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ 210 ((stp_ck) ? CPG_SD_STP_CK : 0) | \ 211 ((sd_srcfc) << 2) | \ 212 ((sd_fc) << 0), \ 213 .div = (sd_div), \ 214 } 215 216 struct sd_div_table { 217 u32 val; 218 unsigned int div; 219 }; 220 221 struct sd_clock { 222 struct clk_hw hw; 223 const struct sd_div_table *div_table; 224 struct cpg_simple_notifier csn; 225 unsigned int div_num; 226 unsigned int div_min; 227 unsigned int div_max; 228 unsigned int cur_div_idx; 229 }; 230 231 /* SDn divider 232 * sd_srcfc sd_fc div 233 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc 234 *------------------------------------------------------------------- 235 * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP) 236 * 0 0 1 (2) 1 (4) 8 : SDR50 237 * 1 0 2 (4) 1 (4) 16 : HS / SDR25 238 * 1 0 3 (8) 1 (4) 32 : NS / SDR12 239 * 1 0 4 (16) 1 (4) 64 240 * 0 0 0 (1) 0 (2) 2 241 * 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP) 242 * 1 0 2 (4) 0 (2) 8 243 * 1 0 3 (8) 0 (2) 16 244 * 1 0 4 (16) 0 (2) 32 245 * 246 * NOTE: There is a quirk option to ignore the first row of the dividers 247 * table when searching for suitable settings. This is because HS400 on 248 * early ES versions of H3 and M3-W requires a specific setting to work. 249 */ 250 static const struct sd_div_table cpg_sd_div_table[] = { 251 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ 252 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), 253 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), 254 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), 255 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), 256 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), 257 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), 258 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), 259 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), 260 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), 261 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), 262 }; 263 264 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw) 265 266 static int cpg_sd_clock_enable(struct clk_hw *hw) 267 { 268 struct sd_clock *clock = to_sd_clock(hw); 269 u32 val = readl(clock->csn.reg); 270 271 val &= ~(CPG_SD_STP_MASK); 272 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK; 273 274 writel(val, clock->csn.reg); 275 276 return 0; 277 } 278 279 static void cpg_sd_clock_disable(struct clk_hw *hw) 280 { 281 struct sd_clock *clock = to_sd_clock(hw); 282 283 writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg); 284 } 285 286 static int cpg_sd_clock_is_enabled(struct clk_hw *hw) 287 { 288 struct sd_clock *clock = to_sd_clock(hw); 289 290 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK); 291 } 292 293 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, 294 unsigned long parent_rate) 295 { 296 struct sd_clock *clock = to_sd_clock(hw); 297 298 return DIV_ROUND_CLOSEST(parent_rate, 299 clock->div_table[clock->cur_div_idx].div); 300 } 301 302 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, 303 unsigned long rate, 304 unsigned long parent_rate) 305 { 306 unsigned int div; 307 308 if (!rate) 309 rate = 1; 310 311 div = DIV_ROUND_CLOSEST(parent_rate, rate); 312 313 return clamp_t(unsigned int, div, clock->div_min, clock->div_max); 314 } 315 316 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, 317 unsigned long *parent_rate) 318 { 319 struct sd_clock *clock = to_sd_clock(hw); 320 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate); 321 322 return DIV_ROUND_CLOSEST(*parent_rate, div); 323 } 324 325 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, 326 unsigned long parent_rate) 327 { 328 struct sd_clock *clock = to_sd_clock(hw); 329 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); 330 u32 val; 331 unsigned int i; 332 333 for (i = 0; i < clock->div_num; i++) 334 if (div == clock->div_table[i].div) 335 break; 336 337 if (i >= clock->div_num) 338 return -EINVAL; 339 340 clock->cur_div_idx = i; 341 342 val = readl(clock->csn.reg); 343 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK); 344 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK); 345 writel(val, clock->csn.reg); 346 347 return 0; 348 } 349 350 static const struct clk_ops cpg_sd_clock_ops = { 351 .enable = cpg_sd_clock_enable, 352 .disable = cpg_sd_clock_disable, 353 .is_enabled = cpg_sd_clock_is_enabled, 354 .recalc_rate = cpg_sd_clock_recalc_rate, 355 .round_rate = cpg_sd_clock_round_rate, 356 .set_rate = cpg_sd_clock_set_rate, 357 }; 358 359 static u32 cpg_quirks __initdata; 360 361 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ 362 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ 363 #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ 364 365 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, 366 void __iomem *base, const char *parent_name, 367 struct raw_notifier_head *notifiers) 368 { 369 struct clk_init_data init; 370 struct sd_clock *clock; 371 struct clk *clk; 372 unsigned int i; 373 u32 val; 374 375 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 376 if (!clock) 377 return ERR_PTR(-ENOMEM); 378 379 init.name = core->name; 380 init.ops = &cpg_sd_clock_ops; 381 init.flags = CLK_SET_RATE_PARENT; 382 init.parent_names = &parent_name; 383 init.num_parents = 1; 384 385 clock->csn.reg = base + core->offset; 386 clock->hw.init = &init; 387 clock->div_table = cpg_sd_div_table; 388 clock->div_num = ARRAY_SIZE(cpg_sd_div_table); 389 390 if (cpg_quirks & SD_SKIP_FIRST) { 391 clock->div_table++; 392 clock->div_num--; 393 } 394 395 val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK; 396 val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK); 397 writel(val, clock->csn.reg); 398 399 clock->div_max = clock->div_table[0].div; 400 clock->div_min = clock->div_max; 401 for (i = 1; i < clock->div_num; i++) { 402 clock->div_max = max(clock->div_max, clock->div_table[i].div); 403 clock->div_min = min(clock->div_min, clock->div_table[i].div); 404 } 405 406 clk = clk_register(NULL, &clock->hw); 407 if (IS_ERR(clk)) 408 goto free_clock; 409 410 cpg_simple_notifier_register(notifiers, &clock->csn); 411 return clk; 412 413 free_clock: 414 kfree(clock); 415 return clk; 416 } 417 418 419 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; 420 static unsigned int cpg_clk_extalr __initdata; 421 static u32 cpg_mode __initdata; 422 423 static const struct soc_device_attribute cpg_quirks_match[] __initconst = { 424 { 425 .soc_id = "r8a7795", .revision = "ES1.0", 426 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST), 427 }, 428 { 429 .soc_id = "r8a7795", .revision = "ES1.*", 430 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), 431 }, 432 { 433 .soc_id = "r8a7795", .revision = "ES2.0", 434 .data = (void *)SD_SKIP_FIRST, 435 }, 436 { 437 .soc_id = "r8a7796", .revision = "ES1.0", 438 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), 439 }, 440 { 441 .soc_id = "r8a7796", .revision = "ES1.1", 442 .data = (void *)SD_SKIP_FIRST, 443 }, 444 { /* sentinel */ } 445 }; 446 447 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 448 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 449 struct clk **clks, void __iomem *base, 450 struct raw_notifier_head *notifiers) 451 { 452 const struct clk *parent; 453 unsigned int mult = 1; 454 unsigned int div = 1; 455 u32 value; 456 457 parent = clks[core->parent & 0xffff]; /* some types use high bits */ 458 if (IS_ERR(parent)) 459 return ERR_CAST(parent); 460 461 switch (core->type) { 462 case CLK_TYPE_GEN3_MAIN: 463 div = cpg_pll_config->extal_div; 464 break; 465 466 case CLK_TYPE_GEN3_PLL0: 467 /* 468 * PLL0 is a configurable multiplier clock. Register it as a 469 * fixed factor clock for now as there's no generic multiplier 470 * clock implementation and we currently have no need to change 471 * the multiplier value. 472 */ 473 value = readl(base + CPG_PLL0CR); 474 mult = (((value >> 24) & 0x7f) + 1) * 2; 475 if (cpg_quirks & PLL_ERRATA) 476 mult *= 2; 477 break; 478 479 case CLK_TYPE_GEN3_PLL1: 480 mult = cpg_pll_config->pll1_mult; 481 div = cpg_pll_config->pll1_div; 482 break; 483 484 case CLK_TYPE_GEN3_PLL2: 485 /* 486 * PLL2 is a configurable multiplier clock. Register it as a 487 * fixed factor clock for now as there's no generic multiplier 488 * clock implementation and we currently have no need to change 489 * the multiplier value. 490 */ 491 value = readl(base + CPG_PLL2CR); 492 mult = (((value >> 24) & 0x7f) + 1) * 2; 493 if (cpg_quirks & PLL_ERRATA) 494 mult *= 2; 495 break; 496 497 case CLK_TYPE_GEN3_PLL3: 498 mult = cpg_pll_config->pll3_mult; 499 div = cpg_pll_config->pll3_div; 500 break; 501 502 case CLK_TYPE_GEN3_PLL4: 503 /* 504 * PLL4 is a configurable multiplier clock. Register it as a 505 * fixed factor clock for now as there's no generic multiplier 506 * clock implementation and we currently have no need to change 507 * the multiplier value. 508 */ 509 value = readl(base + CPG_PLL4CR); 510 mult = (((value >> 24) & 0x7f) + 1) * 2; 511 if (cpg_quirks & PLL_ERRATA) 512 mult *= 2; 513 break; 514 515 case CLK_TYPE_GEN3_SD: 516 return cpg_sd_clk_register(core, base, __clk_get_name(parent), 517 notifiers); 518 519 case CLK_TYPE_GEN3_R: 520 if (cpg_quirks & RCKCR_CKSEL) { 521 struct cpg_simple_notifier *csn; 522 523 csn = kzalloc(sizeof(*csn), GFP_KERNEL); 524 if (!csn) 525 return ERR_PTR(-ENOMEM); 526 527 csn->reg = base + CPG_RCKCR; 528 529 /* 530 * RINT is default. 531 * Only if EXTALR is populated, we switch to it. 532 */ 533 value = readl(csn->reg) & 0x3f; 534 535 if (clk_get_rate(clks[cpg_clk_extalr])) { 536 parent = clks[cpg_clk_extalr]; 537 value |= CPG_RCKCR_CKSEL; 538 } 539 540 writel(value, csn->reg); 541 cpg_simple_notifier_register(notifiers, csn); 542 break; 543 } 544 545 /* Select parent clock of RCLK by MD28 */ 546 if (cpg_mode & BIT(28)) 547 parent = clks[cpg_clk_extalr]; 548 break; 549 550 case CLK_TYPE_GEN3_MDSEL: 551 /* 552 * Clock selectable between two parents and two fixed dividers 553 * using a mode pin 554 */ 555 if (cpg_mode & BIT(core->offset)) { 556 div = core->div & 0xffff; 557 } else { 558 parent = clks[core->parent >> 16]; 559 if (IS_ERR(parent)) 560 return ERR_CAST(parent); 561 div = core->div >> 16; 562 } 563 mult = 1; 564 break; 565 566 case CLK_TYPE_GEN3_Z: 567 return cpg_z_clk_register(core->name, __clk_get_name(parent), 568 base, CPG_FRQCRC_ZFC_MASK); 569 570 case CLK_TYPE_GEN3_Z2: 571 return cpg_z_clk_register(core->name, __clk_get_name(parent), 572 base, CPG_FRQCRC_Z2FC_MASK); 573 574 case CLK_TYPE_GEN3_OSC: 575 /* 576 * Clock combining OSC EXTAL predivider and a fixed divider 577 */ 578 div = cpg_pll_config->osc_prediv * core->div; 579 break; 580 581 case CLK_TYPE_GEN3_RCKSEL: 582 /* 583 * Clock selectable between two parents and two fixed dividers 584 * using RCKCR.CKSEL 585 */ 586 if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) { 587 div = core->div & 0xffff; 588 } else { 589 parent = clks[core->parent >> 16]; 590 if (IS_ERR(parent)) 591 return ERR_CAST(parent); 592 div = core->div >> 16; 593 } 594 break; 595 596 default: 597 return ERR_PTR(-EINVAL); 598 } 599 600 return clk_register_fixed_factor(NULL, core->name, 601 __clk_get_name(parent), 0, mult, div); 602 } 603 604 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 605 unsigned int clk_extalr, u32 mode) 606 { 607 const struct soc_device_attribute *attr; 608 609 cpg_pll_config = config; 610 cpg_clk_extalr = clk_extalr; 611 cpg_mode = mode; 612 attr = soc_device_match(cpg_quirks_match); 613 if (attr) 614 cpg_quirks = (uintptr_t)attr->data; 615 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); 616 return 0; 617 } 618