1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * R-Car Gen2 Clock Pulse Generator
4  *
5  * Copyright (C) 2016 Cogent Embedded Inc.
6  */
7 
8 #ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
9 #define __CLK_RENESAS_RCAR_GEN2_CPG_H__
10 
11 enum rcar_gen2_clk_types {
12 	CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
13 	CLK_TYPE_GEN2_PLL0,
14 	CLK_TYPE_GEN2_PLL1,
15 	CLK_TYPE_GEN2_PLL3,
16 	CLK_TYPE_GEN2_Z,
17 	CLK_TYPE_GEN2_LB,
18 	CLK_TYPE_GEN2_ADSP,
19 	CLK_TYPE_GEN2_SDH,
20 	CLK_TYPE_GEN2_SD0,
21 	CLK_TYPE_GEN2_SD1,
22 	CLK_TYPE_GEN2_QSPI,
23 	CLK_TYPE_GEN2_RCAN,
24 };
25 
26 struct rcar_gen2_cpg_pll_config {
27 	u8 extal_div;
28 	u8 pll1_mult;
29 	u8 pll3_mult;
30 	u8 pll0_mult;		/* leave as zero if PLL0CR exists */
31 };
32 
33 struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
34 	const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
35 	struct clk **clks, void __iomem *base,
36 	struct raw_notifier_head *notifiers);
37 int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
38 		       unsigned int pll0_div, u32 mode);
39 
40 #endif
41