1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G2L CPG driver 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/r9a07g044-cpg.h> 14 15 #include "rzg2l-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2, 20 21 /* External Input Clocks */ 22 CLK_EXTAL, 23 24 /* Internal Core Clocks */ 25 CLK_OSC_DIV1000, 26 CLK_PLL1, 27 CLK_PLL2, 28 CLK_PLL2_DIV2, 29 CLK_PLL2_DIV16, 30 CLK_PLL2_DIV20, 31 CLK_PLL3, 32 CLK_PLL3_400, 33 CLK_PLL3_533, 34 CLK_PLL3_DIV2, 35 CLK_PLL3_DIV2_4, 36 CLK_PLL3_DIV2_4_2, 37 CLK_PLL3_DIV4, 38 CLK_SEL_PLL3_3, 39 CLK_DIV_PLL3_C, 40 CLK_PLL4, 41 CLK_PLL5, 42 CLK_PLL5_FOUT3, 43 CLK_PLL5_250, 44 CLK_PLL6, 45 CLK_PLL6_250, 46 CLK_P1_DIV2, 47 CLK_PLL2_800, 48 CLK_PLL2_SDHI_533, 49 CLK_PLL2_SDHI_400, 50 CLK_PLL2_SDHI_266, 51 CLK_SD0_DIV4, 52 CLK_SD1_DIV4, 53 54 /* Module Clocks */ 55 MOD_CLK_BASE, 56 }; 57 58 /* Divider tables */ 59 static const struct clk_div_table dtable_1_32[] = { 60 {0, 1}, 61 {1, 2}, 62 {2, 4}, 63 {3, 8}, 64 {4, 32}, 65 {0, 0}, 66 }; 67 68 /* Mux clock tables */ 69 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; 70 static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 71 static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 72 73 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 74 /* External Clock Inputs */ 75 DEF_INPUT("extal", CLK_EXTAL), 76 77 /* Internal Core Clocks */ 78 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), 79 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 80 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 81 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), 82 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), 83 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), 84 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), 85 86 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 87 DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), 88 89 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 90 91 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 92 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), 93 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), 94 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), 95 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), 96 97 DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16), 98 DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), 99 100 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 101 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 102 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 103 DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), 104 DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, 105 sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), 106 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, 107 DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 108 109 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), 110 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), 111 112 /* Core output clk */ 113 DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), 114 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, 115 dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 116 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), 117 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), 118 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, 119 DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 120 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), 121 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, 122 DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 123 DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 124 DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), 125 DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, 126 sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), 127 DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), 128 DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), 129 DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, 130 sel_shdi, ARRAY_SIZE(sel_shdi)), 131 DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, 132 sel_shdi, ARRAY_SIZE(sel_shdi)), 133 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), 134 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), 135 }; 136 137 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 138 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, 139 0x514, 0), 140 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, 141 0x518, 0), 142 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 143 0x518, 1), 144 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, 145 0x52c, 0), 146 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, 147 0x52c, 1), 148 DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, 149 0x550, 0), 150 DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, 151 0x550, 1), 152 DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, 153 0x554, 0), 154 DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, 155 0x554, 1), 156 DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, 157 0x554, 2), 158 DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, 159 0x554, 3), 160 DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, 161 0x554, 4), 162 DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, 163 0x554, 5), 164 DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, 165 0x554, 6), 166 DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, 167 0x554, 7), 168 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 169 0x570, 0), 170 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, 171 0x570, 1), 172 DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, 173 0x570, 2), 174 DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, 175 0x570, 3), 176 DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, 177 0x570, 4), 178 DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, 179 0x570, 5), 180 DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, 181 0x570, 6), 182 DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, 183 0x570, 7), 184 DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, 185 0x578, 0), 186 DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, 187 0x578, 1), 188 DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, 189 0x578, 2), 190 DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, 191 0x578, 3), 192 DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, 193 0x57c, 0), 194 DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, 195 0x57c, 0), 196 DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, 197 0x57c, 1), 198 DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, 199 0x57c, 1), 200 DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, 201 0x580, 0), 202 DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, 203 0x580, 1), 204 DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, 205 0x580, 2), 206 DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, 207 0x580, 3), 208 DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, 209 0x584, 0), 210 DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, 211 0x584, 1), 212 DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, 213 0x584, 2), 214 DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, 215 0x584, 3), 216 DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, 217 0x584, 4), 218 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, 219 0x588, 0), 220 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, 221 0x594, 0), 222 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, 223 0x598, 0), 224 DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, 225 0x5a8, 0), 226 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, 227 0x5a8, 1), 228 }; 229 230 static struct rzg2l_reset r9a07g044_resets[] = { 231 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), 232 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), 233 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), 234 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0), 235 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1), 236 DEF_RST(R9A07G044_SPI_RST, 0x850, 0), 237 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0), 238 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1), 239 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0), 240 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1), 241 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2), 242 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3), 243 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0), 244 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1), 245 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2), 246 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3), 247 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0), 248 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1), 249 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0), 250 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1), 251 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2), 252 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3), 253 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0), 254 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1), 255 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2), 256 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3), 257 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4), 258 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0), 259 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0), 260 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1), 261 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0), 262 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1), 263 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2), 264 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0), 265 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1), 266 }; 267 268 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 269 MOD_CLK_BASE + R9A07G044_GIC600_GICCLK, 270 MOD_CLK_BASE + R9A07G044_IA55_CLK, 271 MOD_CLK_BASE + R9A07G044_DMAC_ACLK, 272 }; 273 274 const struct rzg2l_cpg_info r9a07g044_cpg_info = { 275 /* Core Clocks */ 276 .core_clks = r9a07g044_core_clks, 277 .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks), 278 .last_dt_core_clk = LAST_DT_CORE_CLK, 279 .num_total_core_clks = MOD_CLK_BASE, 280 281 /* Critical Module Clocks */ 282 .crit_mod_clks = r9a07g044_crit_mod_clks, 283 .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), 284 285 /* Module Clocks */ 286 .mod_clks = r9a07g044_mod_clks, 287 .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks), 288 .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, 289 290 /* Resets */ 291 .resets = r9a07g044_resets, 292 .num_resets = ARRAY_SIZE(r9a07g044_resets), 293 }; 294