1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RZ/G2L CPG driver 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/r9a07g044-cpg.h> 14 15 #include "renesas-rzg2l-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A07G044_OSCCLK, 20 21 /* External Input Clocks */ 22 CLK_EXTAL, 23 24 /* Internal Core Clocks */ 25 CLK_OSC_DIV1000, 26 CLK_PLL1, 27 CLK_PLL2, 28 CLK_PLL2_DIV2, 29 CLK_PLL2_DIV16, 30 CLK_PLL2_DIV20, 31 CLK_PLL3, 32 CLK_PLL3_DIV2, 33 CLK_PLL3_DIV4, 34 CLK_PLL3_DIV8, 35 CLK_PLL4, 36 CLK_PLL5, 37 CLK_PLL5_DIV2, 38 CLK_PLL6, 39 40 /* Module Clocks */ 41 MOD_CLK_BASE, 42 }; 43 44 /* Divider tables */ 45 static const struct clk_div_table dtable_3b[] = { 46 {0, 1}, 47 {1, 2}, 48 {2, 4}, 49 {3, 8}, 50 {4, 32}, 51 }; 52 53 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 54 /* External Clock Inputs */ 55 DEF_INPUT("extal", CLK_EXTAL), 56 57 /* Internal Core Clocks */ 58 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), 59 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 60 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 61 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), 62 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), 63 64 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 65 DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16), 66 DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), 67 68 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 69 DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), 70 DEF_FIXED(".pll3_div8", CLK_PLL3_DIV8, CLK_PLL3, 1, 8), 71 72 /* Core output clk */ 73 DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), 74 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, 75 dtable_3b, CLK_DIVIDER_HIWORD_MASK), 76 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), 77 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV8, 78 DIVPL3B, dtable_3b, CLK_DIVIDER_HIWORD_MASK), 79 }; 80 81 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 82 DEF_MOD("gic", R9A07G044_CLK_GIC600, 83 R9A07G044_CLK_P1, 84 0x514, BIT(0), (BIT(0) | BIT(1))), 85 DEF_MOD("ia55", R9A07G044_CLK_IA55, 86 R9A07G044_CLK_P1, 87 0x518, (BIT(0) | BIT(1)), BIT(0)), 88 DEF_MOD("scif0", R9A07G044_CLK_SCIF0, 89 R9A07G044_CLK_P0, 90 0x584, BIT(0), BIT(0)), 91 DEF_MOD("scif1", R9A07G044_CLK_SCIF1, 92 R9A07G044_CLK_P0, 93 0x584, BIT(1), BIT(1)), 94 DEF_MOD("scif2", R9A07G044_CLK_SCIF2, 95 R9A07G044_CLK_P0, 96 0x584, BIT(2), BIT(2)), 97 DEF_MOD("scif3", R9A07G044_CLK_SCIF3, 98 R9A07G044_CLK_P0, 99 0x584, BIT(3), BIT(3)), 100 DEF_MOD("scif4", R9A07G044_CLK_SCIF4, 101 R9A07G044_CLK_P0, 102 0x584, BIT(4), BIT(4)), 103 DEF_MOD("sci0", R9A07G044_CLK_SCI0, 104 R9A07G044_CLK_P0, 105 0x588, BIT(0), BIT(0)), 106 }; 107 108 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 109 MOD_CLK_BASE + R9A07G044_CLK_GIC600, 110 }; 111 112 const struct rzg2l_cpg_info r9a07g044_cpg_info = { 113 /* Core Clocks */ 114 .core_clks = r9a07g044_core_clks, 115 .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks), 116 .last_dt_core_clk = LAST_DT_CORE_CLK, 117 .num_total_core_clks = MOD_CLK_BASE, 118 119 /* Critical Module Clocks */ 120 .crit_mod_clks = r9a07g044_crit_mod_clks, 121 .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), 122 123 /* Module Clocks */ 124 .mod_clks = r9a07g044_mod_clks, 125 .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks), 126 .num_hw_mod_clks = R9A07G044_CLK_MIPI_DSI_PIN + 1, 127 }; 128