1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * RZ/G2UL CPG driver
4  *
5  * Copyright (C) 2022 Renesas Electronics Corp.
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/device.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 
13 #include <dt-bindings/clock/r9a07g043-cpg.h>
14 
15 #include "rzg2l-cpg.h"
16 
17 enum clk_ids {
18 	/* Core Clock Outputs exported to DT */
19 	LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,
20 
21 	/* External Input Clocks */
22 	CLK_EXTAL,
23 
24 	/* Internal Core Clocks */
25 	CLK_OSC_DIV1000,
26 	CLK_PLL1,
27 	CLK_PLL2,
28 	CLK_PLL2_DIV2,
29 	CLK_PLL2_DIV2_8,
30 	CLK_PLL2_DIV2_10,
31 	CLK_PLL3,
32 	CLK_PLL3_400,
33 	CLK_PLL3_533,
34 	CLK_PLL3_DIV2,
35 	CLK_PLL3_DIV2_4,
36 	CLK_PLL3_DIV2_4_2,
37 	CLK_SEL_PLL3_3,
38 	CLK_DIV_PLL3_C,
39 #ifdef CONFIG_ARM64
40 	CLK_PLL5,
41 	CLK_PLL5_500,
42 	CLK_PLL5_250,
43 #endif
44 	CLK_PLL6,
45 	CLK_PLL6_250,
46 	CLK_P1_DIV2,
47 	CLK_PLL2_800,
48 	CLK_PLL2_SDHI_533,
49 	CLK_PLL2_SDHI_400,
50 	CLK_PLL2_SDHI_266,
51 	CLK_SD0_DIV4,
52 	CLK_SD1_DIV4,
53 
54 	/* Module Clocks */
55 	MOD_CLK_BASE,
56 };
57 
58 /* Divider tables */
59 static const struct clk_div_table dtable_1_8[] = {
60 	{0, 1},
61 	{1, 2},
62 	{2, 4},
63 	{3, 8},
64 	{0, 0},
65 };
66 
67 static const struct clk_div_table dtable_1_32[] = {
68 	{0, 1},
69 	{1, 2},
70 	{2, 4},
71 	{3, 8},
72 	{4, 32},
73 	{0, 0},
74 };
75 
76 /* Mux clock tables */
77 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
78 static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };
79 static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
80 
81 static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
82 	/* External Clock Inputs */
83 	DEF_INPUT("extal", CLK_EXTAL),
84 
85 	/* Internal Core Clocks */
86 	DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
87 	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
88 	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
89 	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
90 	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
91 	DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
92 	DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
93 	DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
94 	DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
95 	DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
96 	DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
97 	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
98 	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
99 	DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
100 	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
101 	DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
102 	DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
103 	DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
104 	DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
105 #ifdef CONFIG_ARM64
106 	DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
107 	DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
108 	DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
109 #endif
110 	DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
111 	DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
112 
113 	/* Core output clk */
114 	DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
115 	DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
116 	DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
117 	DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
118 	DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
119 	DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
120 	DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
121 	DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
122 	DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
123 	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
124 	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
125 	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
126 	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi),
127 	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi),
128 	DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
129 	DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
130 };
131 
132 static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
133 #ifdef CONFIG_ARM64
134 	DEF_MOD("gic",		R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
135 				0x514, 0),
136 	DEF_MOD("ia55_pclk",	R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
137 				0x518, 0),
138 	DEF_MOD("ia55_clk",	R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
139 				0x518, 1),
140 #endif
141 #ifdef CONFIG_RISCV
142 	DEF_MOD("iax45_pclk",	R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
143 				0x518, 0),
144 	DEF_MOD("iax45_clk",	R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
145 				0x518, 1),
146 #endif
147 	DEF_MOD("dmac_aclk",	R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
148 				0x52c, 0),
149 	DEF_MOD("dmac_pclk",	R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
150 				0x52c, 1),
151 	DEF_MOD("ostm0_pclk",	R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
152 				0x534, 0),
153 	DEF_MOD("ostm1_pclk",	R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
154 				0x534, 1),
155 	DEF_MOD("ostm2_pclk",	R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
156 				0x534, 2),
157 	DEF_MOD("wdt0_pclk",	R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
158 				0x548, 0),
159 	DEF_MOD("wdt0_clk",	R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
160 				0x548, 1),
161 	DEF_MOD("wdt2_pclk",	R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
162 				0x548, 4),
163 	DEF_MOD("wdt2_clk",	R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
164 				0x548, 5),
165 	DEF_MOD("spi_clk2",	R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
166 				0x550, 0),
167 	DEF_MOD("spi_clk",	R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
168 				0x550, 1),
169 	DEF_MOD("sdhi0_imclk",	R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
170 				0x554, 0),
171 	DEF_MOD("sdhi0_imclk2",	R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
172 				0x554, 1),
173 	DEF_MOD("sdhi0_clk_hs",	R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0,
174 				0x554, 2),
175 	DEF_MOD("sdhi0_aclk",	R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1,
176 				0x554, 3),
177 	DEF_MOD("sdhi1_imclk",	R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4,
178 				0x554, 4),
179 	DEF_MOD("sdhi1_imclk2",	R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4,
180 				0x554, 5),
181 	DEF_MOD("sdhi1_clk_hs",	R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1,
182 				0x554, 6),
183 	DEF_MOD("sdhi1_aclk",	R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
184 				0x554, 7),
185 	DEF_MOD("ssi0_pclk",	R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,
186 				0x570, 0),
187 	DEF_MOD("ssi0_sfr",	R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,
188 				0x570, 1),
189 	DEF_MOD("ssi1_pclk",	R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,
190 				0x570, 2),
191 	DEF_MOD("ssi1_sfr",	R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,
192 				0x570, 3),
193 	DEF_MOD("ssi2_pclk",	R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,
194 				0x570, 4),
195 	DEF_MOD("ssi2_sfr",	R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,
196 				0x570, 5),
197 	DEF_MOD("ssi3_pclk",	R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,
198 				0x570, 6),
199 	DEF_MOD("ssi3_sfr",	R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
200 				0x570, 7),
201 	DEF_MOD("usb0_host",	R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
202 				0x578, 0),
203 	DEF_MOD("usb1_host",	R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
204 				0x578, 1),
205 	DEF_MOD("usb0_func",	R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
206 				0x578, 2),
207 	DEF_MOD("usb_pclk",	R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
208 				0x578, 3),
209 	DEF_COUPLED("eth0_axi",	R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
210 				0x57c, 0),
211 	DEF_COUPLED("eth0_chi",	R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
212 				0x57c, 0),
213 	DEF_COUPLED("eth1_axi",	R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
214 				0x57c, 1),
215 	DEF_COUPLED("eth1_chi",	R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
216 				0x57c, 1),
217 	DEF_MOD("i2c0",		R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0,
218 				0x580, 0),
219 	DEF_MOD("i2c1",		R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0,
220 				0x580, 1),
221 	DEF_MOD("i2c2",		R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0,
222 				0x580, 2),
223 	DEF_MOD("i2c3",		R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0,
224 				0x580, 3),
225 	DEF_MOD("scif0",	R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
226 				0x584, 0),
227 	DEF_MOD("scif1",	R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
228 				0x584, 1),
229 	DEF_MOD("scif2",	R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
230 				0x584, 2),
231 	DEF_MOD("scif3",	R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
232 				0x584, 3),
233 	DEF_MOD("scif4",	R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
234 				0x584, 4),
235 	DEF_MOD("sci0",		R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
236 				0x588, 0),
237 	DEF_MOD("sci1",		R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
238 				0x588, 1),
239 	DEF_MOD("rspi0",	R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0,
240 				0x590, 0),
241 	DEF_MOD("rspi1",	R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0,
242 				0x590, 1),
243 	DEF_MOD("rspi2",	R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0,
244 				0x590, 2),
245 	DEF_MOD("canfd",	R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
246 				0x594, 0),
247 	DEF_MOD("gpio",		R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
248 				0x598, 0),
249 	DEF_MOD("adc_adclk",	R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,
250 				0x5a8, 0),
251 	DEF_MOD("adc_pclk",	R9A07G043_ADC_PCLK, R9A07G043_CLK_P0,
252 				0x5a8, 1),
253 	DEF_MOD("tsu_pclk",	R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
254 				0x5ac, 0),
255 };
256 
257 static struct rzg2l_reset r9a07g043_resets[] = {
258 #ifdef CONFIG_ARM64
259 	DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
260 	DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
261 	DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
262 #endif
263 #ifdef CONFIG_RISCV
264 	DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
265 #endif
266 	DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
267 	DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
268 	DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
269 	DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
270 	DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
271 	DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
272 	DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
273 	DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
274 	DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
275 	DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
276 	DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
277 	DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
278 	DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
279 	DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
280 	DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
281 	DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
282 	DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
283 	DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
284 	DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
285 	DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
286 	DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
287 	DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),
288 	DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),
289 	DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),
290 	DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
291 	DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
292 	DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
293 	DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
294 	DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
295 	DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
296 	DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
297 	DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),
298 	DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),
299 	DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),
300 	DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
301 	DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
302 	DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
303 	DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
304 	DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
305 	DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
306 	DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
307 	DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
308 };
309 
310 static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
311 #ifdef CONFIG_ARM64
312 	MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
313 	MOD_CLK_BASE + R9A07G043_IA55_CLK,
314 #endif
315 #ifdef CONFIG_RISCV
316 	MOD_CLK_BASE + R9A07G043_IAX45_CLK,
317 #endif
318 	MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
319 };
320 
321 const struct rzg2l_cpg_info r9a07g043_cpg_info = {
322 	/* Core Clocks */
323 	.core_clks = r9a07g043_core_clks,
324 	.num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
325 	.last_dt_core_clk = LAST_DT_CORE_CLK,
326 	.num_total_core_clks = MOD_CLK_BASE,
327 
328 	/* Critical Module Clocks */
329 	.crit_mod_clks = r9a07g043_crit_mod_clks,
330 	.num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
331 
332 	/* Module Clocks */
333 	.mod_clks = r9a07g043_mod_clks,
334 	.num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
335 #ifdef CONFIG_ARM64
336 	.num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,
337 #endif
338 #ifdef CONFIG_RISCV
339 	.num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1,
340 #endif
341 
342 	/* Resets */
343 	.resets = r9a07g043_resets,
344 #ifdef CONFIG_ARM64
345 	.num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */
346 #endif
347 #ifdef CONFIG_RISCV
348 	.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
349 #endif
350 
351 	.has_clk_mon_regs = true,
352 };
353