1c8b08822SBiju Das // SPDX-License-Identifier: GPL-2.0 2c8b08822SBiju Das /* 3c8b08822SBiju Das * RZ/G2UL CPG driver 4c8b08822SBiju Das * 5c8b08822SBiju Das * Copyright (C) 2022 Renesas Electronics Corp. 6c8b08822SBiju Das */ 7c8b08822SBiju Das 8c8b08822SBiju Das #include <linux/clk-provider.h> 9c8b08822SBiju Das #include <linux/device.h> 10c8b08822SBiju Das #include <linux/init.h> 11c8b08822SBiju Das #include <linux/kernel.h> 12c8b08822SBiju Das 13c8b08822SBiju Das #include <dt-bindings/clock/r9a07g043-cpg.h> 14c8b08822SBiju Das 15c8b08822SBiju Das #include "rzg2l-cpg.h" 16c8b08822SBiju Das 17c8b08822SBiju Das enum clk_ids { 18c8b08822SBiju Das /* Core Clock Outputs exported to DT */ 19c8b08822SBiju Das LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, 20c8b08822SBiju Das 21c8b08822SBiju Das /* External Input Clocks */ 22c8b08822SBiju Das CLK_EXTAL, 23c8b08822SBiju Das 24c8b08822SBiju Das /* Internal Core Clocks */ 25c8b08822SBiju Das CLK_OSC_DIV1000, 26c8b08822SBiju Das CLK_PLL1, 27c8b08822SBiju Das CLK_PLL2, 28c8b08822SBiju Das CLK_PLL2_DIV2, 29c8b08822SBiju Das CLK_PLL2_DIV2_8, 30c8b08822SBiju Das CLK_PLL3, 31c8b08822SBiju Das CLK_PLL3_DIV2, 32c8b08822SBiju Das CLK_PLL3_DIV2_4, 33c8b08822SBiju Das CLK_PLL3_DIV2_4_2, 34c8b08822SBiju Das CLK_PLL5, 35f201eb84SBiju Das CLK_PLL5_500, 36f201eb84SBiju Das CLK_PLL5_250, 37c8b08822SBiju Das CLK_PLL6, 38f201eb84SBiju Das CLK_PLL6_250, 39c8b08822SBiju Das CLK_P1_DIV2, 4059086e41SBiju Das CLK_PLL2_800, 4159086e41SBiju Das CLK_PLL2_SDHI_533, 4259086e41SBiju Das CLK_PLL2_SDHI_400, 4359086e41SBiju Das CLK_PLL2_SDHI_266, 4459086e41SBiju Das CLK_SD0_DIV4, 4559086e41SBiju Das CLK_SD1_DIV4, 46c8b08822SBiju Das 47c8b08822SBiju Das /* Module Clocks */ 48c8b08822SBiju Das MOD_CLK_BASE, 49c8b08822SBiju Das }; 50c8b08822SBiju Das 51c8b08822SBiju Das /* Divider tables */ 52c8b08822SBiju Das static const struct clk_div_table dtable_1_8[] = { 53c8b08822SBiju Das {0, 1}, 54c8b08822SBiju Das {1, 2}, 55c8b08822SBiju Das {2, 4}, 56c8b08822SBiju Das {3, 8}, 57c8b08822SBiju Das {0, 0}, 58c8b08822SBiju Das }; 59c8b08822SBiju Das 60c8b08822SBiju Das static const struct clk_div_table dtable_1_32[] = { 61c8b08822SBiju Das {0, 1}, 62c8b08822SBiju Das {1, 2}, 63c8b08822SBiju Das {2, 4}, 64c8b08822SBiju Das {3, 8}, 65c8b08822SBiju Das {4, 32}, 66c8b08822SBiju Das {0, 0}, 67c8b08822SBiju Das }; 68c8b08822SBiju Das 69f201eb84SBiju Das /* Mux clock tables */ 70f201eb84SBiju Das static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; 7159086e41SBiju Das static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 72f201eb84SBiju Das 73c8b08822SBiju Das static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 74c8b08822SBiju Das /* External Clock Inputs */ 75c8b08822SBiju Das DEF_INPUT("extal", CLK_EXTAL), 76c8b08822SBiju Das 77c8b08822SBiju Das /* Internal Core Clocks */ 78c8b08822SBiju Das DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1), 79c8b08822SBiju Das DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), 80c8b08822SBiju Das DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), 81c8b08822SBiju Das DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), 82c8b08822SBiju Das DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), 8359086e41SBiju Das DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), 8459086e41SBiju Das DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), 8559086e41SBiju Das DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), 8659086e41SBiju Das DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), 87c8b08822SBiju Das DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), 88c8b08822SBiju Das DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), 89c8b08822SBiju Das DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), 90c8b08822SBiju Das DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), 91c8b08822SBiju Das DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), 92c8b08822SBiju Das DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), 93f201eb84SBiju Das DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6), 94f201eb84SBiju Das DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2), 95c8b08822SBiju Das DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), 96f201eb84SBiju Das DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), 97c8b08822SBiju Das 98c8b08822SBiju Das /* Core output clk */ 99c8b08822SBiju Das DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, 100c8b08822SBiju Das CLK_DIVIDER_HIWORD_MASK), 101c8b08822SBiju Das DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, 102c8b08822SBiju Das dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 103c8b08822SBiju Das DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, 104c8b08822SBiju Das DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 105c8b08822SBiju Das DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), 106c8b08822SBiju Das DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, 107c8b08822SBiju Das DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), 108f201eb84SBiju Das DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), 109f201eb84SBiju Das DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), 110f201eb84SBiju Das DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, 111f201eb84SBiju Das sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), 11259086e41SBiju Das DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, 11359086e41SBiju Das sel_shdi, ARRAY_SIZE(sel_shdi)), 11459086e41SBiju Das DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, 11559086e41SBiju Das sel_shdi, ARRAY_SIZE(sel_shdi)), 11659086e41SBiju Das DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), 11759086e41SBiju Das DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), 118c8b08822SBiju Das }; 119c8b08822SBiju Das 120c8b08822SBiju Das static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 121c8b08822SBiju Das DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 122c8b08822SBiju Das 0x514, 0), 123c8b08822SBiju Das DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 124c8b08822SBiju Das 0x518, 0), 125c8b08822SBiju Das DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 126c8b08822SBiju Das 0x518, 1), 127c8b08822SBiju Das DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 128c8b08822SBiju Das 0x52c, 0), 129c8b08822SBiju Das DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 130c8b08822SBiju Das 0x52c, 1), 13159086e41SBiju Das DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 13259086e41SBiju Das 0x554, 0), 13359086e41SBiju Das DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, 13459086e41SBiju Das 0x554, 1), 13559086e41SBiju Das DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0, 13659086e41SBiju Das 0x554, 2), 13759086e41SBiju Das DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1, 13859086e41SBiju Das 0x554, 3), 13959086e41SBiju Das DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4, 14059086e41SBiju Das 0x554, 4), 14159086e41SBiju Das DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4, 14259086e41SBiju Das 0x554, 5), 14359086e41SBiju Das DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1, 14459086e41SBiju Das 0x554, 6), 14559086e41SBiju Das DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 14659086e41SBiju Das 0x554, 7), 147e11f804aSBiju Das DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 148e11f804aSBiju Das 0x57c, 0), 149e11f804aSBiju Das DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, 150e11f804aSBiju Das 0x57c, 0), 151e11f804aSBiju Das DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0, 152e11f804aSBiju Das 0x57c, 1), 153e11f804aSBiju Das DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, 154e11f804aSBiju Das 0x57c, 1), 155*a9391e01SBiju Das DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, 156*a9391e01SBiju Das 0x580, 0), 157*a9391e01SBiju Das DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, 158*a9391e01SBiju Das 0x580, 1), 159*a9391e01SBiju Das DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, 160*a9391e01SBiju Das 0x580, 2), 161*a9391e01SBiju Das DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, 162*a9391e01SBiju Das 0x580, 3), 163c8b08822SBiju Das DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 164c8b08822SBiju Das 0x584, 0), 165c8b08822SBiju Das DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, 166c8b08822SBiju Das 0x584, 1), 167c8b08822SBiju Das DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, 168c8b08822SBiju Das 0x584, 2), 169c8b08822SBiju Das DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, 170c8b08822SBiju Das 0x584, 3), 171c8b08822SBiju Das DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, 172c8b08822SBiju Das 0x584, 4), 173c8b08822SBiju Das DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, 174c8b08822SBiju Das 0x588, 0), 175c8b08822SBiju Das DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 176c8b08822SBiju Das 0x588, 1), 1776c185664SBiju Das DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 1786c185664SBiju Das 0x598, 0), 179c8b08822SBiju Das }; 180c8b08822SBiju Das 181c8b08822SBiju Das static struct rzg2l_reset r9a07g043_resets[] = { 182c8b08822SBiju Das DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), 183c8b08822SBiju Das DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), 184c8b08822SBiju Das DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), 185c8b08822SBiju Das DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), 186c8b08822SBiju Das DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), 18759086e41SBiju Das DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), 18859086e41SBiju Das DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), 189e11f804aSBiju Das DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), 190e11f804aSBiju Das DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), 191*a9391e01SBiju Das DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), 192*a9391e01SBiju Das DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1), 193*a9391e01SBiju Das DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2), 194*a9391e01SBiju Das DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3), 195c8b08822SBiju Das DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), 196c8b08822SBiju Das DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), 197c8b08822SBiju Das DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), 198c8b08822SBiju Das DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3), 199c8b08822SBiju Das DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), 200c8b08822SBiju Das DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), 201c8b08822SBiju Das DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), 2026c185664SBiju Das DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), 2036c185664SBiju Das DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), 2046c185664SBiju Das DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), 205c8b08822SBiju Das }; 206c8b08822SBiju Das 207c8b08822SBiju Das static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { 208c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, 209c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_IA55_CLK, 210c8b08822SBiju Das MOD_CLK_BASE + R9A07G043_DMAC_ACLK, 211c8b08822SBiju Das }; 212c8b08822SBiju Das 213c8b08822SBiju Das const struct rzg2l_cpg_info r9a07g043_cpg_info = { 214c8b08822SBiju Das /* Core Clocks */ 215c8b08822SBiju Das .core_clks = r9a07g043_core_clks, 216c8b08822SBiju Das .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks), 217c8b08822SBiju Das .last_dt_core_clk = LAST_DT_CORE_CLK, 218c8b08822SBiju Das .num_total_core_clks = MOD_CLK_BASE, 219c8b08822SBiju Das 220c8b08822SBiju Das /* Critical Module Clocks */ 221c8b08822SBiju Das .crit_mod_clks = r9a07g043_crit_mod_clks, 222c8b08822SBiju Das .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks), 223c8b08822SBiju Das 224c8b08822SBiju Das /* Module Clocks */ 225c8b08822SBiju Das .mod_clks = r9a07g043_mod_clks, 226c8b08822SBiju Das .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), 227c8b08822SBiju Das .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, 228c8b08822SBiju Das 229c8b08822SBiju Das /* Resets */ 230c8b08822SBiju Das .resets = r9a07g043_resets, 231c8b08822SBiju Das .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ 232c8b08822SBiju Das }; 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